专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US08068576B2 Counters and exemplary applications 有权
标题翻译：计数器和示范应用
公开(公告)号：US08068576B2
公开(公告)日：2011-11-29
申请号：US12699458
申请日：2010-02-03
申请人： Chih-Chang Lin , Tien-Chun Yang , Steven Swei
发明人： Chih-Chang Lin , Tien-Chun Yang , Steven Swei
IPC分类号： H03K21/00
CPC分类号： H03K21/38
摘要： Embodiments described herein are related to a counter. In some embodiments, the counter can be used as a divider, e.g., in a fractional PLL. In some embodiments, the counter (e.g., the main counter or counter C) includes a first counter (e.g., counter C1) and a second counter (e.g., counter C2), which, together with the first counter C1, perform the counting function for counter C. For example, if counter C is to count to the value N, then counter C1 counts, e.g., to N1, and counter C2 counts to N2 where N=N1+N2. For counter C1 to count to N1, N1 is loaded to counter C1. Similarly, for counter C2 to count to N2, N2 is loaded to counter C2. While counter C1 counts (e.g., to N1), N2 can be loaded to counter C2. After counter C1 finishes counting to N1, N2, if loaded, is available for counter C2 to start counting to this N2. Counters C1 and C2 can alternately count and thus provide continuous counting for counter C. Other embodiments and exemplary applications are also disclosed.
摘要翻译：本文描述的实施例涉及计数器。在一些实施例中，计数器可以用作分频器，例如在分数PLL中。在一些实施例中，计数器（例如，主计数器或计数器C）包括第一计数器（例如，计数器C1）和第二计数器（例如，计数器C2），其与第一计数器C1一起执行计数功能对于计数器C.例如，如果计数器C计数到值N，则计数器C1计数，例如，到N1，并且计数器C2计数到N2，其中N = N1 + N2。对于计数器C1计数到N1，N1被加载到计数器C1。类似地，对于计数器C2计数到N2，N2被加载到计数器C2。当计数器C1计数（例如，到N1）时，可以将N2加载到计数器C2。在计数器C1结束计数到N1之后，N2（如果加载）可用于计数器C2开始计数到这个N2。计数器C1和C2可以交替地计数并因此为计数器C提供连续计数。还公开了其他实施例和示例性应用。

52. 发明申请

US20110199152A1 INTEGRATED CIRCUITS INCLUDING A CHARGE PUMP CIRCUIT AND OPERATING METHODS THEREOF 有权
标题翻译：集成电路，包括充电泵电路及其工作方法
公开(公告)号：US20110199152A1
公开(公告)日：2011-08-18
申请号：US12706886
申请日：2010-02-17
申请人： Steven SWEI , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
发明人： Steven SWEI , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
IPC分类号： G05F1/10
CPC分类号： G05F1/10 , G05F3/02 , H03L7/0895 , H03L7/0896 , H03L7/0898
摘要： An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.
摘要翻译：集成电路包括第一电流源。第二电流源经由导线与第一电流源电耦合。开关电路耦合在第一电流源和第二电流源之间。第一电路耦合在第一节点和第二节点之间。第一节点设置在第一电流源和开关电路之间。第二节点与第一电流源耦合。第一电路被配置为基本上均衡第一节点和第二节点上的电压。第二电路耦合在第三节点和第四节点之间。第三节点设置在第二电流源和开关电路之间。第四节点被布置成与第二电流源耦合。第二电路被配置为基本上均衡第三节点和第四节点上的电压。

53. 发明授权

US07026843B1 Flexible cascode amplifier circuit with high gain for flash memory cells 有权
标题翻译：闪存单元具有高增益的灵活的共源共栅放大器电路
公开(公告)号：US07026843B1
公开(公告)日：2006-04-11
申请号：US10759855
申请日：2004-01-16
申请人： Tien-Chun Yang , Pau-Ling Chen
发明人： Tien-Chun Yang , Pau-Ling Chen
IPC分类号： G01R19/00
CPC分类号： G11C16/26 , G11C7/062
摘要： An exemplary cascode amplifier circuit comprises a first intrinsic FET, a second intrinsic FET, a third intrinsic FET, and a fourth FET. The first intrinsic FET has a source connected to a target memory cell via a bit line and a drain connected to a first node. The second intrinsic FET has a gate connected to the source of the first intrinsic FET and a source connected to a reference voltage. The second intrinsic FET also has a drain connected at a second node to a gate of the first intrinsic FET. The third intrinsic FET has a source connected to the first node and a gate connected to a supply voltage, and further provides a load across the supply voltage and the first node. The fourth FET has a source connected to the second node and a drain connected to the supply voltage, the fourth FET having a gate connected to an input control voltage.
摘要翻译：示例性共源共栅放大器电路包括第一本征FET，第二本征FET，第三本征FET和第四FET。第一本征FET具有经由位线连接到目标存储器单元的源极和连接到第一节点的漏极。第二本征FET具有连接到第一本征FET的源极的栅极和连接到参考电压的源极。第二本征FET还具有在第二节点处连接到第一本征FET的栅极的漏极。第三本征FET具有连接到第一节点的源极和连接到电源电压的栅极，并且进一步在电源电压和第一节点之间提供负载。第四FET具有连接到第二节点的源极和连接到电源电压的漏极，第四FET具有连接到输入控制电压的栅极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式