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51. 发明申请

US20130069134A1 MEMORY INCLUDING TRANSISTORS WITH DOUBLE FLOATING GATE STRUCTURES 失效
标题翻译：包含两个浮动门结构的晶体管的存储器
公开(公告)号：US20130069134A1
公开(公告)日：2013-03-21
申请号：US13608436
申请日：2012-09-10
申请人： Tetsufumi TANAMOTO , Kosuke Tatsumura , Kiwamu Sakuma , Atsuhiro Kinoshita , Shinobu Fujita , Koichi Muraoka
发明人： Tetsufumi TANAMOTO , Kosuke Tatsumura , Kiwamu Sakuma , Atsuhiro Kinoshita , Shinobu Fujita , Koichi Muraoka
IPC分类号： H01L27/11
CPC分类号： H01L29/42332 , G11C11/412 , G11C14/0063 , H01L27/1104 , H01L29/7881
摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.
摘要翻译：在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极，第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜，第四浮栅，第六绝缘膜和第二控制栅极。

52. 发明授权

US08299507B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08299507B2
公开(公告)日：2012-10-30
申请号：US12714841
申请日：2010-03-01
申请人： Tatsuo Shimizu , Atsuhiro Kinoshita
发明人： Tatsuo Shimizu , Atsuhiro Kinoshita
IPC分类号： H01L29/78
CPC分类号： H01L29/6659 , H01L21/28176 , H01L21/283 , H01L21/28518 , H01L21/2855 , H01L21/28556 , H01L21/31604 , H01L28/75 , H01L29/41775 , H01L29/45 , H01L29/456 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/7881
摘要： It is made possible to optimize the effective work function of the metal for a junction and suppress the resistance as far as possible at the interface between a semiconductor or a dielectric material and a metal. A semiconductor device includes: a semiconductor film; a Ti oxide film formed on the semiconductor film, and including at least one element selected from the group consisting of V, Cr, Mn, Fe, Co, Ni, Nb, Mo, Tc, Ru, Rh, Pd, Ta, W, Re, Os, Ir, and Pt; and a metal film formed on the Ti oxide film.
摘要翻译：可以优化用于结的金属的有效功函数，并且尽可能地在半导体或电介质材料与金属之间的界面处抑制电阻。半导体器件包括：半导体膜; 形成在所述半导体膜上的Ti氧化膜，并且包括选自V，Cr，Mn，Fe，Co，Ni，Nb，Mo，Tc，Ru，Rh，Pd，Ta，W中的至少一种元素， Re，Os，Ir和Pt; 以及形成在Ti氧化物膜上的金属膜。

53. 发明申请

US20120139030A1 NONVOLATILE SEMICONDUCTOR MEMORY 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20120139030A1
公开(公告)日：2012-06-07
申请号：US13316603
申请日：2011-12-12
申请人： Kiwamu SAKUMA , Atsuhiro Kinoshita , Masahiro Kiyotoshi , Daisuke Hagishima , Koichi Muraoka
发明人： Kiwamu SAKUMA , Atsuhiro Kinoshita , Masahiro Kiyotoshi , Daisuke Hagishima , Koichi Muraoka
IPC分类号： H01L27/105 , H01L21/8239
CPC分类号： H01L29/42328 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer.
摘要翻译：根据一个实施例，非易失性半导体存储器包括在第一方向上的第一至第n（n是不小于2的自然数）半导体层，并且在第二方向上延伸，并且半导体层具有阶梯状图案第二方向的第一端，在第二方向的第一端中共同连接到第一至第n半导体层的公共半导体层，第一至第n层选择晶体管，其从第一电极侧第一电极和第一至第n存储器串以及使第i层选择晶体管（i为1至n之一）的第一至第n杂质区在第一端中的正常导通状态第i个半导体层的第2方向。

54. 发明申请

US20120117354A1 STORAGE DEVICE IN WHICH FORWARDING-FUNCTION-EQUIPPED MEMORY NODES ARE MUTUALLY CONNECTED AND DATA PROCESSING METHOD 有权
标题翻译：存储设备，其中前向功能的存储器端口被连接和数据处理方法
公开(公告)号：US20120117354A1
公开(公告)日：2012-05-10
申请号：US13293399
申请日：2011-11-10
申请人： Kosuke Tatsumura , Atsuhiro Kinoshita , Hirotaka Nishino , Masamichi Suzuki , Yoshifumi Nishi , Takao Marukame , Takahiro Kurita
发明人： Kosuke Tatsumura , Atsuhiro Kinoshita , Hirotaka Nishino , Masamichi Suzuki , Yoshifumi Nishi , Takao Marukame , Takahiro Kurita
IPC分类号： G06F12/02
CPC分类号： H04L49/253 , G06F3/0605 , G06F3/0635 , G06F3/0656 , G06F3/0658 , G06F3/0683 , H04L12/6418 , H04L45/74
摘要： According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
摘要翻译：根据一个实施例，存储设备包括多个存储器节点。每个存储器节点包括多个输入端口，多个输出端口，选择器，分组控制器和存储器。选择器将输入到输入端口的数据包输出输出到其中一个输出端口。分组控制器控制选择器。内存存储数据。存储器节点在输入端口和输出端口相互连接。存储器节点具有由其物理位置确定的地址。当接收到没有寻址到具有分组控制器的存储器节点的分组时，分组控制器基于包括分组的目的地地址的信息和具有分组控制器的存储器节点的地址来切换输出分组的输出端口。

55. 发明申请

US20120077341A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20120077341A1
公开(公告)日：2012-03-29
申请号：US13081629
申请日：2011-04-07
申请人： Yoshifumi Nishi , Atsuhiro Kinoshita , Hirotaka Nishino , Masamichi Suzuki
发明人： Yoshifumi Nishi , Atsuhiro Kinoshita , Hirotaka Nishino , Masamichi Suzuki
IPC分类号： H01L21/283
CPC分类号： H01L21/28518 , H01L29/1608 , H01L29/41708 , H01L29/456 , H01L29/6606 , H01L29/66068 , H01L29/6609 , H01L29/66272 , H01L29/665 , H01L29/6659 , H01L29/66712 , H01L29/732 , H01L29/7833 , H01L29/861
摘要： In a semiconductor device manufacturing method according to an exemplary embodiment, a sulfur-containing film containing sulfur is deposited on an n-type semiconductor, a first metal film containing a first metal is deposited on the sulfur-containing film, a heat treatment is performed to form a metal semiconductor compound film by reacting the n-type semiconductor and the sulfur-containing film, and to introduce sulfur to an interface between the n-type semiconductor and the metal semiconductor compound film being formed.
摘要翻译：在根据示例性实施例的半导体器件制造方法中，在n型半导体上沉积含硫的含硫膜，在含硫膜上沉积含有第一金属的第一金属膜，进行热处理通过使n型半导体和含硫膜反应形成金属半导体化合物膜，并将硫引入到正在形成的n型半导体和金属半导体化合物膜之间的界面上。

56. 发明申请

US20120061731A1 NONVOLATILE PROGRAMMABLE LOGIC SWITCHES AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：非易失性可编程逻辑开关和半导体集成电路
公开(公告)号：US20120061731A1
公开(公告)日：2012-03-15
申请号：US13223331
申请日：2011-09-01
申请人： Daisuke Hagishima , Atsuhiro Kinoshita
发明人： Daisuke Hagishima , Atsuhiro Kinoshita
IPC分类号： H01L27/092
CPC分类号： H01L29/788 , G11C16/0416 , G11C16/0466 , H01L27/11521 , H01L27/11526 , H01L27/11534 , H01L27/11807
摘要： A nonvolatile programmable logic switch according to an embodiment includes: a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type; a memory cell transistor including a first insulating film formed on the first semiconductor region, a charge storage film formed on the first insulating film, a second insulating film formed on the charge storage film, and a control gate formed on the second insulating film; a pass transistor including a third insulating film formed on the second semiconductor region, and a gate electrode formed on the third insulating film and electrically connected to the first drain region; a first electrode applying a substrate bias to the first semiconductor region, the first electrode being formed in the first semiconductor region; and a second electrode applying a substrate bias to the second semiconductor region, the second electrode being formed in the second semiconductor region.
摘要翻译：根据实施例的非易失性可编程逻辑开关包括：第一导电类型的第一半导体区域和第二导电类型的第二半导体区域; 存储单元晶体管，包括形成在第一半导体区域上的第一绝缘膜，形成在第一绝缘膜上的电荷存储膜，形成在电荷存储膜上的第二绝缘膜，以及形成在第二绝缘膜上的控制栅; 包括形成在第二半导体区域上的第三绝缘膜的通过晶体管和形成在第三绝缘膜上并电连接到第一漏极区的栅电极; 将第一电极施加到所述第一半导体区域的衬底偏压，所述第一电极形成在所述第一半导体区域中; 以及向所述第二半导体区域施加衬底偏压的第二电极，所述第二电极形成在所述第二半导体区域中。

57. 发明授权

US07977729B2 Aging device 有权
标题翻译：老化设备
公开(公告)号：US07977729B2
公开(公告)日：2011-07-12
申请号：US12173535
申请日：2008-07-15
申请人： Hiroshi Watanabe , Atsuhiro Kinoshita , Shigeki Kobayashi , Daisuke Hagishima
发明人： Hiroshi Watanabe , Atsuhiro Kinoshita , Shigeki Kobayashi , Daisuke Hagishima
IPC分类号： H01L29/788
CPC分类号： G04F10/10 , G11C16/0408 , G11C2216/10 , H01L21/28273 , H01L27/115 , H01L27/11558 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： An aging device according to an embodiment of the present invention includes a semiconductor substrate, first and second diffusion layers provided in a first element region, a floating gate provided above a channel region between the first and second diffusion layers, and a control gate electrode provided beside the floating gate with an interval in the lateral direction. A coupling capacitance between the floating gate and the control gate electrode is larger than a coupling capacitance between the floating gate and the semiconductor substrate.
摘要翻译：根据本发明的实施例的老化装置包括半导体衬底，设置在第一元件区域中的第一和第二扩散层，设置在第一和第二扩散层之间的沟道区域上方的浮动栅极和设置在第一和第二扩散层之间的控制栅电极在浮动门旁边，横向间隔一段距离。浮置栅极和控制栅电极之间的耦合电容大于浮置栅极和半导体衬底之间的耦合电容。

58. 发明授权

US07777270B2 Nonvolatile semiconductor memory device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07777270B2
公开(公告)日：2010-08-17
申请号：US11835694
申请日：2007-08-08
申请人： Atsuhiro Kinoshita , Hiroshi Watanabe , Fumitaka Arai
发明人： Atsuhiro Kinoshita , Hiroshi Watanabe , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell.
摘要翻译：可以提供一种可以制造尺寸非常小并且具有高容量的存储器件，同时能够有效地抑制短沟道效应。非易失性半导体存储器件包括：形成在半导体衬底上的第一绝缘膜; 半导体层，其形成在所述半导体衬底上方，使得所述第一绝缘膜插入在所述半导体层和所述半导体衬底之间; 具有串联连接的多个存储单元晶体管的NAND单元，每个存储单元晶体管具有形成在所述半导体层上的栅极绝缘膜，形成在所述栅极绝缘膜上的浮置栅极，形成在所述浮动栅极上的第二绝缘膜以及形成在所述第二绝缘膜上的控制栅极; 源区，其具有形成在NAND单元的一侧的杂质扩散层; 以及在NAND单元的另一侧形成有金属电极的漏极区域。

59. 发明授权

US07774162B2 Electronic timer and system LSI 有权
标题翻译：电子定时器和系统LSI
公开(公告)号：US07774162B2
公开(公告)日：2010-08-10
申请号：US12015147
申请日：2008-01-16
申请人： Hiroshi Watanabe , Atsuhiro Kinoshita
发明人： Hiroshi Watanabe , Atsuhiro Kinoshita
IPC分类号： G04F10/00 , G06F11/00
CPC分类号： G04F10/10
摘要： A system LSI including a semiconductor chip which receives power from a power supply, and an electronic timer which measures a time from an interruption of power supplying to the semiconductor chip to a resumption of power supplying to the semiconductor chip.
摘要翻译：包括从电源接收电力的半导体芯片的系统LSI和测量从半导体芯片的供电中断恢复向半导体芯片供电的时间的电子计时器。

60. 发明授权

US09361408B2 Memory system including key-value store 有权
标题翻译：内存系统包括键值存储
公开(公告)号：US09361408B2
公开(公告)日：2016-06-07
申请号：US13569605
申请日：2012-08-08
申请人： Takao Marukame , Atsuhiro Kinoshita , Kosuke Tatsumura
发明人： Takao Marukame , Atsuhiro Kinoshita , Kosuke Tatsumura
IPC分类号： G06F17/30 , G06F12/02
CPC分类号： G06F17/30982 , G06F12/0246 , G06F17/30097 , G06F17/3012 , G06F2212/7201
摘要： According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes an interface, a memory block, an address acquisition circuit and a controller. The interface receives a data write/read request or a request based on the key-value store. The memory block has a data area for storing data and a metadata table containing the key-value data. The address acquisition circuit acquires an address in response to input of the key. The controller executes the data write/read request for the memory block, and outputs the address acquired to the memory block and executes the request based on the key-value store. The controller outputs the value corresponding to the key via the interface.
摘要翻译：根据一个实施例，包括密钥值存储的密钥值存储器的存储器系统包括密钥值数据作为一对密钥和对应于该密钥的值，包括接口，存储器块，地址获取电路和控制器。接口接收数据写/读请求或基于键值存储的请求。存储块具有用于存储数据的数据区域和包含键值数据的元数据表。地址获取电路响应于键的输入而获取地址。控制器执行存储器块的数据写/读请求，并将获取的地址输出到存储块，并根据键值存储执行请求。控制器通过接口输出与该键对应的值。

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