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    • 53. 发明授权
    • Apparatus and method for selectively invalidating entries in an address translation cache
    • 用于选择性地使地址转换高速缓存中的条目无效的装置和方法
    • US07389400B2
    • 2008-06-17
    • US11304136
    • 2005-12-15
    • Michael J. CorriganPaul LuVerne GodtlandJoaquin HinojosaCathy MayNaresh NayarEdward John Silha
    • Michael J. CorriganPaul LuVerne GodtlandJoaquin HinojosaCathy MayNaresh NayarEdward John Silha
    • G06F12/00
    • G06F12/1036G06F12/126G06F2212/1016G06F2212/683
    • An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.
    • 一种装置和方法选择性地使地址转换高速缓存中的条目无效,而不是使所有或几乎所有条目无效。 在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。 可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。 在指令中定义一个或多个“提示位”,该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。 在替代方案中,可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。 以这种方式,使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的,并且因此可以被保留,而地址转换高速缓存中的其他条目是无效的。
    • 56. 发明授权
    • Apparatus and method for virtualizing interrupts in a logically partitioned computer system
    • 用于虚拟化逻辑分区计算机系统中的中断的装置和方法
    • US07000051B2
    • 2006-02-14
    • US10403158
    • 2003-03-31
    • William Joseph ArmstrongRichard Louis ArndtNaresh Nayar
    • William Joseph ArmstrongRichard Louis ArndtNaresh Nayar
    • G06F13/24G06F9/45
    • G06F13/24G06F9/45541G06F9/4812G06F9/5077
    • A resource and partition manager virtualizes interrupts without using any additional hardware in a way that does not disturb the interrupt processing model of operating systems running on a logical partition. In other words, the resource and partition manager supports virtual interrupts in a logically partitioned computer system that may include share processors with no changes to a logical partition's operating system. A set of virtual interrupt registers is created for each virtual processor in the system. The resource and partition manager uses the virtual interrupt registers to process interrupts for the corresponding virtual processor. In this manner, from the point of view of the operating system, the interrupt processing when the operating system is running in a logical partition that may contain shared processors and virtual interrupts is no different that the interrupt processing when the operating system is running in computer system that only contains dedicated processor partitions.
    • 资源和分区管理器以不干扰在逻辑分区上运行的操作系统的中断处理模型的方式,虚拟化中断而不使用任何附加硬件。 换句话说,资源和分区管理器支持逻辑分区的计算机系统中的虚拟中断,其可以包括共享处理器,而不改变逻辑分区的操作系统。 为系统中的每个虚拟处理器创建一组虚拟中断寄存器。 资源和分区管理器使用虚拟中断寄存器来处理相应虚拟处理器的中断。 以这种方式,从操作系统的观点来看,当操作系统在可能包含共享处理器和虚拟中断的逻辑分区中运行时的中断处理与操作系统在计算机中运行时的中断处理没有区别 只包含专用处理器分区的系统。
    • 57. 发明申请
    • Translation look-aside buffer sharing among logical partitions
    • 逻辑分区之间的翻译后备缓冲区共享
    • US20050027960A1
    • 2005-02-03
    • US10631535
    • 2003-07-31
    • Jonathan DeMentCathy MayNaresh NayarEdward Silha
    • Jonathan DeMentCathy MayNaresh NayarEdward Silha
    • G06F12/08G06F12/10
    • G06F12/1036G06F2212/152
    • The present invention provides for storing and using a stored logical partition indicia in a TLB. A partition in a microprocessor architecture is employed. A virtual page number is selected. A stored LPID indicia corresponding to the selected page number is read from a TLB. The stored logical partition indicia from the TLB is compared to a logical partition indicia associated with the employed partition. If the stored logical partition indicia and the logical partition indicia associated with the employed partition match, a corresponding page table entry stored in the translation look-aside buffer is read. If they do not match, a page table entry from a page table entry source is retrieved and stored in the TLB. If a partition is to invalidate an entry in the TLB, a TLB entry command is generated and used to invalidate a memory entry.
    • 本发明提供了在TLB中存储和使用存储的逻辑分区标记。 采用微处理器架构中的分区。 选择虚拟页码。 从TLB中读取对应于所选页码的存储的LPID标记。 将来自TLB的存储的逻辑分区标记与与所使用的分区相关联的逻辑分区标记进行比较。 如果所存储的逻辑分区标记和与所采用分区相关联的逻辑分区标记匹配,则读取存储在转换后备缓冲器中的相应页表条目。 如果它们不匹配,则从页表入口源中的页表项被检索并存储在TLB中。 如果分区要使TLB中的条目无效,则会生成TLB条目命令,并将其用于使内存条目无效。