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51. 发明授权

US08661389B2 Systems and methods of designing integrated circuits 有权
标题翻译：设计集成电路的系统和方法
公开(公告)号：US08661389B2
公开(公告)日：2014-02-25
申请号：US13084748
申请日：2011-04-12
申请人： Chan-Hong Chern , Fu-Lung Hsueh , Li-Chun Tien
发明人： Chan-Hong Chern , Fu-Lung Hsueh , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of designing an integrated circuit includes providing a cell library including a first and second cell structures. The cell structures each include a dummy gate electrode disposed on a boundary. An edge gate electrode is disposed adjacent to the dummy gate electrode. An oxide definition (OD) region has an edge disposed between the edge gate electrode and the dummy gate electrode. The method includes determining if the cell structures are to be abutted with each other. If so, the method includes abutting the cell structures. If not so, the method includes increasing areas of portions of the OD regions between the edge gate electrodes and the dummy gate electrodes.
摘要翻译：设计集成电路的方法包括提供包括第一和第二单元结构的单元库。电池结构各自包括设置在边界上的虚拟栅电极。边缘栅电极被设置成与虚拟栅电极相邻。氧化物定义（OD）区域具有设置在边缘栅电极和伪栅电极之间的边缘。该方法包括确定单元结构是否彼此邻接。如果是，则该方法包括邻接单元结构。如果不是这样，则该方法包括增加边缘栅极电极和虚拟栅电极之间的OD区域的部分区域。

52. 发明授权

US08321828B2 Dummy fill to reduce shallow trench isolation (STI) stress variation on transistor performance 有权
标题翻译：虚拟填充以减少晶体管性能的浅沟槽隔离（STI）应力变化
公开(公告)号：US08321828B2
公开(公告)日：2012-11-27
申请号：US12684819
申请日：2010-01-08
申请人： Chan-Hong Chern
发明人： Chan-Hong Chern
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/0207 , H01L27/088 , H01L29/0692
摘要： A method of forming an integrated circuit structure on a chip includes extracting an active layer from a design of the integrated circuit structure, forming a guard band conforming to the shape of the active layer, the guard band surrounds the active layer, and the guard band is spaced from the active layer at a first spacing in the X-axis direction and at a second spacing in the Y-axis direction, removing any part of the guard band that violates design rules, removing convex corners of the guard band, and adding dummy diffusion patterns into the remaining space of the chip outside the guard band. The first and second spacing can be specified as the same spacings in a Spice model characterization of the integrated circuit structure. The dummy diffusion patterns with different granularities can be added so that the diffusion density is substantially uniform over the chip.
摘要翻译：在芯片上形成集成电路结构的方法包括从集成电路结构的设计中提取有源层，形成符合有源层形状的保护带，保护带围绕有源层，保护带与有源层以X轴方向的第一间隔和Y轴方向上的第二间隔与有源层间隔开，去除违反设计规则的保护带的任何部分，去除保护带的凸角，并添加伪散射图案进入保护带外部芯片的剩余空间。在集成电路结构的Spice模型表征中，第一和第二间隔可以被指定为相同的间距。可以添加具有不同粒度的虚拟扩散图案，使得扩散密度在芯片上基本均匀。

53. 发明授权

US5710450A Transistor with ultra shallow tip and method of fabrication 失效
标题翻译：具有超浅尖端的晶体管及其制造方法
公开(公告)号：US5710450A
公开(公告)日：1998-01-20
申请号：US363749
申请日：1994-12-23
申请人： Robert S. Chau , Chan-Hong Chern , Chia-Hong Jan , Kevin R. Weldon , Paul A. Packan , Leopoldo D. Yau
发明人： Robert S. Chau , Chan-Hong Chern , Chia-Hong Jan , Kevin R. Weldon , Paul A. Packan , Leopoldo D. Yau
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/08 , H01L29/417 , H01L29/45 , H01L29/49 , H01L29/78 , H01L29/06 , H01L21/265
CPC分类号： H01L29/66613 , H01L21/2254 , H01L21/2257 , H01L21/2807 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L29/0847 , H01L29/41775 , H01L29/41783 , H01L29/45 , H01L29/4925 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip region comprising an ultra shallow region which extends beneath the gate electrode and a raised region.
摘要翻译：具有低电阻超浅尖端区域的新型晶体管及其制造方法。本发明的新型晶体管具有源/漏扩展或尖端区域，其包括在栅电极下方延伸的超浅区域和升高区域。

54. 发明授权

US06165826A Transistor with low resistance tip and method of fabrication in a CMOS process 失效
标题翻译：具有低电阻尖端的晶体管和CMOS工艺中的制造方法
公开(公告)号：US06165826A
公开(公告)日：2000-12-26
申请号：US581243
申请日：1995-12-29
申请人： Robert S. Chau , Chia-Hong Jan , Chan-Hong Chern , Leopoldo D. Yau
发明人： Robert S. Chau , Chia-Hong Jan , Chan-Hong Chern , Leopoldo D. Yau
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/08 , H01L29/417 , H01L29/45 , H01L29/49 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/2254 , H01L21/2257 , H01L21/2807 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L29/41775 , H01L29/41783 , H01L29/45 , H01L29/4925 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66613 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first gate electrode are formed on a first portion of a semiconductor substrate having a first conductivity type, and a second gate dielectric and a said gate electrode are formed on a second portion of semiconductor substrate having a second conductivity type. A silicon nitride layer is formed over the first portion of the semiconductor substrate including the first gate electrode and over the second portion of the semiconductor substrate including the second gate electrode. The silicon nitride layer is removed from the second portion of the silicon substrate and from the top of the second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of the second gate electrode. A pair of recesses are then formed in the second portion of the semiconductor substrate in alignment with the first pair of sidewall spacers. A selectively deposited semiconductor material is then formed in the recesses.
摘要翻译：一种具有低电阻超浅尖端区域的新型晶体管及其在互补金属氧化物半导体（CMOS）工艺中制造的方法。根据本发明的优选方法，在具有第一导电类型的半导体衬底的第一部分上形成第一栅极电介质和第一栅电极，并且在第二栅极电极上形成第二栅极电介质和所述栅电极具有第二导电类型的半导体衬底的部分。在包括第一栅电极的半导体衬底的第一部分之上以及包括第二栅电极的半导体衬底的第二部分之上形成氮化硅层。从硅衬底的第二部分和第二栅电极的顶部去除氮化硅层，从而形成与第二栅电极的相对侧相邻的第一对氮化硅间隔物。然后在半导体衬底的第二部分中与第一对侧壁间隔件对准地形成一对凹部。然后在凹部中形成选择性淀积的半导体材料。

55. 发明授权

US5488003A Method of making emitter trench BiCMOS using integrated dual layer emitter mask 失效
标题翻译：使用集成双层发射器掩模制造发射极沟槽BiCMOS的方法
公开(公告)号：US5488003A
公开(公告)日：1996-01-30
申请号：US40673
申请日：1993-03-31
申请人： Stephen Chambers , Brian J. Brown , Chan-Hong Chern , Robert Chau , Leopoldo D. Yau
发明人： Stephen Chambers , Brian J. Brown , Chan-Hong Chern , Robert Chau , Leopoldo D. Yau
IPC分类号： H01L21/331 , H01L21/8249 , H01L29/08 , H01L21/265
CPC分类号： H01L29/66272 , H01L21/8249 , H01L29/0804 , Y10S148/01 , Y10S148/011
摘要： A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.
摘要翻译：公开了一种从双极晶体管的基极区域隔离多晶硅发射极的新方法，将多晶硅发射极沟槽到半导体衬底中，并保持独立于发射极掩模厚度变化的双极晶体管的一致的基底宽度。多晶硅发射极隔离通过保护多晶硅发射极和基极区域之间的电介质层与BiCMOS制造环境相关的缺陷和污染来提供发射极和基极之间的更好的电击穿特性。为了减少与热电子注入相关的晶体管操作问题，多晶硅发射极被沟入半导体衬底。一致的基极宽度提高了晶体管的性能均匀性，从而提高了可制造性和可靠性。

56. 发明授权

US08835246B2 Integrated circuits with resistors and methods of forming the same 有权
标题翻译：具有电阻器的集成电路及其形成方法
公开(公告)号：US08835246B2
公开(公告)日：2014-09-16
申请号：US13035533
申请日：2011-02-25
申请人： Chan-Hong Chern , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Fu-Lung Hsueh
IPC分类号： H01L27/088 , H01L27/06
CPC分类号： H01L27/0629 , H01L27/1207 , H01L28/20 , H01L29/42364 , H01L29/42372 , H01L29/4958 , H01L29/4966 , H01L29/4975
摘要： A method of forming an integrated circuit includes forming at least one transistor over a substrate. The at least one transistor includes a first gate dielectric structure disposed over a substrate. A work-function metallic layer is disposed over the first gate dielectric structure. A conductive layer is disposed over the work-function metallic layer. A source/drain (S/D) region is disposed adjacent to each sidewall of the first gate dielectric structure. At least one resistor structure is formed over the substrate. The at least one resistor structure includes a first doped semiconductor layer disposed over the substrate. The at least one resistor structure does not include any work-function metallic layer between the first doped semiconductor layer and the substrate.
摘要翻译：形成集成电路的方法包括在衬底上形成至少一个晶体管。所述至少一个晶体管包括设置在衬底上的第一栅极电介质结构。工作功能金属层设置在第一栅极电介质结构上。导电层设置在功函数金属层上。源极/漏极（S / D）区域邻近第一栅极电介质结构的每个侧壁设置。在衬底上形成至少一个电阻器结构。所述至少一个电阻器结构包括设置在所述衬底上的第一掺杂半导体层。至少一个电阻器结构不包括在第一掺杂半导体层和衬底之间的任何功函数金属层。

57. 发明授权

US08350339B2 Integrated circuits having dummy gate electrodes and methods of forming the same 有权
标题翻译：具有虚拟栅电极的集成电路及其形成方法
公开(公告)号：US08350339B2
公开(公告)日：2013-01-08
申请号：US12795144
申请日：2010-06-07
申请人： Mei-Hui Huang , Chan-Hong Chern
发明人： Mei-Hui Huang , Chan-Hong Chern
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/088 , H01L21/823425 , H01L21/823437 , H01L27/0207 , H01L29/0619 , H01L29/0649 , H01L29/42372 , H01L29/66545
摘要： An integrated circuit includes at least one first gate electrode of at least one active transistor. At least one first dummy gate electrode is disposed adjacent to a first side edge of the at least one first gate electrode. At least one second dummy gate electrode is disposed adjacent to a second side edge of the at least one first gate electrode. The second side edge is opposite to the first side edge. At least one guard ring is disposed around the at least one first gate electrode, the at least one first dummy gate electrode, and the at least one second dummy gate electrode. An ion implantation layer of the at least one guard ring substantially touches at least one of the at least one first dummy gate electrode and the at least one second dummy gate electrode.
摘要翻译：集成电路包括至少一个有源晶体管的第一栅电极。至少一个第一虚拟栅电极设置成与所述至少一个第一栅电极的第一侧边缘相邻。至少一个第二伪栅电极设置成与所述至少一个第一栅电极的第二侧边相邻。第二侧边缘与第一侧边缘相对。至少一个保护环布置在所述至少一个第一栅电极，所述至少一个第一虚拟栅极电极和所述至少一个第二虚拟栅电极周围。所述至少一个保护环的离子注入层基本上接触所述至少一个第一伪栅极电极和所述至少一个第二虚设栅极电极中的至少一个。

58. 发明授权

US5434093A Inverted spacer transistor 失效
标题翻译：反向间隔晶体管
公开(公告)号：US5434093A
公开(公告)日：1995-07-18
申请号：US288332
申请日：1994-08-10
申请人： Robert S. Chau , Chan-Hong Chern , Shahriar S. Ahmed , Robert F. Hainsey , Robert J. Stoner , Todd E. Wilke , Leopoldo D. Yau
发明人： Robert S. Chau , Chan-Hong Chern , Shahriar S. Ahmed , Robert F. Hainsey , Robert J. Stoner , Todd E. Wilke , Leopoldo D. Yau
IPC分类号： H01L21/336 , H01L29/08 , H01L29/10 , H01L29/423 , H01L21/265
CPC分类号： H01L29/66583 , H01L29/0847 , H01L29/1033 , H01L29/41783 , H01L29/42376 , H01L29/66553 , H01L29/66628 , H01L29/66537
摘要： A method for forming narrow length transistors by forming a trench in a first layer over a semiconductor substrate. Spacers are then formed within the trench and a gate dielectric is formed between the spacers at the bottom of the trench on the semiconductor substrate. The trench is then filled with a gate electrode material which is chemically-mechanically polished back to isolate the gate electrode material within the trench, and the first layer is removed leaving the gate dielectric, gate electrode and spacers behind.
摘要翻译：一种通过在半导体衬底上的第一层中形成沟槽来形成窄长度晶体管的方法。然后在沟槽内形成间隔物，并且在半导体衬底上的沟槽的底部的间隔物之间形成栅极电介质。然后用栅极电极材料填充沟槽，该栅电极材料被化学机械地抛光以隔离沟槽内的栅极电极材料，并且去除第一层，留下栅极电介质，栅极电极和间隔物。

59. 发明授权

US06326664B1 Transistor with ultra shallow tip and method of fabrication 失效
标题翻译：具有超浅尖端的晶体管及其制造方法
公开(公告)号：US06326664B1
公开(公告)日：2001-12-04
申请号：US08971992
申请日：1997-11-17
申请人： Robert S. Chau , Chan-Hong Chern , Chia-Hong Jan , Kevin R. Weldon , Paul A. Packan , Leopoldo D. Yau
发明人： Robert S. Chau , Chan-Hong Chern , Chia-Hong Jan , Kevin R. Weldon , Paul A. Packan , Leopoldo D. Yau
IPC分类号： H01L2906
CPC分类号： H01L29/0847 , H01L21/2254 , H01L21/2257 , H01L21/2807 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L29/41775 , H01L29/41783 , H01L29/45 , H01L29/4925 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66613 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode and a raised region.
摘要翻译：具有低电阻超浅尖端区域的新型晶体管及其制造方法。本发明的新型晶体管具有源极/漏极延伸部分或尖端，其包括在栅电极下方延伸的超浅区域和升高的区域。

60. 发明授权

US5891809A Manufacturable dielectric formed using multiple oxidation and anneal steps 失效
标题翻译：使用多个氧化和退火步骤形成的可制造电介质
公开(公告)号：US5891809A
公开(公告)日：1999-04-06
申请号：US536653
申请日：1995-09-29
申请人： Robert S. K. Chau , Lawrence N. Brigham , Chia-Hong Jan , Chan-Hong Chern , Binny P. Arcot
发明人： Robert S. K. Chau , Lawrence N. Brigham , Chia-Hong Jan , Chan-Hong Chern , Binny P. Arcot
IPC分类号： H01L21/28 , H01L21/314 , H01L21/316 , H01L21/336 , H01L21/762 , H01L29/51 , H01L21/31
CPC分类号： H01L21/28185 , H01L21/0214 , H01L21/02238 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/28202 , H01L21/28211 , H01L21/3144 , H01L21/31662 , H01L21/76235 , H01L29/518 , H01L29/6656 , H01L29/6659
摘要： A method of forming a thin, robust nitrided oxide layer. The process results in a manufacturable, uniform, low-defect density, reliable nitrided oxide that may be used as a gate dielectric, as a portion of a spacer, or as a portion of a trench isolation. First, a substrate is oxidized in a chlorinated dry oxidation followed by a low temperature pyrogenic steam oxidation. Next, a low temperature ammonia anneal is performed, followed by a high temperature anneal in an inert ambient.
摘要翻译：形成薄而坚固的氮化氧化物层的方法。该方法产生可制造，均匀，低缺陷密度，可靠的氮化氧化物，其可以用作栅极电介质，作为间隔物的一部分，或者作为沟槽隔离的一部分。首先，将基板在氯化干燥氧化中氧化，然后进行低温热解蒸汽氧化。接下来，进行低温氨退火，随后在惰性环境中进行高温退火。

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