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51. 发明授权

US07298219B2 Phase-locked loop circuit 有权
标题翻译：锁相环电路
公开(公告)号：US07298219B2
公开(公告)日：2007-11-20
申请号：US11269742
申请日：2005-11-09
申请人： Shiro Dosho , Takashi Morie , Kouji Okamoto , Yuji Yamada , Kazuaki Sogawa
发明人： Shiro Dosho , Takashi Morie , Kouji Okamoto , Yuji Yamada , Kazuaki Sogawa
IPC分类号： H03L7/00 , H03L1/02
CPC分类号： H03L7/0995 , H03L7/0898 , H03L7/18 , H03L7/1976
摘要： The phase-locked loop circuit includes a gain setting circuit for setting a gain of a voltage controlled oscillator, and a time-constant setting circuit for setting a time constant, which is determined by the amount of current in a charge pump circuit and a capacitance value of a loop filter. The gain setting circuit sets the gain to a predetermined value, and the time-constant setting circuit sets the time constant to a predetermined value, whereby the loop band width of the phase-locked loop circuit is set to a desired value.
摘要翻译：锁相环电路包括用于设定压控振荡器的增益的增益设定电路和用于设定时间常数的时间常数设定电路，时间常数由电荷泵电路中的电流量和电容环路滤波器的值。增益设定电路将增益设定为预定值，时间常数设定电路将时间常数设定为规定值，由此将锁相环电路的环带宽度设定为期望值。

52. 发明授权

US07078948B2 Low-pass filter, feedback system, and semiconductor integrated circuit 失效
标题翻译：低通滤波器，反馈系统和半导体集成电路
公开(公告)号：US07078948B2
公开(公告)日：2006-07-18
申请号：US10815672
申请日：2004-04-02
申请人： Shiro Dosho
发明人： Shiro Dosho
IPC分类号： H04B7/197
CPC分类号： H03H7/06 , H03H11/126 , H03L7/0893 , H03L7/0895 , H03L7/093 , H03L7/18
摘要： In a low-pass filter which is preferably used as a loop filter in a PLL or DLL, filter characteristics which are the same as those of a conventional low-pass filter are realized without causing collateral problems, such as an increase in the circuit area, the circuit complexity, or the resistance value, which may be caused due to size reduction of a capacitive element in the conventional low-pass filter. Thus, in a loop filter including a capacitive element and a resistive element which are connected in series, the first input terminal is provided at the side including the resistive element, and the second input terminal is provided at a connection point of the capacitive element and the resistive element. The first input terminal is supplied with the first electric current. On the other hand, the second electric current, which is a part of the first electric current supplied to the first input terminal, is extracted from the second input terminal, so that the electric current flowing into the capacitive element is smaller than the electric current flowing through the resistive element.
摘要翻译：在PLL或DLL中优选用作环路滤波器的低通滤波器中，实现与常规低通滤波器相同的滤波器特性，而不会引起诸如电路面积增加之类的附带问题，电路复杂度或电阻值，这可能是由于常规低通滤波器中的电容元件的尺寸减小而引起的。因此，在包括串联连接的电容元件和电阻元件的环路滤波器中，第一输入端子设置在包括电阻元件的一侧，第二输入端子设置在电容元件的连接点处，电阻元件。第一输入端被提供有第一电流。另一方面，从第二输入端子抽出作为提供给第一输入端子的第一电流的一部分的第二电流，使得流入电容元件的电流小于电流流过电阻元件。

53. 发明授权

US06982581B2 Duty cycle correction circuit 失效
标题翻译：占空比校正电路
公开(公告)号：US06982581B2
公开(公告)日：2006-01-03
申请号：US10713162
申请日：2003-11-17
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
IPC分类号： H03K3/017
CPC分类号： H03K5/133 , H03K5/1565
摘要： In order to correct the duty cycle of a given clock signal to produce a clock signal with a 50% duty cycle, a duty cycle correction circuit includes a delay unit for delaying a first clock signal to output a second clock signal and a clock-signal output unit. The clock-signal output unit includes two transistors which use the first and second clock signals as the inputs of respective gates and an inverter circuit for inverting a signal output from a common drain of the transistors to output a third clock signal. The delay unit delays the first clock signal so that the first clock signal falling appears at a timing at which the duty cycle thereof becomes 50%. The two transistors in the clock-signal output unit output, as the third clock signal, a ground voltage and a source voltage as the signal from the common drain in response to the rising of the first clock signal and the falling of the second clock signal, respectively.
摘要翻译：为了校正给定时钟信号的占空比以产生具有50％占空比的时钟信号，占空比校正电路包括用于延迟第一时钟信号以输出第二时钟信号和时钟信号的延迟单元输出单元。时钟信号输出单元包括使用第一和第二时钟信号作为各个门的输入的两个晶体管，以及用于反相从晶体管的公共漏极输出的信号以输出第三时钟信号的反相器电路。延迟单元延迟第一时钟信号，使得第一时钟信号在占空比变为50％的定时出现。时钟信号输出单元中的两个晶体管响应于第一时钟信号的上升和第二时钟信号的下降而输出作为第三时钟信号的接地电压和源极电压作为来自公共漏极的信号，分别。

54. 发明申请

US20050024100A1 Current driver and display device 有权
标题翻译：当前驱动和显示设备
公开(公告)号：US20050024100A1
公开(公告)日：2005-02-03
申请号：US10815800
申请日：2004-04-02
申请人： Yoshito Date , Tetsuro Omori , Shiro Dosho , Makoto Mizuki
发明人： Yoshito Date , Tetsuro Omori , Shiro Dosho , Makoto Mizuki
IPC分类号： H01L51/50 , G09G3/20 , G09G3/30 , G09G3/32 , H03B21/00 , H05B33/14
CPC分类号： G09G3/3283 , G09G3/3241 , G09G2310/027 , G09G2320/0233 , G09G2330/028
摘要： The first and second chips are provided side by side. The first chip includes: a current supply section for outputting a drive current, the current supply section including a current mirror; a current distribution MISFET; a current input MISFET for transmitting an electric current to the current supply section, the current input MISFET being connected to the current distribution MISFET; and a second current distribution MISFET. The current distribution MISFET and the second current distribution MISFET constitute a current mirror. The second chip includes a second current input MISFET which is connected to the second current distribution MISFET. The ratio between the W/L ratio of the current distribution MISFET and the W/L ratio of the current input MISFET connected thereto is the same in the first and second chips.
摘要翻译：第一和第二芯片并排设置。第一芯片包括：电流供应部分，用于输出驱动电流;电流供应部分包括电流镜; 电流分布MISFET; 电流输入MISFET，用于将电流传输到电流供应部分，电流输入MISFET连接到电流分布MISFET; 和第二电流分布MISFET。电流分布MISFET和第二电流分布MISFET构成电流镜。第二芯片包括连接到第二电流分布MISFET的第二电流输入MISFET。电流分布MISFET的W / L比与与其连接的电流输入MISFET的W / L比之间的比率在第一和第二芯片中是相同的。

55. 发明授权

US06603219B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06603219B2
公开(公告)日：2003-08-05
申请号：US09801472
申请日：2001-03-08
申请人： Masaomi Toyama , Shiro Dosho , Naoshi Yanagisawa
发明人： Masaomi Toyama , Shiro Dosho , Naoshi Yanagisawa
IPC分类号： H02J100
CPC分类号： H03K17/005 , H01L24/06 , H01L2224/05554 , H01L2224/49175 , H01L2924/14 , H03K3/03 , H03K17/693 , Y10T307/391 , Y10T307/461 , Y10T307/492 , H01L2924/00
摘要： A semiconductor integrated circuit includes a plurality of units. Each of the units includes a power supply pad, a function circuit, and a power supply control circuit. The plurality of units each have a first state in which the function circuit is in an operating state by the power supply pad being at a prescribed operating potential and a second state in which the function circuit is in a non-operating state by the power supply pad being at a prescribed non-operating potential. The power supply control circuit includes a switching circuit for connecting the power supply pad to the prescribed non-operating potential. The power supply control circuit in each of the plurality of units closes the switching circuit when at least one of the other units is in the first state and opens the switching circuit otherwise.
摘要翻译：半导体集成电路包括多个单元。每个单元包括电源焊盘，功能电路和电源控制电路。所述多个单元各自具有第一状态，其中所述功能电路处于处于规定操作电位的所述功率电路处于工作状态，以及所述功能电路通过所述电源处于非工作状态的第二状态垫处于规定的非操作电位。电源控制电路包括用于将电源焊盘连接到规定的非工作电位的开关电路。当多个单元中的至少一个处于第一状态时，多个单元中的每个单元中的电源控制电路闭合开关电路，否则打开开关电路。

56. 发明申请

US20120262320A1 RESONATOR, DELTA-SIGMA MODULATOR, AND WIRELESS COMMUNICATION DEVICE 有权
标题翻译：谐振器，DELTA-SIGMA调制器和无线通信设备
公开(公告)号：US20120262320A1
公开(公告)日：2012-10-18
申请号：US13534716
申请日：2012-06-27
申请人： Yosuke Mitani , Kazuo Matsukawa , Masao Takayama , Koji Obata , Shiro Dosho
发明人： Yosuke Mitani , Kazuo Matsukawa , Masao Takayama , Koji Obata , Shiro Dosho
IPC分类号： H03M3/02 , H03F3/45
CPC分类号： H03H11/04 , H03H2011/0488 , H03M3/404
摘要： Two T filters, one of which includes two resistive elements and one capacitive element and the other of which includes two capacitive elements and one resistive element, are inserted in a negative-feedback section of an operational amplifier, and a resistive element and a capacitive element are connected between each of intermediate nodes and a signal input terminal. A resistive element and a capacitive element which are connected to each other in parallel are connected between the signal input terminal and an inverting input terminal of the operational amplifier. With this configuration, overall admittances where elements connected to the corresponding intermediate nodes are in parallel connection are equal to each other.
摘要翻译：两个T滤波器，其中一个包括两个电阻元件和一个电容元件，另一个包括两个电容元件和一个电阻元件，插入到运算放大器的负反馈部分中，电阻元件和电容元件连接在每个中间节点和信号输入端子之间。并联连接的电阻元件和电容元件连接在信号输入端子和运算放大器的反相输入端子之间。利用这种配置，连接到对应的中间节点的元件并联连接的整体导纳彼此相等。

57. 发明授权

US07523154B2 Write compensation circuit and signal interpolation circuit of recording device 有权
标题翻译：写记录装置的补偿电路和信号插补电路
公开(公告)号：US07523154B2
公开(公告)日：2009-04-21
申请号：US11198950
申请日：2005-08-08
申请人： Hirokuni Fujiyama , Shiro Dosho , Hiroyuki Nakahira , Akira Yamamoto , Hiroki Mouri
发明人： Hirokuni Fujiyama , Shiro Dosho , Hiroyuki Nakahira , Akira Yamamoto , Hiroki Mouri
IPC分类号： G06G7/00
CPC分类号： G11B20/10 , G11B5/09 , G11B20/10194 , G11B20/10212 , G11B2005/0005 , H03K5/082 , H03K5/13 , H03K5/133
摘要： A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying portion for supplying the first driving voltage to the first delay portion in such a manner that the first delay time is substantially equal to a clock period of the clock signal.
摘要翻译：记录装置的写补偿电路包括由第一驱动电压驱动的第一延迟部分，用于接收时钟信号，延迟时钟信号第一延迟时间，并输出延迟时钟信号;以及电压提供部分，用于提供第一驱动电压到第一延迟部分，使得第一延迟时间基本上等于时钟信号的时钟周期。

58. 发明授权

US07327182B2 Switched capacitor filter and feedback system 有权
标题翻译：开关电容滤波器和反馈系统
公开(公告)号：US07327182B2
公开(公告)日：2008-02-05
申请号：US11396464
申请日：2006-04-04
申请人： Shiro Dosho , Yusuke Tokunaga , Takashi Morie
发明人： Shiro Dosho , Yusuke Tokunaga , Takashi Morie
IPC分类号： G06F7/64
CPC分类号： H03H19/004 , H03D13/004 , H03L7/0891 , H03L7/093 , H03L7/18
摘要： A switched capacitor filter comprises three switched capacitor circuits. Each switched capacitor circuit has a capacitance. A first state that the capacitance is connected to an input end of a current signal, a second state that the capacitance is connected to an output end of a voltage signal, and a third state that the capacitance is connected to a side of a filter capacitance, are cycled. These three switched capacitor circuits are operated under an interleave control so that the first to third states do not each overlap between the three switched capacitor circuits.
摘要翻译：开关电容滤波器包括三个开关电容器电路。每个开关电容电路具有电容。电容连接到电流信号的输入端的第一状态，电容连接到电压信号的输出端的第二状态，以及电容连接到滤波电容的一侧的第三状态，循环。这三个开关电容器电路在交错控制下操作，使得第一至第三状态在三个开关电容器电路之间不重叠。

59. 发明授权

US07271648B2 Ladder filter, analog equalizer and signal readout system 有权
标题翻译：梯形滤波器，模拟均衡器和信号读出系统
公开(公告)号：US07271648B2
公开(公告)日：2007-09-18
申请号：US10680129
申请日：2003-10-08
申请人： Shiro Dosho , Takashi Morie
发明人： Shiro Dosho , Takashi Morie
IPC分类号： H03K5/00
CPC分类号： G11B20/10009 , H03H11/04 , H03H11/486 , H03H11/50
摘要： A ladder filter includes multiple inductor sections, each including voltage-controlled current sources and capacitors. A second signal input terminal is provided for the filter separately from an ordinary signal input terminal and a signal, which has been input through the second terminal, is supplied to one of the voltage-controlled current sources by way of a gain calculator. By adjusting the gain obtained by the gain calculator to an appropriate value, the ladder filter can make the numerator of its transfer function freely definable.
摘要翻译：梯形滤波器包括多个电感器部分，每个电路部分包括压控电流源和电容器。与普通信号输入端分开设置用于滤波器的第二信号输入端子，并且已经通过第二端子输入的信号通过增益计算器提供给一个压控电流源。通过将增益计算器获得的增益调整到适当的值，梯形滤波器可以使其传递函数的分子自由定义。

60. 发明授权

US07254507B2 Analog circuit automatic calibration system 有权
标题翻译：模拟电路自动校准系统
公开(公告)号：US07254507B2
公开(公告)日：2007-08-07
申请号：US10915345
申请日：2004-08-11
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
IPC分类号： G01R35/02
CPC分类号： G01R35/005 , G01R31/316
摘要： An analog circuit automatic calibration system for calibrating an object circuit that is an analog circuit having a characteristic changing with an input set value. The system includes: a set value storage section for storing a value and outputting the value to the object circuit as the set value; a characteristic detection section for detecting the characteristic of the object circuit; a first characteristic change section for determining the set value so that the characteristic of the object circuit is optimized; a second characteristic change section for updating the set value so that the characteristic of the object circuit is maintained, using an algorithm different from that used in the first characteristic change section; and a selector for selecting either one of the outputs of the first and second characteristic sections to enable the selected one to be stored in the set value storage section.
摘要翻译：一种模拟电路自动校准系统，用于校准作为具有随着输入设定值变化的特性的模拟电路的目标电路。该系统包括：设定值存储部分，用于存储值并将该值输出到对象电路作为设定值; 用于检测所述目标电路的特性的特性检测部分; 用于确定所述设定值使得所述对象电路的特性被优化的第一特征变化部分; 第二特征变化部，使用与第一特征变化部中使用的算法不同的算法来更新设定值，使得保持对象电路的特性; 以及选择器，用于选择第一和第二特征部分的输出之一，以使所选择的一个存储在设定值存储部分中。

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