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51. 发明授权

US6055743A Method and apparatus for drying semiconductor wafers without forming water markers thereon 失效
标题翻译：用于干燥半导体晶片而不在其上形成水标记的方法和设备
公开(公告)号：US6055743A
公开(公告)日：2000-05-02
申请号：US9158
申请日：1998-01-20
申请人： Yi-Nan Chen , Wen-Chi Hsu
发明人： Yi-Nan Chen , Wen-Chi Hsu
IPC分类号： H01L21/304 , H01L21/00 , F26B3/00
CPC分类号： H01L21/67028
摘要： A method and an apparatus for drying a semiconductor wafer. The semiconductor wafer is first dipped in a liquid with a volatility higher than water and which is miscible with water. The dipped semiconductor wafer is then delivered in an IPA dryer to carry out the drying process. The drying process includes evaporating isopropyl alcohol to obtain a vapor and condensing the IPA vapor on the surface of the semiconductor wafer. The IPA is heated and vaporized by a hot plate disposed at the bottom of the IPA dryer. The condenser is mounted on the inner peripheral surface of the IPA dryer and surrounds the semiconductor wafer, which is supported by a holder.
摘要翻译：一种用于干燥半导体晶片的方法和装置。首先将半导体晶片浸入挥发性高于水并与水混溶的液体中。然后将浸渍的半导体晶片在IPA干燥器中输送以进行干燥过程。干燥过程包括蒸发异丙醇以获得蒸汽并将半导体晶片表面上的IPA蒸气冷凝。 IPA由设置在IPA干燥器底部的热板加热和蒸发。冷凝器安装在IPA干燥器的内周表面上，并且围绕由保持器支撑的半导体晶片。

52. 发明授权

US08912595B2 Trench MOS structure and method for forming the same 有权
标题翻译：沟槽MOS结构及其形成方法
公开(公告)号：US08912595B2
公开(公告)日：2014-12-16
申请号：US13106852
申请日：2011-05-12
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/78 , H01L29/423 , H01L29/66 , H01L21/308
CPC分类号： H01L29/7813 , H01L21/3083 , H01L29/4236 , H01L29/66666 , H01L29/66734 , H01L29/7827
摘要： A trench MOS structure is disclosed. The trench MOS structure includes a substrate, an epitaxial layer, a doping well, a doping region and a trench gate. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. The trench gate is partially disposed in the doping region. The trench gate has a bottle shaped profile with a top section smaller than a bottom section, both are partially disposed in the doping well. The bottom section of two adjacent trench gates results in a higher electrical field around the trench MOS structures.
摘要翻译：公开了一种沟槽MOS结构。沟槽MOS结构包括衬底，外延层，掺杂阱，掺杂区和沟槽栅。衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。外延层具有第一导电类型并且设置在第一侧。掺杂阱具有第二导电类型并且设置在外延层上。掺杂区域具有第一导电类型并且被布置在掺杂阱上。沟槽栅极部分地设置在掺杂区域中。沟槽门具有瓶形轮廓，其顶部部分小于底部部分，都部分地设置在掺杂井中。两个相邻沟槽栅极的底部部分导致沟槽MOS结构周围的较高电场。

53. 发明授权

US08816715B2 MOS test structure, method for forming MOS test structure and method for performing wafer acceptance test 有权
标题翻译： MOS测试结构，用于形成MOS测试结构的方法和用于进行晶片验收测试的方法
公开(公告)号：US08816715B2
公开(公告)日：2014-08-26
申请号：US13105913
申请日：2011-05-12
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： G01R31/02 , G01R31/26 , H01L21/66 , G01R31/28
CPC分类号： H01L22/34 , G01R31/02 , G01R31/26 , G01R31/2644 , G01R31/2831
摘要： A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together.
摘要翻译：公开了MOS测试结构。划线区域设置在具有与第一侧相对的第一侧和第二侧的基板上。外延层设置在第一侧上，掺杂阱设置在外延层上，并且掺杂区域设置在掺杂阱上。第一深度的沟槽栅极设置在掺杂区域，掺杂阱和划线区域中。导电材料填充测试，通过该测试具有覆盖测试通孔的内壁的第二深度和隔离，并且设置在掺杂区域，掺杂阱，外延层和划线区域中，以电连接到外延层，使得测试通孔能够一起测试外延层和衬底。

54. 发明授权

US08692318B2 Trench MOS structure and method for making the same 有权
标题翻译：沟槽MOS结构和制作方法
公开(公告)号：US08692318B2
公开(公告)日：2014-04-08
申请号：US13104924
申请日：2011-05-10
申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0649 , H01L29/0696 , H01L29/1095 , H01L29/66734
摘要： A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring.
摘要翻译：提供沟槽MOS结构。沟槽MOS结构包括保护环内的衬底，外延层，沟槽，栅极隔离，沟槽栅极，保护环和加强结构。衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。外延层具有第一导电类型并且设置在第一侧。沟槽设置在外延层中。栅极隔离覆盖沟槽的内壁。沟槽栅设置在沟槽中并且具有第一导电类型。保护环具有第二导电类型并且设置在外延层内。加强结构具有电绝缘材料并且设置在保护环内。

55. 发明授权

US08458842B2 Post-CMP wafer cleaning apparatus 有权
标题翻译： CMP后晶圆清洗装置
公开(公告)号：US08458842B2
公开(公告)日：2013-06-11
申请号：US13104964
申请日：2011-05-10
申请人： Li-Chung Liu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Li-Chung Liu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： B08B3/02
CPC分类号： H01L21/67051 , H01L21/02052 , H01L21/67046
摘要： A post-CMP wafer cleaning apparatus includes a chamber; a plurality of rollers adapted to hold and rotate a wafer within the chamber; at least one brush adapted to scrub a surface of the wafer to be cleaned; and a liquid spraying device adapted to spray a liquid on the wafer, the liquid spraying device comprising two spray bars jointed together via a joint member.
摘要翻译： CMP后晶片清洗装置包括：腔室; 多个辊子，适于在所述腔室内保持和旋转晶片; 至少一个刷子，适于擦拭要清洁的晶片的表面; 以及适于将液体喷射在晶片上的液体喷射装置，所述液体喷射装置包括通过接头构件连接在一起的两个喷射杆。

56. 发明授权

US08394721B2 Method for obtaining a layout design for an existing integrated circuit 有权
标题翻译：获得现有集成电路布局设计的方法
公开(公告)号：US08394721B2
公开(公告)日：2013-03-12
申请号：US13104986
申请日：2011-05-11
申请人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/311
CPC分类号： H01L27/0203 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure.
摘要翻译：一种用于获得现有集成电路的布局设计的方法，其中集成电路管芯以倾斜角抛光以形成倾斜的抛光表面，并且获得倾斜抛光表面的一个或多个图像。图像可以直接重叠，或者图像或图像可以用于提供信息以获得包括布局结构的至少一个重复单元结构的布局设计。

57. 发明申请

US20130052820A1 METHOD OF FORMING CONDUCTIVE PATTERN 有权
标题翻译：形成导电图案的方法
公开(公告)号：US20130052820A1
公开(公告)日：2013-02-28
申请号：US13214244
申请日：2011-08-22
申请人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
发明人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/28
CPC分类号： H01L21/321 , H01L21/76856 , H01L21/76861 , H01L21/76876 , H01L21/76885
摘要： A method of forming conductive pattern is provided. A seeding layer is formed on an underlayer. By using an energy ray, an irradiation treatment is performed on a portion of a surface of the seeding layer. The seeding layer thus includes a plurality of irradiated regions and a plurality of unirradiated regions. A conversion treatment is performed on the irradiated regions of the seeding layer. A selective growth process is performed, so as to form a conductive pattern on each unirradiated region of the seeding layer. The irradiated regions of the seeding layer are removed, so that the conductive patterns are insulated from each other.
摘要翻译：提供形成导电图案的方法。在底层上形成接种层。通过使用能量射线，对接种层的表面的一部分进行照射处理。因此，接种层包括多个照射区域和多个未照射区域。对接种层的照射区域进行转化处理。进行选择性生长处理，以在接种层的每个未照射区域上形成导电图案。去除接种层的照射区域，使得导电图案彼此绝缘。

58. 发明授权

US08377632B2 Method of reducing microloading effect 有权
标题翻译：降低微载荷效应的方法
公开(公告)号：US08377632B2
公开(公告)日：2013-02-19
申请号：US13118447
申请日：2011-05-29
申请人： Hsiu-Chun Lee , Yi-Nan Chen , Hsien-Wen Liu
发明人： Hsiu-Chun Lee , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： G03F7/26
CPC分类号： H01L21/3083
摘要： The present invention provides a method of reducing microloading effect by using a photoresist layer as a buffer. The method includes: providing a substrate defined with a dense region and an isolated region. Then, a dense feature pattern and an isolated feature pattern are formed on the dense region and the isolated region respectively. After that, a photoresist layer is formed to cover the isolated region. Finally, the substrate and the photoresist layer are etched by taking the dense feature pattern and the isolated feature pattern as a mask.
摘要翻译：本发明提供一种通过使用光致抗蚀剂层作为缓冲液来减少微载物效应的方法。该方法包括：提供限定有致密区域和隔离区域的衬底。然后，分别在密集区域和孤立区域上形成致密特征图案和隔离特征图案。之后，形成光致抗蚀剂层以覆盖隔离区域。最后，通过将密集特征图案和孤立的特征图案作为掩模来蚀刻基底和光致抗蚀剂层。

59. 发明申请

US20130017687A1 METHOD FOR FORMING OPENINGS IN SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中形成开口的方法
公开(公告)号：US20130017687A1
公开(公告)日：2013-01-17
申请号：US13183358
申请日：2011-07-14
申请人： Chih-Ching Lin , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chih-Ching Lin , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/306
CPC分类号： H01L21/76802 , H01L21/31144 , H01L21/32137
摘要： A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.
摘要翻译：提供了一种在半导体器件中形成开口的方法，包括：向半导体衬底提供其上顺序形成的氧化硅层，多晶硅层和氮化硅层; 图案化氮化硅层，在氮化硅层中形成第一开口，其中第一开口暴露多晶硅层的顶表面; 使用包括溴化氢（HBr），氧（O 2）和碳氟化合物（C x F y）的气体蚀刻剂进行第一蚀刻工艺，在多晶硅层中形成第二开口，其中与第二开口相邻的多晶硅层的侧壁基本上垂直于氧化硅层的顶表面，其中x在1-5之间，y在2-8之间; 去除氮化硅层; 以及进行第二蚀刻工艺，在由所述第二开口暴露的所述氧化硅层中形成第三开口。

60. 发明申请

US20120289133A1 CHEMICAL MECHANICAL POLISHING SYSTEM 有权
标题翻译：化学机械抛光系统
公开(公告)号：US20120289133A1
公开(公告)日：2012-11-15
申请号：US13106822
申请日：2011-05-12
申请人： Li-Chung Liu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Li-Chung Liu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： B24B55/00
CPC分类号： H01L21/02057 , B24B37/34 , B24B57/02 , H01L21/67046
摘要： A chemical mechanical polishing (CMP) system includes a wafer polishing unit producing a used slurry; a slurry treatment system for receiving and treating the used slurry to thereby produce an extracted basic solution; and a post-CMP cleaning unit utilizing the extracted basic solution to wash a polished wafer surface. The post-CMP cleaning unit includes a plurality of rollers for supporting and rotating a wafer, a brush for scrubbing the wafer, and a spray bar disposed in proximity to the brush for spraying the extracted basic solution onto the polished wafer surface.
摘要翻译：化学机械抛光（CMP）系统包括生产所用浆料的晶片抛光单元; 用于接收和处理所使用的浆料从而产生提取的碱性溶液的浆料处理系统; 以及利用所提取的碱性溶液洗涤抛光的晶片表面的后CMP清洁单元。后CMP清洁单元包括用于支撑和旋转晶片的多个辊，用于洗涤晶片的刷子和布置在刷子附近的喷杆，用于将提取的碱性溶液喷射到抛光的晶片表面上。

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