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1. 发明申请

US20120302030A1 METHOD OF FABRICATING A DEEP TRENCH DEVICE 审中-公开
标题翻译：制造深层TRENCH装置的方法
公开(公告)号：US20120302030A1
公开(公告)日：2012-11-29
申请号：US13118451
申请日：2011-05-29
申请人： Hsiu-Chun Lee , Yi-Nan Chen , Hsien-Wen Liu
发明人： Hsiu-Chun Lee , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/02 , H01L21/28
CPC分类号： H01L29/66181 , H01L29/945
摘要： A method of fabricating a deep trench capacitor includes the steps as follows. Firstly, a substrate having a trench therein is provided. Then, a bottom electrode is formed in the substrate around the trench. Later, a capacitor dielectric layer is formed to surround an inner sidewall of the trench. After that, a first conductive layer is form to fill up the trench. Subsequently, a material layer is formed on the substrate. Later, a hole is formed in the material layer, wherein the hole is directly above the trench. Finally, a second conductive layer is form to fill in the hole.
摘要翻译：制造深沟槽电容器的方法包括以下步骤。首先，提供其中具有沟槽的衬底。然后，在沟槽周围的衬底中形成底部电极。之后，形成电容器电介质层以包围沟槽的内侧壁。之后，形成填充沟槽的第一导电层。接着，在基板上形成材料层。之后，在该材料层中形成一个孔，其中孔直接在沟槽的上方。最后，第二导电层是填充孔的形式。

2. 发明申请

US20120301833A1 METHOD OF REDUCING MICROLOADING EFFECT 有权
标题翻译：减少微波效应的方法
公开(公告)号：US20120301833A1
公开(公告)日：2012-11-29
申请号：US13118447
申请日：2011-05-29
申请人： Hsiu-Chun Lee , Yi-Nan Chen , Hsien-Wen Liu
发明人： Hsiu-Chun Lee , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： G03F7/20
CPC分类号： H01L21/3083
摘要： The present invention provides a method of reducing microloading effect by using a photoresist layer as a buffer. The method includes: providing a substrate defined with a dense region and an isolated region. Then, a dense feature pattern and an isolated feature pattern are formed on the dense region and the isolated region respectively. After that, a photoresist layer is formed to cover the isolated region. Finally, the substrate and the photoresist layer are etched by taking the dense feature pattern and the isolated feature pattern as a mask.
摘要翻译：本发明提供一种通过使用光致抗蚀剂层作为缓冲液来减少微载物效应的方法。该方法包括：提供限定有致密区域和隔离区域的衬底。然后，分别在密集区域和孤立区域上形成致密特征图案和隔离特征图案。之后，形成光致抗蚀剂层以覆盖隔离区域。最后，通过将密集特征图案和孤立的特征图案作为掩模来蚀刻基底和光致抗蚀剂层。

3. 发明授权

US08377632B2 Method of reducing microloading effect 有权
标题翻译：降低微载荷效应的方法
公开(公告)号：US08377632B2
公开(公告)日：2013-02-19
申请号：US13118447
申请日：2011-05-29
申请人： Hsiu-Chun Lee , Yi-Nan Chen , Hsien-Wen Liu
发明人： Hsiu-Chun Lee , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： G03F7/26
CPC分类号： H01L21/3083
摘要： The present invention provides a method of reducing microloading effect by using a photoresist layer as a buffer. The method includes: providing a substrate defined with a dense region and an isolated region. Then, a dense feature pattern and an isolated feature pattern are formed on the dense region and the isolated region respectively. After that, a photoresist layer is formed to cover the isolated region. Finally, the substrate and the photoresist layer are etched by taking the dense feature pattern and the isolated feature pattern as a mask.
摘要翻译：本发明提供一种通过使用光致抗蚀剂层作为缓冲液来减少微载物效应的方法。该方法包括：提供限定有致密区域和隔离区域的衬底。然后，分别在密集区域和孤立区域上形成致密特征图案和隔离特征图案。之后，形成光致抗蚀剂层以覆盖隔离区域。最后，通过将密集特征图案和孤立的特征图案作为掩模来蚀刻基底和光致抗蚀剂层。

4. 发明授权

US08252684B1 Method of forming a trench by a silicon-containing mask 有权
标题翻译：通过含硅掩模形成沟槽的方法
公开(公告)号：US08252684B1
公开(公告)日：2012-08-28
申请号：US13118480
申请日：2011-05-30
申请人： Hsiu-Chun Lee , Yi-Nan Chen , Hsien-Wen Liu
发明人： Hsiu-Chun Lee , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/44 , H01L21/302 , H01L21/461
CPC分类号： H01L21/3081 , H01L21/3212
摘要： A method of forming a trench by a silicon-containing mask is provided in the present invention. The method includes providing a substrate covered with a silicon-containing mask. Then, anti-etch dopants are implanted into the silicon-containing mask to transform the silicon-containing mask into an etching resist mask. Later, the substrate and the etching resist mask are patterned to form at least one trench. Next, a silicon-containing layer is formed to fill into the trench. Finally, the silicon-containing layer is etched by taking the etching resist mask as a mask.
摘要翻译：在本发明中提供了通过含硅掩模形成沟槽的方法。该方法包括提供用含硅掩模覆盖的基底。然后，将抗蚀刻掺杂剂注入到含硅掩模中以将含硅掩模转变成抗蚀剂掩模。然后，对衬底和抗蚀剂掩模进行构图以形成至少一个沟槽。接下来，形成含硅层以填充到沟槽中。最后，通过将抗蚀剂掩模作为掩模来蚀刻含硅层。

5. 发明申请

US20120305525A1 METHOD OF REDUCING STRIATION ON A SIDEWALL OF A RECESS 审中-公开
标题翻译：减少碰撞的障碍的方法
公开(公告)号：US20120305525A1
公开(公告)日：2012-12-06
申请号：US13149861
申请日：2011-05-31
申请人： Hsiu-Chun Lee , Yi-Nan Chen , Hsien-Wen Liu
发明人： Hsiu-Chun Lee , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： C23F1/00 , B05D3/10
CPC分类号： G03F7/40 , G03F7/405 , H01L21/0273 , H01L21/3086
摘要： A method of reducing striation on a sidewall of a recess is provided. The method includes the steps of providing a substrate covered with a photoresist layer. Then, the photoresist layer is etched to form a patterned photoresist layer. Later, a repairing process is performed by treating the patterned photoresist layer with a repairing gas which is selected from the group consisting of CF4, HBr, O2 and He. Next, the substrate is etched by taking the patterned photoresist layer as a mask after the repairing process. Finally, the patterned photoresist layer is removed.
摘要翻译：提供一种减少凹槽侧壁上的条纹的方法。该方法包括提供被光致抗蚀剂层覆盖的基底的步骤。然后，蚀刻光致抗蚀剂层以形成图案化的光致抗蚀剂层。然后，通过用选自CF 4，HBr，O 2和He的修复气体处理图案化的光致抗蚀剂层来进行修复过程。接下来，在修复处理之后，通过将图案化的光致抗蚀剂层作为掩模来蚀刻基板。最后，去除图案化的光致抗蚀剂层。

6. 发明授权

US08963282B2 Crack stop structure and method for forming the same 有权
标题翻译：断裂结构及其形成方法
公开(公告)号：US08963282B2
公开(公告)日：2015-02-24
申请号：US13231961
申请日：2011-09-14
申请人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/72 , H01L23/31 , H01L23/00 , H01L21/78 , H01L21/56
CPC分类号： H01L23/562 , H01L21/311 , H01L21/561 , H01L21/76224 , H01L21/78 , H01L23/3178 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.
摘要翻译：半导体结构包括矩阵，集成电路和划线。矩阵包括划线区域和电路区域。集成电路设置在电路区域内。划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

7. 发明授权

US08692245B2 Crack stop structure and method for forming the same 有权
标题翻译：断裂结构及其形成方法
公开(公告)号：US08692245B2
公开(公告)日：2014-04-08
申请号：US13214227
申请日：2011-08-21
申请人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L23/544 , H01L23/482 , H01L21/762
CPC分类号： H01L21/76224 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure.
摘要翻译：本发明在第一方面提出了一种具有裂纹停止结构的半导体结构。半导体结构包括矩阵，集成电路和划线。矩阵包括划线区域和电路区域。集成电路设置在电路区域内。划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

8. 发明授权

US08642479B2 Method for forming openings in semiconductor device 有权
标题翻译：在半导体器件中形成开口的方法
公开(公告)号：US08642479B2
公开(公告)日：2014-02-04
申请号：US13183358
申请日：2011-07-14
申请人： Chih-Ching Lin , Yi-Nan Chen , Hsien-Wen Liu
发明人： Chih-Ching Lin , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/302
CPC分类号： H01L21/76802 , H01L21/31144 , H01L21/32137
摘要： A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.
摘要翻译：提供了一种在半导体器件中形成开口的方法，包括：向半导体衬底提供其上顺序形成的氧化硅层，多晶硅层和氮化硅层; 图案化氮化硅层，在氮化硅层中形成第一开口，其中第一开口暴露多晶硅层的顶表面; 使用包括溴化氢（HBr），氧（O 2）和碳氟化合物（C x F y）的气体蚀刻剂进行第一蚀刻工艺，在多晶硅层中形成第二开口，其中与第二开口相邻的多晶硅层的侧壁基本上垂直于氧化硅层的顶表面，其中x在1-5之间，y在2-8之间; 去除氮化硅层; 以及进行第二蚀刻工艺，在由所述第二开口暴露的所述氧化硅层中形成第三开口。

9. 发明授权

US08551881B2 Method of bevel trimming three dimensional semiconductor device 有权
标题翻译：斜面修边三维半导体器件的方法
公开(公告)号：US08551881B2
公开(公告)日：2013-10-08
申请号：US13093735
申请日：2011-04-25
申请人： Shing-Yih Shih , Yi-Nan Chen , Hsien-Wen Liu
发明人： Shing-Yih Shih , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/44
CPC分类号： H01L21/304 , H01L21/76898
摘要： A method of bevel trimming a three dimensional (3D) semiconductor device is disclosed, comprising providing a substrate with stack layers thereon and through substrate vias (TSV) therein, wherein an edge of the substrate is curved, performing a bevel trimming step to the curved edge of the substrate for obtaining a planar edge, and thinning the substrate to expose the through substrate vias.
摘要翻译：公开了一种斜面修整三维（3D）半导体器件的方法，包括提供衬底上的堆叠层，并通过其中的衬底通孔（TSV），其中衬底的边缘是弯曲的，对弯曲的边缘，用于获得平面边缘，并且使基板变薄以暴露通过的基板通孔。

10. 发明授权

US08487397B2 Method for forming self-aligned contact 有权
标题翻译：形成自对准接触的方法
公开(公告)号：US08487397B2
公开(公告)日：2013-07-16
申请号：US13093742
申请日：2011-04-25
申请人： Jar-Ming Ho , Yi-Nan Chen , Hsien-Wen Liu
发明人： Jar-Ming Ho , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L23/52
CPC分类号： H01L23/485 , H01L21/76897 , H01L21/823425 , H01L21/823468 , H01L21/823475 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor.
摘要翻译：具有自对准接触的集成电路包括其上形成有晶体管的衬底，介电间隔物，保护屏障和导电层。晶体管包括掩模层和形成在掩模层的相对侧上的一对绝缘间隔物。电介质间隔物部分地覆盖晶体管的至少一个绝缘间隔物。保护屏障形成在电介质间隔物上。导电层形成在掩模层，保护屏障，电介质间隔物，绝缘间隔物和介电间隔物上，作为用于接触晶体管的源/漏区的自对准接触。

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