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51. 发明授权

US08610240B2 Integrated circuit with multi recessed shallow trench isolation 有权
标题翻译：集成电路具有多凹槽浅沟槽隔离
公开(公告)号：US08610240B2
公开(公告)日：2013-12-17
申请号：US12838264
申请日：2010-07-16
申请人： Tsung-Lin Lee , Chang-Yun Chang
发明人： Tsung-Lin Lee , Chang-Yun Chang
IPC分类号： H01L21/70
CPC分类号： H01L21/762 , H01L21/76232
摘要： A system and method for forming multi recessed shallow trench isolation structures on substrate of an integrated circuit is provided. An integrated circuit includes a substrate, at least two shallow trench isolation (STI) structures formed in the substrate, an oxide fill disposed in the at least two STI structures, and semiconductor devices disposed on the oxide fill in the at least two STI structures. A first STI structure is formed to a first depth and a second STI structure is formed to a second depth. The oxide fill fills the at least two STI structures, and the first depth and the second depth are based on semiconductor device characteristics of semiconductor devices disposed thereon.
摘要翻译：提供了一种用于在集成电路的衬底上形成多凹槽浅沟槽隔离结构的系统和方法。集成电路包括衬底，在衬底中形成的至少两个浅沟槽隔离（STI）结构，设置在至少两个STI结构中的氧化物填充物，以及设置在至少两个STI结构中的氧化物填充物上的半导体器件。第一STI结构形成为第一深度，并且第二STI结构形成为第二深度。氧化物填充物填充至少两个STI结构，并且第一深度和第二深度基于设置在其上的半导体器件的半导体器件特性。

52. 发明授权

US08513078B2 Structure and method for fabricating fin devices 有权
标题翻译：制造鳍片器件的结构和方法
公开(公告)号：US08513078B2
公开(公告)日：2013-08-20
申请号：US13335479
申请日：2011-12-22
申请人： Ming-Feng Shieh , Chih-Hao Yu , Chang-Yun Chang
发明人： Ming-Feng Shieh , Chih-Hao Yu , Chang-Yun Chang
IPC分类号： H01L21/336
CPC分类号： H01L29/7855 , H01L21/823431 , H01L21/845
摘要： A structure and method of forming a semiconductor device with a fin is provided. In an embodiment a hard mask is utilized to pattern a gate electrode layer and is then removed. After the hard mask has been removed, the gate electrode layer may be separated into individual gate electrodes.
摘要翻译：提供一种形成具有翅片的半导体器件的结构和方法。在一个实施例中，使用硬掩模来图案化栅极电极层，然后将其去除。在硬掩模被去除之后，栅极电极层可以分离成单独的栅电极。

53. 发明申请

US20130187237A1 STRUCTURE AND METHOD FOR TRANSISTOR WITH LINE END EXTENSION 有权
标题翻译：具有线端延伸的晶体管的结构和方法
公开(公告)号：US20130187237A1
公开(公告)日：2013-07-25
申请号：US13356235
申请日：2012-01-23
申请人： Shao-Ming Yu , Chang-Yun Chang , Chih-Hao Chang , Hsin-Chih Chen , Kai-Tai Chang , Ming-Feng Shieh , Kuei-Liang Lu , Yi-Tang Lin
发明人： Shao-Ming Yu , Chang-Yun Chang , Chih-Hao Chang , Hsin-Chih Chen , Kai-Tai Chang , Ming-Feng Shieh , Kuei-Liang Lu , Yi-Tang Lin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41783 , H01L29/41791 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; an isolation feature formed in the semiconductor substrate; a first active region and a second active region formed in the semiconductor substrate, wherein the first and second active regions extend in a first direction and are separated from each other by the isolation feature; and a dummy gate disposed on the isolation feature, wherein the dummy gate extends in the first direction to the first active region from one side and to the second active region from another side.
摘要翻译：本公开提供了一种半导体结构。半导体结构包括半导体衬底; 形成在半导体衬底中的隔离特征; 形成在所述半导体衬底中的第一有源区和第二有源区，其中所述第一和第二有源区在第一方向上延伸并且通过隔离特征彼此分离; 以及设置在所述隔离特征上的伪栅极，其中所述伪栅极在第一方向上从另一侧的一侧延伸到所述第一有源区域并且从另一侧向所述第二有源区域延伸。

54. 发明申请

US20130140639A1 HIGH GATE DENSITY DEVICES AND METHODS 有权
标题翻译：高门密度装置和方法
公开(公告)号：US20130140639A1
公开(公告)日：2013-06-06
申请号：US13308671
申请日：2011-12-01
申请人： Ming-Feng Shieh , Chang-Yun Chang , Hsin-Chih Chen
发明人： Ming-Feng Shieh , Chang-Yun Chang , Hsin-Chih Chen
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L29/66545 , H01L21/76224 , H01L21/76232 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L29/66636
摘要： A semiconductor device with an isolation feature is disclosed. The semiconductor device includes a plurality of gate structures disposed on a semiconductor substrate, a plurality of gate sidewall spacers of a dielectric material formed on respective sidewalls of the plurality of gate structures, an interlayer dielectric (ILD) disposed on the semiconductor substrate and the gate structures, an isolation feature embedded in the semiconductor substrate and extended to the ILD and a sidewall spacer of the dielectric material disposed on sidewalls of extended portion of the isolation feature.
摘要翻译：公开了具有隔离特征的半导体器件。所述半导体器件包括设置在半导体衬底上的多个栅极结构，形成在所述多个栅极结构的相应侧壁上的介电材料的多个栅极侧壁间隔物，设置在所述半导体衬底上的层间电介质（ILD）结构，嵌入在半导体衬底中并延伸到ILD的隔离特征以及设置在隔离特征的延伸部分的侧壁上的介电材料的侧壁间隔物。

55. 发明申请

US20110212579A1 Fully Depleted SOI Multiple Threshold Voltage Application 有权
标题翻译：完全耗尽的SOI多阈值电压应用
公开(公告)号：US20110212579A1
公开(公告)日：2011-09-01
申请号：US13100673
申请日：2011-05-04
申请人： Hao-Yu Chen , Chang-Yun Chang , Di-Hong Lee , Fu-Liang Yang
发明人： Hao-Yu Chen , Chang-Yun Chang , Di-Hong Lee , Fu-Liang Yang
IPC分类号： H01L21/8234 , H01L21/265 , H01L21/28
CPC分类号： H01L29/78603 , H01L21/76267 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.
摘要翻译：集成电路包括在衬底中形成的衬底和掩埋电介质。掩埋电介质在第一区域具有第一厚度，在第二区域中具有第二埋入介质厚度，以及在第一和第二区域之间的台阶。半导体层覆盖在埋入的电介质上。

56. 发明申请

US20110156148A1 SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME USING SEMICONDUCTOR FIN DENSITY DESIGN RULES 有权
标题翻译：半导体器件及其制造方法使用半导体FIN密度设计规则
公开(公告)号：US20110156148A1
公开(公告)日：2011-06-30
申请号：US12649875
申请日：2009-12-30
申请人： Shao-Ming Yu , Chang-Yun Chang
发明人： Shao-Ming Yu , Chang-Yun Chang
IPC分类号： H01L27/088 , G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F2217/12 , H01L21/823431 , H01L21/823821 , H01L27/0207 , H01L27/105 , H01L27/10879 , H01L27/11 , H01L27/1116 , H01L29/785
摘要： A method for designing a semiconductor ic chip includes dividing the chip into functional blocks such as a core portion and one or more other functional cells and applying design rules concerning the spatial arrangement of semiconductor fins to the core portion but not to the other functional cells. The design guidelines include the application of design rules to some but not all functional blocks of the chip, may be stored on a computer-readable medium and the design of the semiconductor ic chip and the generation of a photomask set for manufacturing the semiconductor ic chip may be carried out using a CAD or other automated design system. The semiconductor ic chip formed in accordance with this method includes semiconductor fins that are formed in both the core portion and the other functional cells but are only required to be tightly packed in the core portion.
摘要翻译：一种用于设计半导体芯片的方法包括将芯片划分为诸如核心部分和一个或多个其它功能单元的功能块，并将关于半导体鳍片的空间布置的设计规则应用于核心部分而不是其它功能单元。设计指南包括将设计规则应用于芯片的一些而不是所有功能块，可以存储在计算机可读介质上，半导体芯片的设计以及用于制造半导体芯片的光掩模组的生成可以使用CAD或其他自动化设计系统进行。根据该方法形成的半导体IC芯片包括形成在芯部和其它功能单元两者中但仅需要紧密堆积在芯部中的半导体散热片。

57. 发明申请

US20110084340A1 Voids in STI Regions for Forming Bulk FinFETs 有权
标题翻译：用于形成大量FinFET的STI区域中的空隙
公开(公告)号：US20110084340A1
公开(公告)日：2011-04-14
申请号：US12612442
申请日：2009-11-04
申请人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
发明人： Feng Yuan , Tsung-Lin Lee , Hung-Ming Chen , Chang-Yun Chang
IPC分类号： H01L27/088 , H01L21/762
CPC分类号： H01L27/0203 , H01L21/76224 , H01L21/764 , H01L21/823431 , H01L21/823481 , H01L21/845
摘要： An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.
摘要翻译：集成电路结构包括：基板; 两个绝缘区域在衬底上，两个绝缘区域中的一个在其中包括空隙; 以及在所述两个绝缘区域之间并邻接所述两个绝缘区域的第一半导体条带。第一半导体条包括在两个绝缘区域的顶表面上形成翅片的顶部部分。

58. 发明授权

US07862962B2 Integrated circuit layout design 有权
标题翻译：集成电路布局设计
公开(公告)号：US07862962B2
公开(公告)日：2011-01-04
申请号：US12356405
申请日：2009-01-20
申请人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
发明人： Ming-Feng Shieh , Shinn-Sheng Yu , Anthony Yen , Shao-Ming Yu , Chang-Yun Chang , Jeff J. Xu , Clement Hsingjen Wann
IPC分类号： G03F9/00 , G03C5/00
CPC分类号： H01L27/0203 , G03F1/00 , G03F1/36 , H01L21/3086 , H01L21/823431 , H01L29/66795
摘要： Provided is a method including layout design of an integrated circuit. A first pattern is provided. The first pattern includes an array of dummy line features and a plurality of spacer elements abutting the dummy line features. A second pattern is provided. The second pattern defines an active region of an integrated circuit device. An edge spacer element of the active region is determined. A dummy line feature of the array of dummy line features is biased (e.g., increased in width), the dummy line feature is adjacent an edge spacer element.
摘要翻译：提供了一种包括集成电路的布局设计的方法。提供了第一种模式。第一图案包括虚线特征的阵列和与虚线特征相邻的多个间隔元件。提供了第二种模式。第二图案定义了集成电路器件的有源区。确定有源区的边缘间隔元件。假线特征阵列的虚线特征被偏置（例如，宽度增加），虚线特征与边缘间隔元件相邻。

59. 发明申请

US20060065948A1 Inductor energy loss reduction techniques 有权
标题翻译：电感衰减技术
公开(公告)号：US20060065948A1
公开(公告)日：2006-03-30
申请号：US10950046
申请日：2004-09-24
申请人： Andrew Yeh , Alex Chang , Sung-Pi Tseng , Chang-Yun Chang , Hao-Yu Chen , Fu-Liang Yang
发明人： Andrew Yeh , Alex Chang , Sung-Pi Tseng , Chang-Yun Chang , Hao-Yu Chen , Fu-Liang Yang
IPC分类号： H01L29/00
CPC分类号： H01L27/08 , H01F17/0006 , H01F2017/008 , H01L21/761 , H01L21/762 , H01L27/0688
摘要： An inductive device including an inductor coil located over a substrate, at least one electrically insulating layer interposing the inductor coil and the substrate, and a plurality of current interrupters each extending into the substrate, wherein a first aggregate outer boundary of the plurality of current interrupters substantially encompasses a second aggregate outer boundary of the inductor coil.
摘要翻译：一种电感器件，包括位于衬底上的电感器线圈，插入电感线圈和衬底的至少一个电绝缘层和各自延伸到衬底中的多个电流中断器，其中多个电流断流器的第一聚集外边界基本上包含电感线圈的第二聚集外边界。

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