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51. 发明申请

US20100067301A1 COLUMNAR NON-VOLATILE MEMORY DEVICES WITH AUXILIARY TRANSISTORS AND METHODS OF OPERATING THE SAME 有权
标题翻译：具有辅助晶体管的柱状非易失性存储器件及其操作方法
公开(公告)号：US20100067301A1
公开(公告)日：2010-03-18
申请号：US12493935
申请日：2009-06-29
申请人： Suk-pil Kim , Yoon-dong Park
发明人： Suk-pil Kim , Yoon-dong Park
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： H01L21/28273 , G11C16/10 , H01L21/28282 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/42328 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7883 , H01L29/792 , H01L29/7926
摘要： A non-volatile memory device includes at least one semiconductor column having a first sidewall and a second sidewall. The device also includes at least one gate electrode is disposed on the first sidewall and at least one control gate electrode disposed on the second sidewall. The device further includes at least one charge storage layer is disposed between the second sidewall and the at least one control gate electrode. The at least one gate electrode and the at least one control gate electrode may be disposed on opposite sides of the at least one semiconductor column such that they commonly control a channel region in the semiconductor column.
摘要翻译：非易失性存储器件包括至少一个具有第一侧壁和第二侧壁的半导体柱。该器件还包括设置在第一侧壁上的至少一个栅电极和设置在第二侧壁上的至少一个控制栅电极。该装置还包括至少一个电荷存储层设置在第二侧壁和至少一个控制栅电极之间。至少一个栅电极和至少一个控制栅电极可以设置在至少一个半导体柱的相对侧上，使得它们共同地控制半导体柱中的沟道区。

52. 发明申请

US20100065899A1 SEMICONDUCTOR DEVICES INCLUDING AUXILIARY GATE ELECTRODES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：包括辅助电极的半导体器件及其制造方法
公开(公告)号：US20100065899A1
公开(公告)日：2010-03-18
申请号：US12544631
申请日：2009-08-20
申请人： Suk-pil Kim , Yoon-dong Park , Jae-young Choi , June-mo Koo , Byung-hee Hong
发明人： Suk-pil Kim , Yoon-dong Park , Jae-young Choi , June-mo Koo , Byung-hee Hong
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/66833 , B82Y10/00 , G11C16/0483 , H01L27/11521 , H01L27/11568 , H01L27/12 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： A semiconductor device may include first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode may be provided on the semiconductor layer so that the semiconductor layer is between the primary gate electrode and the first and second auxiliary gate electrodes. Moreover, the first and second auxiliary gate electrodes may be configured to induce respective first and second field effect type source/drain regions in the semiconductor layer. Related methods are also discussed.
摘要翻译：半导体器件可以包括第一和第二辅助栅极电极以及与第一和第二辅助栅电极交叉的半导体层。主栅电极可以设置在半导体层上，使得半导体层位于主栅极和第一和第二辅助栅电极之间。此外，第一和第二辅助栅电极可以被配置为在半导体层中诱发相应的第一和第二场效应型源极/漏极区。还讨论了相关方法。

53. 发明授权

US07679960B2 Non-volatile memory device and method of operating the same 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US07679960B2
公开(公告)日：2010-03-16
申请号：US11980358
申请日：2007-10-31
申请人： Jae-woong Hyun , Kyu-charn Park , Yoon-dong Park , Won-joo Kim , Young-gu Jin , Suk-pil Kim , Kyoung-Iae Cho , Jung-hoon Lee , Seung-hwan Song
发明人： Jae-woong Hyun , Kyu-charn Park , Yoon-dong Park , Won-joo Kim , Young-gu Jin , Suk-pil Kim , Kyoung-Iae Cho , Jung-hoon Lee , Seung-hwan Song
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L27/1203
摘要： A highly integrated non-volatile memory device and a method of operating the non-volatile memory device are provided. The non-volatile memory device includes a semiconductor layer. A plurality of upper control gate electrodes are arranged above the semiconductor layer. A plurality of lower control gate electrodes are arranged below the semiconductor layer, and the plurality of upper control gate electrodes and the plurality of lower control gate electrodes are disposed alternately. A plurality of upper charge storage layers are interposed between the semiconductor layer and the upper control gate electrodes. A plurality of lower charge storage layers are interposed between the semiconductor layer and the lower control gate electrodes.
摘要翻译：提供高度集成的非易失性存储器件和操作非易失性存储器件的方法。非易失性存储器件包括半导体层。多个上控制栅电极设置在半导体层的上方。多个下部控制栅电极配置在半导体层的下方，多个上部控制栅极电极和多个下部控制栅极电极交替配置。多个上电荷存储层插入在半导体层和上控制栅电极之间。多个下电荷存储层插入在半导体层和下控制栅电极之间。

54. 发明申请

US20100012186A1 Bulb-Type Light Concentrated Solar Cell Module 审中-公开
标题翻译：灯泡型集中太阳能电池模块
公开(公告)号：US20100012186A1
公开(公告)日：2010-01-21
申请号：US12436832
申请日：2009-05-07
申请人： Yoon-dong Park , Kwang-soo Seol , Deok-kee Kim , Won-joo Kim , Young-gu Jin , Seung-hoon Lee , Suk-pil Kim
发明人： Yoon-dong Park , Kwang-soo Seol , Deok-kee Kim , Won-joo Kim , Young-gu Jin , Seung-hoon Lee , Suk-pil Kim
IPC分类号： H01L31/00
CPC分类号： H01L35/32 , H01L31/0547 , H02S10/10 , Y02E10/52
摘要： Provided is a bulb-type light concentrated solar cell module that includes a reflective mirror unit that is concavely formed to convergingly reflect sunlight and has a first hole on a bottom thereof; a solar cell that generates electrical energy in response to light received from the reflective mirror unit; a socket that blocks the first hole at a lower part of the reflective mirror unit and is fixed on the reflective mirror unit; and a power control unit that is electrically connected to the solar cell to generate electricity in the socket.
摘要翻译：本发明提供一种灯泡型光集中太阳能电池模块，其包括反射镜单元，该反射镜单元凹入地形成以会聚地反射太阳光，并且在其底部具有第一孔; 太阳能电池，其响应于从所述反射镜单元接收的光产生电能; 插座，其阻挡反射镜单元的下部的第一孔并固定在反射镜单元上; 以及电连接到太阳能电池以在插座中发电的电力控制单元。

55. 发明申请

US20090251963A1 Non-volatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20090251963A1
公开(公告)日：2009-10-08
申请号：US12385201
申请日：2009-04-01
申请人： Kwang-soo Seol , Yoon-dong Park , Suk-pil Kim
发明人： Kwang-soo Seol , Yoon-dong Park , Suk-pil Kim
IPC分类号： G11C16/04 , H01L29/792 , G11C16/06
CPC分类号： H01L29/7926 , G11C16/0483 , G11C16/10 , H01L27/0688 , H01L27/11517 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/66825 , H01L29/792
摘要： A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers.
摘要翻译：一种多层非易失性存储器件及其制造方法。非易失性存储器件可以包括具有堆叠结构的多个第一半导体层。多个控制栅电极可以跨越第一半导体层延伸。第一体接触层可以跨越第一半导体层延伸。可以在控制栅电极和第一半导体层之间插入多个电荷存储层。

56. 发明申请

US20090091975A1 Non-volatile memory device and operation method of the same 有权
标题翻译：非易失性存储器件及其操作方法相同
公开(公告)号：US20090091975A1
公开(公告)日：2009-04-09
申请号：US12081679
申请日：2008-04-18
申请人： Tae-hee Lee , Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon
发明人： Tae-hee Lee , Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , H01L27/11521 , H01L27/11568
摘要： Provided are a non-volatile memory device and an operation method of the same. The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor.
摘要翻译：提供了一种非易失性存储器件及其操作方法。非易失性存储器件可以包括一个或多个主串，每个主弦可以包括可以分别包括多个存储单元晶体管的第一和第二子串; 以及电荷供给线，其可以被配置为向每个主串的第一和第二子串提供电荷或阻止电荷，其中每个主串可以包括第一接地选择晶体管，其可以连接到第一子串 ; 可以连接到第一接地选择晶体管的第一子串选择晶体管; 可以连接到第二子串的第二接地选择晶体管; 以及可以连接到第二接地选择晶体管的第二子串选择晶体管。

57. 发明申请

US20080157182A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080157182A1
公开(公告)日：2008-07-03
申请号：US11980632
申请日：2007-10-31
申请人： Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Won-joo Kim , June-mo Koo , Kyoung-Iae Cho , Jae-Woong Hyun , Sung-jae Byun
发明人： Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Won-joo Kim , June-mo Koo , Kyoung-Iae Cho , Jae-Woong Hyun , Sung-jae Byun
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/785 , H01L21/76897 , H01L29/41791 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/7851 , H01L29/7881 , H01L29/792 , H01L2029/7858
摘要： Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.
摘要翻译：示例性实施例涉及包括鳍型沟道区的半导体器件及其制造方法。半导体器件包括半导体衬底，半导体柱和接触插塞。半导体衬底包括至少一对使用（或功能）作为活性区的翅片。半导体柱可以插入翅片的部分之间以连接散热片。接触插塞可以设置（或形成）在半导体柱上并电连接到散热片的顶表面。

58. 发明申请

US20080157176A1 Nonvolatile memory device and method of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080157176A1
公开(公告)日：2008-07-03
申请号：US11902511
申请日：2007-09-21
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Sung-jae Byun
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Sung-jae Byun
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/42336 , H01L29/66803
摘要： A nonvolatile memory device having lower bit line contact resistance and a method of fabricating the same is provided. In the nonvolatile memory device, a semiconductor substrate of a first conductivity type may include first and second fins. A common bit line electrode may connect one end of the first fin to one end of the second fin. A plurality of control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins. A first string selection gate electrode may be positioned between the common bit line electrode and the plurality of control gate electrodes. The first string selection gate electrode may cover the first and second fins and expand across the top surface of each of the first and second fins. A second string selection gate electrode may be positioned between the first string selection gate electrode and the plurality of control gate electrodes. The second string selection gate electrode may cover the first and second fins and expand across the top surface of each of the first and second fins. The first fin under the first string selection gate electrode and the second fin under the second string selection gate electrode may have a second conductivity type opposite to the first conductivity type.
摘要翻译：提供一种具有较低位线接触电阻的非易失性存储器件及其制造方法。在非易失性存储器件中，第一导电类型的半导体衬底可以包括第一和第二鳍片。公共位线电极可将第一鳍片的一端连接到第二鳍片的一端。多个控制栅极电极可以覆盖第一和第二鳍片并且跨越第一和第二鳍片中的每一个的顶表面膨胀。第一串选择栅极可以位于公共位线电极和多个控制栅电极之间。第一串选择栅电极可以覆盖第一和第二鳍片并且横跨第一和第二鳍片中的每一个的顶表面扩展。第二串选择栅电极可以位于第一串选择栅电极和多个控制栅电极之间。第二串选择栅电极可以覆盖第一和第二鳍片并且横跨第一和第二鳍片中的每一个的顶表面扩展。第一串选择栅电极下的第一鳍和第二串选择栅电极下的第二鳍可以具有与第一导电类型相反的第二导电类型。

59. 发明申请

US20080135916A1 Non-volatile memory device and method of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080135916A1
公开(公告)日：2008-06-12
申请号：US11987008
申请日：2007-11-26
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L29/7885 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/42344 , H01L29/42352 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： Provided are example embodiments of a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a control gate electrode arranged on a semiconductor substrate, a gate insulating layer interposed between the semiconductor substrate and the control gate electrode, a storage node layer interposed between the gate insulating layer and the control gate electrode, a blocking insulating layer interposed between the storage node layer and the control gate electrode, first dopant doping regions along a first side of the control gate electrode, and second dopant doping regions along a second side of the control gate electrode. The first dopant doping regions may alternate with the second dopant doping regions. Stated differently, each of the second dopant doping regions may be arranged in a region on the second side of the control gate electrode that is adjacent to one of the first dopant doping regions.
摘要翻译：提供了非易失性存储器件的示例性实施例及其制造方法。非易失性存储器件可以包括布置在半导体衬底上的控制栅电极，介于半导体衬底和控制栅电极之间的栅极绝缘层，介于栅极绝缘层和控制栅电极之间的存储节点层，插入在所述存储节点层和所述控制栅电极之间的阻挡绝缘层，沿着所述控制栅电极的第一侧的第一掺杂剂掺杂区域和沿着所述控制栅电极的第二侧的第二掺杂剂掺杂区域。第一掺杂剂掺杂区域可以与第二掺杂剂掺杂区域交替。换句话说，每个第二掺杂剂掺杂区域可以被布置在与第一掺杂剂掺杂区域中的一个相邻的控制栅电极的第二侧上的区域中。

60. 发明申请

US20080123390A1 Non-volatile memory device and method of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080123390A1
公开(公告)日：2008-05-29
申请号：US11882694
申请日：2007-08-03
申请人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , June-mo Koo
发明人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park , June-mo Koo
IPC分类号： G11C11/00 , H01L21/16
CPC分类号： G11C11/5678 , G11C13/0004 , H01L27/24
摘要： A non-volatile memory device and a method of fabricating the same are provided. In the non-volatile memory device, at least one first semiconductor layer of a first conductivity type may be formed spaced apart from each other on a portion of a substrate. A plurality of first resistance variation storage layers may contact first sidewalls of each of the at least one first semiconductor layer. A plurality of second semiconductor layers of a second conductivity type, opposite to the first conductivity type, may be interposed between the first sidewalls of each of the at least one first semiconductor layer and the plurality of first resistance variation storage layers. A plurality of bit line electrodes may be connected to each of the plurality of first resistance variation storage layers.
摘要翻译：提供了一种非易失性存储器件及其制造方法。在非易失性存储器件中，第一导电类型的至少一个第一半导体层可以在衬底的一部分上彼此间隔开形成。多个第一电阻变化存储层可以接触至少一个第一半导体层中的每一个的第一侧壁。与第一导电类型相反的第二导电类型的多个第二半导体层可以插入在至少一个第一半导体层和多个第一电阻变化存储层中的每一个的第一侧壁之间。多个位线电极可以连接到多个第一电阻变化存储层中的每一个。

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