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51. 发明申请

US20050098111A1 Apparatus for single-wafer-processing type CVD 审中-公开
标题翻译：单晶片处理型CVD装置
公开(公告)号：US20050098111A1
公开(公告)日：2005-05-12
申请号：US11014437
申请日：2004-12-16
申请人： Akira Shimizu , Hideaki Fukuda , Baiei Kawano , Kazuo Sato
发明人： Akira Shimizu , Hideaki Fukuda , Baiei Kawano , Kazuo Sato
IPC分类号： C23C16/44 , C23C16/455 , C23C16/458 , C23C16/54 , H01L21/285 , H01L21/3065 , C23C16/00
CPC分类号： C23C16/45521 , C23C16/4409 , C23C16/4412 , C23C16/4557 , C23C16/45572 , C23C16/4585 , C23C16/54
摘要： A single-wafer-processing type CVD apparatus includes: (a) a reaction chamber including: (i) a susceptor having at least one gas discharge hole to flow a gas into the reaction chamber via a back side and a periphery of the wafer into the reaction chamber; (ii) a showerhead; (iii) an exhaust duct positioned in the vicinity of the showerhead and provided circularly along an inner wall of the reaction chamber; and (iv) a circular separation plate provided coaxially with the exhaust duct to form a clearance with the bottom of the exhaust duct; and (b) a temperature-controlling apparatus for regulating the temperature of the showerhead. The separation plate has a sealing portion to seal a periphery of the susceptor and to separate the reaction chamber from a wafer-handling chamber when the susceptor rises.
摘要翻译：单晶加工型CVD装置包括：（a）反应室，包括：（i）基座，具有至少一个气体排出孔，用于将气体经由晶片的背面和周边流入反应室，进入反应室; （ii）喷头; （iii）位于喷头附近并沿着反应室的内壁圆周设置的排气管道; 和（iv）与排气管道同轴设置的与排气管道的底部形成间隙的圆形分离板; 和（b）用于调节喷头温度的温度控制装置。分离板具有密封部分，以密封基座的周边，并且当基座上升时将反应室与晶片处理室分开。

52. 发明授权

US06868010B2 Semiconductor memory device having row decoder in which high-voltage-applied portion is located adjacent to low-voltage-applied portion 失效
标题翻译：具有行解码器的半导体存储器件，其中高压施加部分位于与低电压施加部分相邻的位置
公开(公告)号：US06868010B2
公开(公告)日：2005-03-15
申请号：US10370512
申请日：2003-02-24
申请人： Akira Shimizu , Riichiro Shirota , Fumitaka Arai
发明人： Akira Shimizu , Riichiro Shirota , Fumitaka Arai
IPC分类号： G11C16/04 , G11C11/34 , G11C16/02 , G11C16/06 , G11C16/08 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/08 , G11C16/0483 , H01L27/105 , H01L27/115
摘要： A semiconductor memory device includes a first, second, and third memory cell transistors in which information can be electrically rewritten, addresses of which are consecutive in a row direction. One end of a current passage in each of a first, second, and third transfer transistors is connected to a control electrode of the first, second, and third memory cell transistors. A write voltage, a pass voltage lower than the write voltage, and a first voltage lower than the pass voltage are applied to the other ends of the first, second, and third transfer transistors. A first control section applies the first on-voltage to make the first transfer transistor conductive, to a gate of the first transfer transistor. A second control section applies a second on-voltage to make the second and third transfer transistors conductive, to gates of the second and third transfer transistors.
摘要翻译：半导体存储器件包括第一，第二和第三存储单元晶体管，其中信息可被电重写，其地址在行方向上是连续的。第一，第二和第三传输晶体管中的每一个中的电流通路的一端连接到第一，第二和第三存储单元晶体管的控制电极。写入电压，低于写入电压的通过电压以及低于通过电压的第一电压施加到第一，第二和第三转移晶体管的另一端。第一控制部分将第一传导晶体管导通的第一导通电压施加到第一传输晶体管的栅极。第二控制部分施加第二导通电压以使第二和第三转移晶体管导通到第二和第三转移晶体管的栅极。

53. 发明申请

US20050022737A1 Semiconductor-processing apparatus provided with susceptor and placing block 有权
标题翻译：设有基座和放置块的半导体处理设备
公开(公告)号：US20050022737A1
公开(公告)日：2005-02-03
申请号：US10897061
申请日：2004-07-22
申请人： Akira Shimizu , Hideaki Fukuda , Hiroki Arai , Baiei Kawano , Takayuki Yamagishi
发明人： Akira Shimizu , Hideaki Fukuda , Hiroki Arai , Baiei Kawano , Takayuki Yamagishi
IPC分类号： H01L21/683 , C23C16/00 , C23C16/458 , H01L21/205 , H01L21/677 , H01L21/68
CPC分类号： C23C16/4585
摘要： A semiconductor-processing apparatus comprises a susceptor and removable placing blocks detachably placed at a periphery of the susceptor for transferring a substrate. Retractable supporting members are provided for detaching/attaching the placing blocks from/to the susceptor.
摘要翻译：半导体处理装置包括基座和可拆卸地放置在基座周边的可拆卸放置块，用于传送基板。提供可伸缩的支撑构件用于将放置块从基座分离/附接到基座。

54. 发明授权

US06645873B2 Method for manufacturing a semiconductor device 有权
公开(公告)号：US06645873B2
公开(公告)日：2003-11-11
申请号：US09881255
申请日：2001-06-14
申请人： Akira Shimizu , Fumitoshi Ozaki
发明人： Akira Shimizu , Fumitoshi Ozaki
IPC分类号： H01L21302
CPC分类号： H01L21/76807 , H01L21/31116 , H01L21/31629 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： A method of processing a semiconductor substrate involves etching a SiOF layer with HF or HF+H2O. The method can be used to form hollow structures in semiconductor substrates and thus provides a way to make interlayer insulators.

55. 发明授权

US06562908B2 Thermoplastic resin composition and shaped articles thereof 失效
公开(公告)号：US06562908B2
公开(公告)日：2003-05-13
申请号：US10040351
申请日：2002-01-09
申请人： Shinichiro Zen , Akira Shimizu
发明人： Shinichiro Zen , Akira Shimizu
IPC分类号： C08L2300
CPC分类号： C08L101/00 , C08L2666/04
摘要： Described are a thermoplastic resin composition containing (A): one or more rubber reinforced thermoplastic resins, (B): one or more acrylic resins and (C): one or more thermoplastic norbornene resins, and further containing (D): one or more styrenic resins other than (A) and (E): coloring agents as needed, and a shaped article obtained by forming the composition. Described thermoplastic resin composition is excellent in heat resistance, strength and processability, and excellent in laser marking properties, so that it is useful for various applications.

56. 发明授权

US06330425B1 Double-surface printing apparatus 有权
标题翻译：双面印刷装置
公开(公告)号：US06330425B1
公开(公告)日：2001-12-11
申请号：US09558041
申请日：2000-04-26
申请人： Yoshio Ohuchi , Akira Shimizu , Nobuaki Fukasawa , Michio Sumiyoshi , Satoshi Narita , Kiminori Takada
发明人： Yoshio Ohuchi , Akira Shimizu , Nobuaki Fukasawa , Michio Sumiyoshi , Satoshi Narita , Kiminori Takada
IPC分类号： G03G1500
CPC分类号： G03G15/234
摘要： A double-surface printing apparatus, which is small-sized and has a simple construction to make it impossible to take out a sheet, of which one surface has been subjected to printing, from outside. The apparatus includes a paper discharge tray, to which sheets having been subjected to printing are discharged; a sheet reversing mechanism including a reversal/temporary storage unit for guiding a sheet in a direction different from a discharge direction toward the paper discharge tray, once exposing the sheet outside of the apparatus, and rotating conveying rollers in an opposite direction to thereby reverse the sheet; and a protective cover, which covers the sheet conveyed to the reversal/temporary storage unit so that a sheet, of which one-surface has been subjected to printing, cannot be taken out from outside.
摘要翻译：一种双面打印装置，其尺寸小并且具有简单的结构，使得不可能从外部取出其表面已经被印刷的片材。该设备包括排纸托盘，已经印刷的纸张被排出到该排纸托盘; 纸张反转机构，其包括用于将片材沿着与排出方向不同的方向朝向排纸盘引导的反转/临时存储单元，一旦暴露出设备外部的片材，并且使相反方向的输送辊转动，片; 以及保护盖，其覆盖输送到反转/临时存储单元的纸张，使得其中一个表面已被印刷的纸张不能从外部取出。

57. 发明授权

US6001677A Method for fabricating CMOS transistors by implanting into polysilicon 失效
标题翻译：通过植入多晶硅制造CMOS晶体管的方法
公开(公告)号：US6001677A
公开(公告)日：1999-12-14
申请号：US65334
申请日：1998-04-23
申请人： Akira Shimizu
发明人： Akira Shimizu
IPC分类号： H01L21/28 , H01L21/265 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823842
摘要： A method for fabricating MOS transistors comprises the steps of forming a polysilicon layer, having an underlying gate oxide layer on the major surface of a silicon substrate, providing a mask to cover a predetermined portion except the portion for an N-type polysilicon layer to be formed, doping the polysilicon layer uncovered by the first mask with N-type ions, providing a second mask to cover a predetermined portion except the portion for a P-type polysilicon layer to be formed, doping the polysilicon layer uncovered by the second mask with boron ions, subjecting the polysilicon layer to a patterning process to define gate electrodes of an NMOS and PMOS transistors, providing a third mask to cover a predetermined portion except the portion for an NMOS transistor to be formed, doping N-type ions into substrate portion for the NMOS transistor to be formed using the third mask and the gate electrodes as a mask to thereby form a source and a drain of the NMOS transistor, forming a silicon oxide layer over each of the gate electrodes, providing a fourth mask to cover a predetermined portion except the portion for a PMOS transistor to be formed, and doping BF.sub.2 ions into substrate portion for PMOS transistors to be formed using the fourth mask and gate electrodes overlaid by the silicon oxide layer as a mask, to thereby form source and drain regions of the PMOS transistors.
摘要翻译：一种用于制造MOS晶体管的方法包括以下步骤：在硅衬底的主表面上形成具有下面的栅氧化层的多晶硅层，提供掩模以覆盖除了用于N型多晶硅层的部分之外的预定部分形成，用N型离子掺杂由第一掩模未覆盖的多晶硅层，提供第二掩模以覆盖除了待形成的P型多晶硅层的部分之外的预定部分，将由第二掩模未覆盖的多晶硅层掺杂硼离子，对多晶硅层进行图形化处理以限定NMOS和PMOS晶体管的栅电极，提供第三掩模以覆盖除了要形成的NMOS晶体管的部分之外的预定部分，将N型离子掺杂到衬底部分为了使用第三掩模和栅电极作为掩模形成NMOS晶体管，从而形成NMOS晶体管的源极和漏极，形成硅在每个栅电极上的氧化物层上，提供第四掩模以覆盖除了要形成的PMOS晶体管的部分之外的预定部分，并且将BF 2离子掺杂到使用第四掩模和栅电极形成的PMOS晶体管的衬底部分由氧化硅层覆盖作为掩模，从而形成PMOS晶体管的源区和漏区。

58. 发明授权

US5602106A 16-membered macrolide derivatives 失效
标题翻译： 16元大环内酯衍生物
公开(公告)号：US5602106A
公开(公告)日：1997-02-11
申请号：US271996
申请日：1994-07-08
申请人： Keiichi Ajito , Osamu Hara , Ken-ichi Kurihara , Nobue Kikuchi , Minako Araake , Akira Shimizu , Tsuneo Okonogi , Shigeharu Inouye , Seiji Shibahara
发明人： Keiichi Ajito , Osamu Hara , Ken-ichi Kurihara , Nobue Kikuchi , Minako Araake , Akira Shimizu , Tsuneo Okonogi , Shigeharu Inouye , Seiji Shibahara
IPC分类号： C07H17/08 , A61K31/70
CPC分类号： C07H17/08
摘要： 16-membered macrolide derivatives represented by the formula (I): ##STR1## wherein R.sup.1 represents a hydrogen atom or a substituent group which protects a hydroxyl group; R.sup.2 represents a hydrogen atom or a substituent group which protects a hydroxyl group; R.sup.3 represents a hydrogen atom or a straight-chain aliphatic acyl group having 2 to 4 carbon atoms; and R.sup.4 represents a hydrogen atom or a straight-chain aliphatic or aromatic acyl group having 1 to 10 carbon atoms;or a pharmaceutically acceptable salt thereof are disclosed.A novel process for producing these 16-membered macrolide derivatives is also disclosed.
摘要翻译：由式（I）表示的16元大环内酯衍生物：其中R 1表示氢原子或保护羟基的取代基; R2表示氢原子或保护羟基的取代基; R3表示氢原子或碳原子数2〜4的直链脂肪族酰基， R 4表示氢原子或碳原子数1〜10的直链脂肪族或芳香族酰基，或其药学上可接受的盐。还公开了一种制备这些16元大环内酯衍生物的新方法。

59. 发明授权

US5548411A Facsimile apparatus 失效
标题翻译：传真机
公开(公告)号：US5548411A
公开(公告)日：1996-08-20
申请号：US427279
申请日：1995-04-24
申请人： Kazutaka Sato , Michihiro Watanabe , Masahisa Aoyagi , Taisaku Seino , Katsuo Ohki , Hiromitsu Fukuda , Hideyuki Kawase , Kimio Oga , Akira Shimizu , Youichi Narui , Tsuguo Suzuki , Yasuo Otsuka , Kazutoshi Konno
发明人： Kazutaka Sato , Michihiro Watanabe , Masahisa Aoyagi , Taisaku Seino , Katsuo Ohki , Hiromitsu Fukuda , Hideyuki Kawase , Kimio Oga , Akira Shimizu , Youichi Narui , Tsuguo Suzuki , Yasuo Otsuka , Kazutoshi Konno
IPC分类号： H04N1/00 , H04N1/04
CPC分类号： H04N1/0057 , H04N1/00543
摘要： A facsimile apparatus has a lower structure and an upper structure which is swingable between a raised open position an a lowered close position about a pivot located at a lower part of the rear end portion of the apparatus. A thermal print head is fixed to the front end portion of the upper structure. A recording medium conveyor roller is fixed to the front end portion of the lower structure. A linear image sensor and an original sheet conveyor roller are fixed to a central portion of the lower structure. The recording medium is placed on the lower structure at a position between the thermal print head and the linear image sensor.
摘要翻译：传真装置具有下部结构和上部结构，所述上部结构可以在围绕位于所述装置的后端部分的下部的枢轴的升高的打开位置和降低的关闭位置之间摆动。热敏打印头固定到上部结构的前端部分。记录介质传送辊固定到下部结构的前端部分。线性图像传感器和原稿输送辊固定到下部结构的中心部分。记录介质在热打印头和线性图像传感器之间的位置处放置在下部结构上。

60. 发明授权

US5305331A Data logging apparatus with memory and pattern testing device 失效
标题翻译：具有记忆和图案测试装置的数据记录仪
公开(公告)号：US5305331A
公开(公告)日：1994-04-19
申请号：US684411
申请日：1991-04-12
申请人： Toshiya Sato , Akira Shimizu , Hajime Hiroi , Hirohisa Ooishi
发明人： Toshiya Sato , Akira Shimizu , Hajime Hiroi , Hirohisa Ooishi
IPC分类号： G01R31/28 , G01R31/3193 , G06F11/22 , G06F11/00
CPC分类号： G01R31/31935
摘要： A data logging apparatus for a device function tester comprises a first shift circuit (1) supplied with an output signal of the tester and a strobe signal for shifting the output of the tester by n rates under the timing of a basic clock (T.sub.0), a second shift circuit (2) for shifting the timing of the basic clock (T.sub.0) by n rates, a write pulse generating circuit (3) supplied with the output signal of the shift circuit (2), a third shift circuit (4) supplied with a memory address signal for shifting it by n rates under the timing of the basic clock (T.sub.0), a fourth shift circuit (5) for shifting a pattern address signal by n rates under the timing of the basic clock (T.sub.0), a first memory (6) supplied with the output signal of the first shift circuit (1) and the output signal of the third shift circuit (1) for storing the result of the test shifted by n rates in response to a write command signal, and a second memory ( 7) supplied with the output of the fourth shift circuit (5) and the output of the third shift circuit (4) for storing the pattern address shifted by n rates in response to the write command signal. Data logging can be accomplished without being affected by variable time intervals of write enable strobe pulses.
摘要翻译：一种用于设备功能测试器的数据记录装置，包括：提供有测试仪的输出信号的第一移位电路（1）和用于在基本时钟（T0）的定时下将测试仪的输出移位n个速率的选通信号，用于将基本时钟（T0）的定时移位n个速率的第二移位电路（2），提供有移位电路（2）的输出信号的写脉冲发生电路（3），第三移位电路（4）提供存储器地址信号，用于在基本时钟（T0）的定时下移位n个速率;第四移位电路（5），用于在基本时钟（T0）的定时下将模式地址信号移位n个速率，提供有第一移位电路（1）的输出信号的第一存储器（6）和第三移位电路（1）的输出信号，用于存储响应写入命令信号移位n个速率的测试结果，以及提供有第四移位电路（5）的输出和外部输出的第二存储器（7） t用于响应写入命令信号存储以n个速率移位的模式地址。可以在不受写使能选通脉冲的可变时间间隔的影响的情况下实现数据记录。

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