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51. 发明授权

US07962722B2 Branch target address cache with hashed indices 有权
标题翻译：具有散列索引的分支目标地址缓存
公开(公告)号：US07962722B2
公开(公告)日：2011-06-14
申请号：US12024219
申请日：2008-02-01
申请人： Sheldon B. Levenstein , David S. Levitan , Lixin Zhang
发明人： Sheldon B. Levenstein , David S. Levitan , Lixin Zhang
IPC分类号： G06F9/32 , G06F9/34
CPC分类号： G06F9/3806 , G06F9/3844
摘要： In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including a branch target address cache (BTAC) including a plurality of entries for storing branch target address predictions. The BTAC includes index logic that selects an entry to access utilizing a BTAC index based upon at least a set of higher order bits of an instruction address and a set of lower order bits of the instruction address.
摘要翻译：在至少一个实施例中，处理器包括至少一个执行单元，其执行耦合到至少一个执行单元的指令和指令排序逻辑，其从存储器系统取出用于由至少一个执行单元执行的指令。指令排序逻辑包括分支目标地址高速缓存（BTAC），其包括用于存储分支目标地址预测的多个条目。 BTAC包括索引逻辑，其基于指令地址的至少一组较高位和指令地址的较低位的集合来选择使用BTAC索引的访问条目。

52. 发明申请

US20110055827A1 Cache Partitioning in Virtualized Environments 有权
标题翻译：虚拟化环境中的高速缓存分区
公开(公告)号：US20110055827A1
公开(公告)日：2011-03-03
申请号：US12546791
申请日：2009-08-25
申请人： Jiang Lin , Lixin Zhang
发明人： Jiang Lin , Lixin Zhang
IPC分类号： G06F12/08 , G06F9/455
CPC分类号： G06F9/455 , G06F12/084 , G06F12/0842 , G06F12/0848 , G06F12/0864 , G06F12/121
摘要： A mechanism is provided in a virtual machine monitor for providing cache partitioning in virtualized environments. The mechanism assigns a virtual identification (ID) to each virtual machine in the virtualized environment. The processing core stores the virtual ID of the virtual machine in a special register. The mechanism also creates an entry for the virtual machine in a partition table. The mechanism may partition a shared cache using a vertical (way) partition and/or a horizontal partition. The entry in the partition table includes a vertical partition control and a horizontal partition control. For each cache access, the virtual machine passes the virtual ID along with the address to the shared cache. If the cache access results in a miss, the shared cache uses the partition table to select a victim cache line for replacement.
摘要翻译：在虚拟机监视器中提供了一种机制，用于在虚拟化环境中提供高速缓存分区。该机制为虚拟化环境中的每个虚拟机分配一个虚拟标识（ID）。处理核心将虚拟机的虚拟ID存储在专用寄存器中。该机制还为分区表中的虚拟机创建一个条目。该机制可以使用垂直（方式）分区和/或水平分区来划分共享高速缓存。分区表中的条目包括垂直分区控制和水平分区控制。对于每个缓存访问，虚拟机将虚拟ID与该地址一起传递到共享缓存。如果缓存访问导致错过，共享缓存使用分区表选择受害缓存行进行替换。

53. 发明申请

US20100115204A1 NON-UNIFORM CACHE ARCHITECTURE (NUCA) 有权
标题翻译：非均匀缓存架构（NUCA）
公开(公告)号：US20100115204A1
公开(公告)日：2010-05-06
申请号：US12264682
申请日：2008-11-04
申请人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Xiaoxia Wu , Lixin Zhang
发明人： Jian Li , Ramakrishnan Rajamony , William E. Speight , Xiaoxia Wu , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0846 , G06F12/0848 , G06F12/123 , G06F2212/225 , G06F2212/271
摘要： In one embodiment, a cache memory includes a cache array including a plurality of entries for caching cache lines of data, where the plurality of entries are distributed between a first region implemented in a first memory technology and a second region implemented in a second memory technology. The cache memory further includes a cache directory of the contents of the cache array and a cache controller that controls operation of the cache memory.
摘要翻译：在一个实施例中，高速缓冲存储器包括高速缓存阵列，其包括用于缓存高速缓存数据行的多个条目，其中多个条目分布在以第一存储器技术实现的第一区域和在第二存储器技术中实现的第二区域之间。高速缓冲存储器还包括高速缓存阵列的内容的高速缓存目录和控制高速缓冲存储器的操作的高速缓存控制器。

54. 发明授权

US07698508B2 System and method for reducing unnecessary cache operations 失效
标题翻译：减少不必要的缓存操作的系统和方法
公开(公告)号：US07698508B2
公开(公告)日：2010-04-13
申请号：US11674960
申请日：2007-02-14
申请人： Ramakrishnan Rajamony , Hazim Shafi , William Evan Speight , Lixin Zhang
发明人： Ramakrishnan Rajamony , Hazim Shafi , William Evan Speight , Lixin Zhang
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/0817
摘要： A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure. In response to replacing data from the upper memory cache, the upper memory cache examines the write-back data structure to determine whether or not the data is present in the lower memory cache. If the data is present in the lower memory cache, the data is replaced in the upper memory cache without casting out the data to the lower memory cache.
摘要翻译：一种用于数据处理系统中缓存管理的系统和方法。数据处理系统包括处理器和存储器层级。存储器层级至少包括上部存储器高速缓存，至少下部存储器高速缓存和回写数据结构。响应于从上部存储器高速缓存替换数据，上部存储器高速缓存检查回写数据结构以确定数据是否存在于下部存储器高速缓存中。如果数据存在于较低存储器高速缓存中，则数据将在上部存储器高速缓存中替换，而不会将数据丢弃到较低的内存高速缓存。

55. 发明申请

US20090288063A1 PREDICATION SUPPORTING CODE GENERATION BY INDICATING PATH ASSOCIATIONS OF SYMMETRICALLY PLACED WRITE INSTRUCTIONS 有权
标题翻译：通过表示对称写入指令的路径协会来确定支持代码生成
公开(公告)号：US20090288063A1
公开(公告)日：2009-11-19
申请号：US12123083
申请日：2008-05-19
申请人： Ram Rangan , Mark W. Stephenson , Lixin Zhang
发明人： Ram Rangan , Mark W. Stephenson , Lixin Zhang
IPC分类号： G06F9/44
CPC分类号： G06F8/4451
摘要： A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition.
摘要翻译：用于无序指令处理的预测技术提供了低硬件开销的有效的无序执行。一个特殊的操作代码区分了程序代码的统一区域，其中包含依赖于条件分辨率的预测指令。与特殊操作码相关联的字段或操作数指示操作码后面的指令数，并且还包含每个指令与其对应条件路径的关联的指示。区域中的每个条件寄存器写入对于每个条件路径都有相应的寄存器写入，如果对称性尚未存在，编译器插入附加的寄存器写入，形成一组寄存器写操作。因此，统一的指令流可以使用与相同重名资源相关联的寄存器写入进行解码和分派，并且通过执行由解析条件指定的特定指令来解决条件寄存器写入。

56. 发明申请

US20090199190A1 System and Method for Priority-Based Prefetch Requests Scheduling and Throttling 有权
标题翻译：基于优先级的预取请求调度和调节的系统和方法
公开(公告)号：US20090199190A1
公开(公告)日：2009-08-06
申请号：US12024389
申请日：2008-02-01
申请人： Lei Chen , Lixin Zhang
发明人： Lei Chen , Lixin Zhang
IPC分类号： G06F9/46
CPC分类号： G06F12/0862 , G06F9/3455 , G06F9/383 , G06F2212/1016
摘要： A method, processor, and data processing system for implementing a framework for priority-based scheduling and throttling of prefetching operations. A prefetch engine (PE) assigns a priority to a first prefetch stream, indicating a relative priority for scheduling prefetch operations of the first prefetch stream. The PE monitors activity within the data processing system and dynamically updates the priority of the first prefetch stream based on the activity (or lack thereof). Low priority streams may be discarded. The PE also schedules prefetching in a priority-based scheduling sequence that corresponds to the priority currently assigned to the scheduled active streams. When there are no prefetches within a prefetch queue, the PE triggers the active streams to provide prefetches for issuing. The PE determines when to throttle prefetching, based on the current usage level of resources relevant to completing the prefetch.
摘要翻译：一种用于实现基于优先级调度和限制预取操作的框架的方法，处理器和数据处理系统。预取引擎（PE）将优先级分配给第一预取流，指示用于调度第一预取流的预取操作的相对优先级。 PE监视数据处理系统内的活动，并基于活动（或缺乏）动态地更新第一预取流的优先级。低优先级流可能被丢弃。 PE还在基于优先级的调度序列中调度预取，该调度序列对应于当前分配给调度的活动流的优先级。当预取队列中没有预取时，PE触发活动流以提供预取。根据与完成预取相关的资源的当前使用水平，PE确定何时限制预取。

57. 发明申请

US20090198907A1 Dynamic Adjustment of Prefetch Stream Priority 有权
标题翻译：动态调整预取流优先级
公开(公告)号：US20090198907A1
公开(公告)日：2009-08-06
申请号：US12024411
申请日：2008-02-01
申请人： William E. Speight , Lixin Zhang
发明人： William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/1041 , G06F2212/6024
摘要： A method, processor, and data processing system for dynamically adjusting a prefetch stream priority based on the consumption rate of the data by the processor. The method includes a prefetch engine issuing a prefetch request of a first prefetch stream to fetch one or more data from the memory subsystem. The first prefetch stream has a first assigned priority that determines a relative order for scheduling prefetch requests of the first prefetch stream relative to other prefetch requests of other prefetch streams. Based on the receipt of a processor demand for the data before the data returns to the cache or return of the data along time before the receiving the processor demand, logic of the prefetch engine dynamically changes the first assigned priority to a second higher or lower priority, which priority is subsequently utilized to schedule and issue a next prefetch request of the first prefetch stream.
摘要翻译：一种用于基于处理器的数据的消耗速率动态地调整预取流优先级的方法，处理器和数据处理系统。该方法包括预取引擎，其发出第一预取流的预取请求以从存储器子系统获取一个或多个数据。第一预取流具有第一分配的优先级，其相对于其他预取流的其他预取请求确定第一预取流的调度预取请求的相对顺序。基于在数据返回到高速缓存之前对数据的接收处理器需求，或者在接收到处理器需求之前的时间返回数据，预取引擎的逻辑动态地将第一分配的优先级改变为第二较高或更低的优先级随后利用该优先级来调度和发出第一预取流的下一个预取请求。

58. 发明申请

US20090198903A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT VARY AN AMOUNT OF DATA RETRIEVED FROM MEMORY BASED UPON A HINT 失效
标题翻译：数据处理系统，处理器和方法，从基于记忆的记忆中提取的数据量变化不大
公开(公告)号：US20090198903A1
公开(公告)日：2009-08-06
申请号：US12024170
申请日：2008-02-01
申请人： RAVI K. ARIMILLI , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
发明人： RAVI K. ARIMILLI , Gheorghe C. Cascaval , Balaram Sinharoy , William E. Speight , Lixin Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0822 , G06F2212/507 , G06F2212/6028
摘要： In at least one embodiment, a processor detects during execution of program code whether a load instruction within the program code is associated with a hint. In response to detecting that the load instruction is not associated with a hint, the processor retrieves a full cache line of data from the memory hierarchy into the processor in response to the load instruction. In response to detecting that the load instruction is associated with a hint, a processor retrieves a partial cache line of data into the processor from the memory hierarchy in response to the load instruction.
摘要翻译：在至少一个实施例中，处理器在执行程序代码期间检测程序代码内的加载指令是否与提示相关联。响应于检测到加载指令不与提示相关联，处理器响应于加载指令从存储器层次结构检索完整的高速缓存行数据到处理器。响应于检测到加载指令与提示相关联，处理器响应于加载指令从存储器层次结构检索数据的部分高速缓存行到处理器中。

59. 发明申请

US20090077354A1 Techniques for Predicated Execution in an Out-of-Order Processor 有权
标题翻译：在无序处理器中执行预处理的技术
公开(公告)号：US20090077354A1
公开(公告)日：2009-03-19
申请号：US11856170
申请日：2007-09-17
申请人： Ram Rangan , William E. Speight , Mark W. Stephenson , Lixin Zhang
发明人： Ram Rangan , William E. Speight , Mark W. Stephenson , Lixin Zhang
IPC分类号： G06F9/318
CPC分类号： G06F9/3851 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/30094 , G06F9/384
摘要： A technique for handling predicated code in an out-of-order processor includes detecting a predicate defining instruction associated with a predicated code region. Renaming of predicated instructions, within the predicated code region, is then stalled until a predicate of the predicate defining instruction is resolved.
摘要翻译：用于处理无序处理器中的预定代码的技术包括检测与预定代码区相关联的谓词定义指令。然后，在预定的代码区域内重命名预定的指令，直到谓词定义指令的谓词解决为止。

60. 发明申请

US20090049286A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING IMPROVED BRANCH TARGET ADDRESS CACHE 失效
标题翻译：数据处理系统，具有改进的分支目标地址高速缓存的数据处理的处理器和方法
公开(公告)号：US20090049286A1
公开(公告)日：2009-02-19
申请号：US11837893
申请日：2007-08-13
申请人： David S. Levitan , William E. Speight , Lixin Zhang
发明人： David S. Levitan , William E. Speight , Lixin Zhang
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3844
摘要： A processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a level one branch target address cache (BTAC) and a level two BTAC each having a respective plurality of entries each associating at least a tag with a predicted branch target address. The branch logic accesses the level one and level two BTACs in parallel with a tag portion of a first instruction fetch address to obtain a first predicted branch target address from the level one BTAC for use as a second instruction fetch address in a first processor clock cycle and a second predicted branch target address from the level two BTAC for use as a third instruction fetch address in a later second processor clock cycle.
摘要翻译：处理器包括执行单元和从存储器系统执行指令的指令排序逻辑。指令排序逻辑包括分支逻辑，该分支逻辑输出用作指令获取地址的预测分支目标地址。分支逻辑包括一级分支目标地址高速缓存（BTAC）和二级BTAC，每级具有相应的多个条目，每个条目将至少一个标签与预测的分支目标地址相关联。分支逻辑与第一指令获取地址的标签部分并行地访问一级和二级BTAC以从第一级BTAC获得第一预测分支目标地址，以在第一处理器时钟周期中用作第二指令获取地址以及来自第二级BTAC的第二预测分支目标地址，以在随后的第二处理器时钟周期中用作第三指令提取地址。

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