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51. 发明授权

US5877986A Multi-state Flash EEprom system on a card that includes defective cell substitution 失效
标题翻译：包含有缺陷的单元替换的卡上的多状态闪存EEprom系统
公开(公告)号：US5877986A
公开(公告)日：1999-03-02
申请号：US999472
申请日：1997-12-29
申请人： Eliyahou Harari , Robert D. Norman , Sanjay Mehrotra
发明人： Eliyahou Harari , Robert D. Norman , Sanjay Mehrotra
IPC分类号： G11C16/02 , G06F3/06 , G06F11/10 , G06F12/00 , G06F12/02 , G06F12/08 , G06F12/12 , G06F12/16 , G11C5/00 , G11C8/02 , G11C8/12 , G11C11/56 , G11C16/06 , G11C16/10 , G11C16/16 , G11C16/34 , G11C17/00 , G11C29/00 , G11C29/04 , G11C29/26 , G11C29/34 , G11C29/52 , H01L21/82 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： G11C29/26 , G06F12/0246 , G06F12/0802 , G06F12/0804 , G06F12/0866 , G06F12/0875 , G06F12/123 , G06F3/0601 , G06F3/0616 , G06F3/064 , G06F3/0652 , G06F3/0679 , G06F3/068 , G06F3/0688 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/52 , G11C29/765 , G11C29/82 , G11C7/1039 , G11C8/12 , G06F11/1068 , G06F2003/0694 , G06F2212/2022 , G06F2212/312 , G06F2212/7201 , G06F2212/7203 , G06F2212/7205 , G06F2212/7207 , G06F2212/7208 , G11C2211/5621 , G11C2211/5634 , G11C2211/5643 , G11C2216/18 , G11C29/00 , G11C29/34
摘要： A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.
摘要翻译：具有控制电路的闪存EEprom存储器芯片的系统用作诸如由磁盘驱动器提供的非易失性存储器。改进包括选择性多扇区擦除，其中Flash扇区的任何组合可以一起被擦除。所选组合中的选择扇区也可以在擦除操作期间被取消选择。另一个改进是使用替代细胞重新映射和替换有缺陷的细胞的能力。一旦检测到有缺陷的单元，就会自动执行重新映射。当Flash扇区的缺陷数量变大时，整个扇区被重新映射。另一个改进是使用写高速缓存来减少写入闪存EEPROM存储器的数量，从而最小化对器件进行过多写/擦循环的应力。

52. 发明授权

US5438573A Flash EEPROM array data and header file structure 失效
公开(公告)号：US5438573A
公开(公告)日：1995-08-01
申请号：US252052
申请日：1994-06-01
申请人： John S. Mangan , Robert D. Norman , Jeffrey Craig , Richard Albert , Anil Gupta , Jeffrey D. Stai , Karl M. J. Lofgren
发明人： John S. Mangan , Robert D. Norman , Jeffrey Craig , Richard Albert , Anil Gupta , Jeffrey D. Stai , Karl M. J. Lofgren
IPC分类号： G06F3/06 , G06F11/10 , G11C16/10 , G11C29/00
CPC分类号： G11C29/765 , G06F3/0601 , G11C16/102 , G06F11/1068 , G06F2003/0694
摘要： A file structure employed in a flash electrically erasable and programmable read only memory ("EEPROM") system and aspects of forming and using certain data fields within such a file structure. An array of rows and columns of EEPROM memory cells is divided into blocks of cells that are separately addressable for the purpose of erasing an entire block of cells at the same time. Each block contains several rows of cells with certain columns thereof storing a sector of data, typically 512 bytes of data, and other columns of cells within the same rows being used as spare cells to replace any defective sector data cells and store overhead (header) information about the block and the data sector. Such overhead information includes pointers to locations of any defective sector data cells within the block, whether the block has been mapped out in favor of another block, error correction codes for the sector data and the header information, and other similar types of information.

53. 发明授权

US5430859A Solid state memory system including plural memory chips and a serialized bus 失效
标题翻译：包括多个存储器芯片和串行总线的固态存储器系统
公开(公告)号：US5430859A
公开(公告)日：1995-07-04
申请号：US736733
申请日：1991-07-26
申请人： Robert D. Norman , Karl M. J. Lofgren , Jeffrey D. Stai , Anil Gupta , Sanjay Mehrotra
发明人： Robert D. Norman , Karl M. J. Lofgren , Jeffrey D. Stai , Anil Gupta , Sanjay Mehrotra
IPC分类号： G06F3/06 , G06F12/06 , G06F13/16 , G06F13/42 , G11C5/00 , G11C5/06 , G11C8/12 , G06F12/00 , G06F13/00 , G11C5/04 , G11C16/06
CPC分类号： G11C5/04 , G06F12/0676 , G06F13/1668 , G06F13/4243 , G06F3/0613 , G06F3/0659 , G06F3/0679 , G11C5/00 , G11C5/066 , G11C8/12 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A memory system includes an array of solid-state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit and assigned an array address. A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A particular multi-bit mount configuration is used to unconditionally select the device mounted thereon. A predefined address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory devices to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.
摘要翻译：存储器系统包括固态存储器件的阵列，其经由具有极少线的器件总线与控制器模块通信并处于控制器模块的控制之下。这形成了集成电路大容量存储系统，其被设想来替代大容量存储系统，例如计算机系统中的磁盘驱动器存储器。命令，地址和数据信息被串行化为组件字符串，并在控制器模块和存储器件阵列之间传输之前被多路复用。序列化信息伴随着一个控制信号，以帮助整理复用的组件。阵列中的每个存储器件都安装在多位并分配了一个阵列地址。通过在设备总线上广播的适当地址来选择存储设备，而不需要通常的专用选择信号。使用特定的多位安装配置来无条件地选择安装在其上的设备。通过设备总线广播的预定义地址将取消所有先前选择的存储设备。通过读取流技术增强读取性能，其中当当前块的数据被串行化并从存储器件移出到控制器模块时，控制器模块还设置下一个数据块的地址以开始寻址内存系统。

54. 发明授权

US5297148A Flash eeprom system 失效
标题翻译：闪光eeprom系统
公开(公告)号：US5297148A
公开(公告)日：1994-03-22
申请号：US963838
申请日：1992-10-20
申请人： Eliyahou Harari , Robert D. Norman , Sanjay Mehrotra
发明人： Eliyahou Harari , Robert D. Norman , Sanjay Mehrotra
IPC分类号： G11C16/02 , G06F3/06 , G06F11/10 , G06F12/00 , G06F12/02 , G06F12/08 , G06F12/12 , G06F12/16 , G11C5/00 , G11C8/02 , G11C8/12 , G11C11/56 , G11C16/06 , G11C16/10 , G11C16/16 , G11C16/34 , G11C17/00 , G11C29/00 , G11C29/04 , G11C29/26 , G11C29/34 , G11C29/52 , H01L21/82 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G06F11/00
CPC分类号： G11C29/26 , G06F12/0246 , G06F12/0802 , G06F12/0804 , G06F12/0866 , G06F12/0875 , G06F12/123 , G06F3/0601 , G06F3/0616 , G06F3/064 , G06F3/0652 , G06F3/0679 , G06F3/068 , G06F3/0688 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/52 , G11C29/765 , G11C29/82 , G11C7/1039 , G11C8/12 , G06F11/1068 , G06F2003/0694 , G06F2212/2022 , G06F2212/312 , G06F2212/7201 , G06F2212/7203 , G06F2212/7205 , G06F2212/7207 , G06F2212/7208 , G11C2211/5621 , G11C2211/5634 , G11C2211/5643 , G11C2216/18 , G11C29/00 , G11C29/34
摘要： A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.
摘要翻译：具有控制电路的闪存EEprom存储器芯片的系统用作诸如由磁盘驱动器提供的非易失性存储器。改进包括选择性多扇区擦除，其中Flash扇区的任何组合可以一起被擦除。所选组合中的选择扇区也可以在擦除操作期间被取消选择。另一个改进是使用替代细胞重新映射和替换有缺陷的细胞的能力。一旦检测到有缺陷的单元，就会自动执行重新映射。当Flash扇区的缺陷数量变大时，整个扇区被重新映射。另一个改进是使用写高速缓存来减少写入闪存EEPROM存储器的数量，从而最小化对器件进行过多写/擦循环的应力。

55. 发明授权

US4892518A Hemodialysis 失效
标题翻译：血液透析
公开(公告)号：US4892518A
公开(公告)日：1990-01-09
申请号：US128890
申请日：1987-12-04
申请人： James R. Cupp , Robert D. Norman , David L. Purdy , Orlando Maytin
发明人： James R. Cupp , Robert D. Norman , David L. Purdy , Orlando Maytin
IPC分类号： A61M1/16 , A61M39/02
CPC分类号： A61M39/0208 , A61M1/16 , A61M2039/0211 , Y10T137/7891
摘要： Hemodialysis port assembly including a port and a catheter assembly. The port includes an inlet septum subtended by an inlet plenum and an outlet septum subtended by an outlet plenum. The catheter assembly includes an inlet channel connected to the inlet plenum and an outlet channel connected to the outlet plenum. The port and catheter assembly are completely implanted in the chest of a patient with the port subcutaneous and the end of the catheter assembly remote from the port injected into the subclavian vein. The blood flow in this vein is in the direction away from the end of the catheter assembly. Near this remote end the catheter assembly or the inlet channel terminates in an inlet valve and the outlet channel terminates in an outlet valve. Each of these valves is essentially a flapper on which the blood is incident in a generally perpendicular direction so that its flow is substantially unimpeded. The outlet valve is spaced a small but effective distance from the inlet valve in the downstream direction of the flow to toxified blood through the outlet channel. In practice of this invention, the detoxified blood from an artificial kidney is supplied to the vein through a hypodermic needle which penetrates the inlet septum, the inlet plenum, the inlet channel and the inlet valve and toxified blood is supplied from the vein to the artificial kidney through the outlet valve, the outlet channel, the outlet plenum and an outlet needle which penetrates the outlet septum. The spacing of the outlet valve from the inlet valve suppresses short-circuit flow of detoxified blood from the inlet branch to the outlet branch.
摘要翻译：血液透析端口组件包括端口和导管组件。该端口包括入口隔室对面的入口隔膜和由出口增压室对着的出口隔膜。导管组件包括连接到入口气室的入口通道和连接到出口增压室的出口通道。端口和导管组件完全植入患者的胸部，皮下端口和导管组件的端部远离注入锁骨下静脉的口。该静脉中的血液流动方向远离导管组件的端部。在该远端附近，导管组件或入口通道终止于入口阀，并且出口通道终止于出口阀。这些阀中的每一个基本上是挡板，血液沿着大致垂直的方向入射，使得其流动基本上不受阻碍。出口阀在通向出口通道的有毒血液流向下游方向与入口阀隔开一段小而有效的距离。在本发明的实践中，来自人造肾的解毒血液通过渗透入口隔膜，入口通气室，入口通道和入口阀的皮下注射针供给到静脉，并且有毒血液从静脉供应到人造肾通过出口阀，出口通道，出口增压室和穿过出口隔膜的出口针头。出口阀与入口阀的间距抑制了从入口分支到出口分支的解毒血液的短路流动。

56. 发明授权

US07839685B2 Soft errors handling in EEPROM devices 有权
标题翻译： EEPROM器件中的软错误处理
公开(公告)号：US07839685B2
公开(公告)日：2010-11-23
申请号：US12572098
申请日：2009-10-01
申请人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
发明人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C29/028 , G06F11/1068 , G06F11/1072 , G06F2201/81 , G11C16/04 , G11C16/10 , G11C16/3431 , G11C29/50 , G11C29/50004 , G11C29/52 , G11C2029/5004 , G11C2029/5006
摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.
摘要翻译：正常使用固态存储器（如EEPROM或闪存EEPROM）时会发生软错误。存储器单元的编程阈值电压从原来的预期电平漂移导致软错误。在正常读取期间，最初不容易检测到该误差，直到累积漂移变得如此严重以致其发展为硬错误。数据可能会丢失，如果这些硬错误足够的可以在存储器中发出可用的纠错码。一种存储器件及其技术能够在整个使用存储器件的过程中检测这些漂移并且将每个存储器单元的阈值电压基本上保持在其预期的水平，从而抵抗将软错误发展成硬错误。

57. 发明授权

US07492660B2 Flash EEprom system 失效
公开(公告)号：US07492660B2
公开(公告)日：2009-02-17
申请号：US10414718
申请日：2003-04-15
申请人： Eliyahou Harari , Robert D. Norman , Sanjay Mehrotra
发明人： Eliyahou Harari , Robert D. Norman , Sanjay Mehrotra
IPC分类号： G11C11/34
CPC分类号： G11C29/26 , G06F3/0614 , G06F3/0616 , G06F3/064 , G06F3/0652 , G06F3/0679 , G06F11/1068 , G06F12/0246 , G06F12/0804 , G06F12/123 , G06F2212/1036 , G06F2212/312 , G06F2212/7201 , G06F2212/7203 , G06F2212/7205 , G11C7/1039 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/00 , G11C29/34 , G11C29/52 , G11C29/765 , G11C29/82 , G11C2211/5621 , G11C2211/5634 , G11C2211/5643
摘要： A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

58. 发明授权

US07171525B1 Method and system for arbitrating priority bids sent over serial links to a multi-port storage device 有权
标题翻译：仲裁通过串行链路发送到多端口存储设备的优先级投标的方法和系统
公开(公告)号：US07171525B1
公开(公告)日：2007-01-30
申请号：US10210839
申请日：2002-07-31
申请人： Robert D. Norman , Frank Sai-Keung Lee
发明人： Robert D. Norman , Frank Sai-Keung Lee
IPC分类号： G06F12/00
CPC分类号： G06F3/0659 , G06F3/0622 , G06F3/0689
摘要： A system including a multi-port storage device (e.g., a disk drive) and at least two users, each user coupled to a port of the storage device by a serial link. The storage device has an operational portion and an interface (including arbitration circuitry) between its ports and the operational portion. In response to a set of competing priority bids from the users, the arbitration circuitry grants one bid (including by sending an acknowledgement to the successful bidder) and preferably holds each non-granted competing bid without sending any notification to the unsuccessful bidder until the successful bidder sends a deselect signal. The system can be a RAID system including at least two disk drives and at least two controllers, where at least one drive is a multi-port device shared by at least two of the controllers. Preferably, each priority bid and deselect signal is a primitive code (e.g., an ordered sequence of a 10-bit control character and three 10-bit data characters in SATA format). Other aspects of the invention are multi-port storage devices and users for use in such a system.
摘要翻译：一种包括多端口存储设备（例如，磁盘驱动器）和至少两个用户的系统，每个用户通过串行链路耦合到存储设备的端口。存储装置在其端口和操作部分之间具有操作部分和接口（包括仲裁电路）。为响应来自用户的一组竞争优先权投标，仲裁电路授予一个投标（包括通过向中标者发送确认），并且优选地保持每个未被许可的竞争投标，而不向不成功的投标人发送任何通知，直到成功投标人发送取消信号。该系统可以是包括至少两个磁盘驱动器和至少两个控制器的RAID系统，其中至少一个驱动器是由至少两个控制器共享的多端口设备。优选地，每个优先权出价和取消选择信号是原始码（例如，10位控制字符的有序序列和SATA格式的三个10位数据字符）。本发明的其他方面是用于这种系统的多端口存储设备和用户。

59. 发明授权

US06826649B2 Apparatus and method for reducing programming cycles for multistate memory system 失效
标题翻译：用于减少多状态存储器系统的编程周期的装置和方法
公开(公告)号：US06826649B2
公开(公告)日：2004-11-30
申请号：US10755538
申请日：2004-01-12
申请人： Robert D. Norman
发明人： Robert D. Norman
IPC分类号： G06F1200
CPC分类号： G11C11/5628 , G11C11/56 , G11C11/5621 , G11C2211/5647 , Y10T74/18928
摘要： A method for reducing the number of programming states (threshold voltage levels) required to be traversed when programming a multistate memory cell with a given set of data. The invention first determines the average programming state (corresponding to an average threshold voltage level) for the set of data which is to be programmed into the memory cells. This is accomplished by counting the number of programming states which must be traversed in programming the cells with the data. If the majority of the data requires programming the memory cell(s) to the upper two programming states (in the case of a two bit per cell or four state system), then the data is inverted and stored in the memory in the inverted form. This reduces the amount of programming time, the number of programming states traversed, and the power consumed in programming the memory cell(s) with the data field.
摘要翻译：一种用于给具有给定的数据集的多组存储单元进行编程时减少编程状态（阈值电压电平）数量的方法。本发明首先确定要编程到存储器单元中的数据组的平均编程状态（对应于平均阈值电压电平）。这是通过对使用数据编程单元格中必须遍历的编程状态数进行计数来实现的。如果大多数数据需要将存储器单元编程到上两个编程状态（在每个单元或四个状态系统为2位的情况下），则数据被反转并以倒置形式存储在存储器中。这减少了编程时间的数量，遍历的编程状态的数量以及使用数据字段编程存储单元的功耗。

60. 发明授权

US06763480B2 Flash EEprom system 失效
公开(公告)号：US06763480B2
公开(公告)日：2004-07-13
申请号：US10330739
申请日：2002-12-26
申请人： Eliyahou Harari , Robert D. Norman , Sanjay Mehrotra
发明人： Eliyahou Harari , Robert D. Norman , Sanjay Mehrotra
IPC分类号： G06F1100
CPC分类号： G11C29/26 , G06F3/0601 , G06F3/0616 , G06F3/064 , G06F3/0652 , G06F3/0679 , G06F3/068 , G06F3/0688 , G06F11/1068 , G06F12/0246 , G06F12/0802 , G06F12/0804 , G06F12/0866 , G06F12/0875 , G06F12/123 , G06F2003/0694 , G06F2212/2022 , G06F2212/312 , G06F2212/7201 , G06F2212/7203 , G06F2212/7205 , G06F2212/7207 , G06F2212/7208 , G11C7/1039 , G11C8/12 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/00 , G11C29/34 , G11C29/52 , G11C29/765 , G11C29/82 , G11C2211/5621 , G11C2211/5634 , G11C2211/5643 , G11C2216/18
摘要： A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

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