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1. 发明授权

US5471478A Flash EEPROM array data and header file structure 失效
标题翻译：闪存EEPROM阵列数据和头文件结构
公开(公告)号：US5471478A
公开(公告)日：1995-11-28
申请号：US401942
申请日：1995-03-10
申请人： John S. Mangan , Robert D. Norman , Jeffrey Craig , Richard Albert , Anil Gupta , Jeffrey D. Stai , Karl M. J. Lofgren
发明人： John S. Mangan , Robert D. Norman , Jeffrey Craig , Richard Albert , Anil Gupta , Jeffrey D. Stai , Karl M. J. Lofgren
IPC分类号： G06F3/06 , G06F11/10 , G11C16/10 , G11C29/00 , G06F11/00
CPC分类号： G11C29/765 , G06F3/0601 , G11C16/102 , G06F11/1068 , G06F2003/0694
摘要： A file structure employed in a flash electrically erasable and programmable read only memory ("EEPROM") system and aspects of forming and using certain data fields within such a file structure. An array of rows and columns of EEPROM memory cells is divided into blocks of cells that are separately addressable for the purpose of erasing an entire block of cells at the same time. Each block contains several rows of cells with certain columns thereof storing a sector of data, typically 512 bytes of data, and other columns of cells within the same rows being used as spare cells to replace any defective sector data cells and store overhead (header) information about the block and the data sector. Such overhead information includes pointers to locations of any defective sector data cells within the block, whether the block has been mapped out in favor of another block, error correction codes for the sector data and the header information, and other similar types of information.
摘要翻译：在闪存电可擦除和可编程只读存储器（“EEPROM”）系统中采用的文件结构以及在这样的文件结构内形成和使用某些数据字段的方面。 EEPROM存储器单元的行和列的阵列被划分为可单独寻址以便同时擦除整个单元块的单元的单元块。每个块包含几行单元，其中某些列存储数据扇区（通常为512字节的数据），同一行内的其他单元格列用作备用单元以替代任何缺陷扇区数据单元并存储开销（标题）关于块和数据扇区的信息。这种开销信息包括指向块内的任何缺陷扇区数据单元的位置的指针，该块是否被映射到有利于另一个块，扇区数据的纠错码和头部信息以及其他类似类型的信息。

2. 发明授权

US5438573A Flash EEPROM array data and header file structure 失效
公开(公告)号：US5438573A
公开(公告)日：1995-08-01
申请号：US252052
申请日：1994-06-01
申请人： John S. Mangan , Robert D. Norman , Jeffrey Craig , Richard Albert , Anil Gupta , Jeffrey D. Stai , Karl M. J. Lofgren
发明人： John S. Mangan , Robert D. Norman , Jeffrey Craig , Richard Albert , Anil Gupta , Jeffrey D. Stai , Karl M. J. Lofgren
IPC分类号： G06F3/06 , G06F11/10 , G11C16/10 , G11C29/00
CPC分类号： G11C29/765 , G06F3/0601 , G11C16/102 , G06F11/1068 , G06F2003/0694
摘要： A file structure employed in a flash electrically erasable and programmable read only memory ("EEPROM") system and aspects of forming and using certain data fields within such a file structure. An array of rows and columns of EEPROM memory cells is divided into blocks of cells that are separately addressable for the purpose of erasing an entire block of cells at the same time. Each block contains several rows of cells with certain columns thereof storing a sector of data, typically 512 bytes of data, and other columns of cells within the same rows being used as spare cells to replace any defective sector data cells and store overhead (header) information about the block and the data sector. Such overhead information includes pointers to locations of any defective sector data cells within the block, whether the block has been mapped out in favor of another block, error correction codes for the sector data and the header information, and other similar types of information.

3. 发明授权

US5430859A Solid state memory system including plural memory chips and a serialized bus 失效
标题翻译：包括多个存储器芯片和串行总线的固态存储器系统
公开(公告)号：US5430859A
公开(公告)日：1995-07-04
申请号：US736733
申请日：1991-07-26
申请人： Robert D. Norman , Karl M. J. Lofgren , Jeffrey D. Stai , Anil Gupta , Sanjay Mehrotra
发明人： Robert D. Norman , Karl M. J. Lofgren , Jeffrey D. Stai , Anil Gupta , Sanjay Mehrotra
IPC分类号： G06F3/06 , G06F12/06 , G06F13/16 , G06F13/42 , G11C5/00 , G11C5/06 , G11C8/12 , G06F12/00 , G06F13/00 , G11C5/04 , G11C16/06
CPC分类号： G11C5/04 , G06F12/0676 , G06F13/1668 , G06F13/4243 , G06F3/0613 , G06F3/0659 , G06F3/0679 , G11C5/00 , G11C5/066 , G11C8/12 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A memory system includes an array of solid-state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit and assigned an array address. A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A particular multi-bit mount configuration is used to unconditionally select the device mounted thereon. A predefined address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory devices to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.
摘要翻译：存储器系统包括固态存储器件的阵列，其经由具有极少线的器件总线与控制器模块通信并处于控制器模块的控制之下。这形成了集成电路大容量存储系统，其被设想来替代大容量存储系统，例如计算机系统中的磁盘驱动器存储器。命令，地址和数据信息被串行化为组件字符串，并在控制器模块和存储器件阵列之间传输之前被多路复用。序列化信息伴随着一个控制信号，以帮助整理复用的组件。阵列中的每个存储器件都安装在多位并分配了一个阵列地址。通过在设备总线上广播的适当地址来选择存储设备，而不需要通常的专用选择信号。使用特定的多位安装配置来无条件地选择安装在其上的设备。通过设备总线广播的预定义地址将取消所有先前选择的存储设备。通过读取流技术增强读取性能，其中当当前块的数据被串行化并从存储器件移出到控制器模块时，控制器模块还设置下一个数据块的地址以开始寻址内存系统。

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