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51. 发明申请

US20110215409A1 STRUCTURE AND METHOD TO MAKE REPLACEMENT METAL GATE AND CONTACT METAL 有权
标题翻译：结构和方法替代金属门和接触金属
公开(公告)号：US20110215409A1
公开(公告)日：2011-09-08
申请号：US12717398
申请日：2010-03-04
申请人： Zhengwen Li , Michael P. Chudzik , Unoh Kwon , Filippos Papadatos , Andrew H. Simon , Keith Kwong Hon Wong
发明人： Zhengwen Li , Michael P. Chudzik , Unoh Kwon , Filippos Papadatos , Andrew H. Simon , Keith Kwong Hon Wong
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L23/485 , H01L21/28088 , H01L21/28202 , H01L21/76283 , H01L21/76877 , H01L21/823842 , H01L21/823871 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： An electrical device is provided with a p-type semiconductor device having a first gate structure that includes a gate dielectric on top of a semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.
摘要翻译：电气装置设置有具有第一栅极结构的p型半导体器件，其包括在半导体衬底的顶部上的栅极电介质，p型功函数金属层，由钛和铝构成的金属层，以及金属填充铝。 n型半导体器件也存在于半导体衬底上，该半导体衬底包括第二栅极结构，其包括栅极电介质，由钛和铝构成的金属层以及由铝组成的金属填充物。层间电介质存在于半导体衬底上。层间电介质包括到p型和n型半导体器件的源区和漏区的互连。互连由钛和铝构成的金属层和由铝组成的金属填充物构成。本公开还提供了形成上述结构的方法。

52. 发明授权

US07838908B2 Semiconductor device having dual metal gates and method of manufacture 有权
标题翻译：具有双金属栅极的半导体器件及其制造方法
公开(公告)号：US07838908B2
公开(公告)日：2010-11-23
申请号：US12359520
申请日：2009-01-26
申请人： Unoh Kwon , Siddarth A. Krishnan , Takashi Ando , Michael P. Chudzik , Martin M. Frank , William K. Henson , Rashmi Jha , Yue Liang , Vijay Narayanan , Ravikumar Ramachandran , Keith Kwong Hon Wong
发明人： Unoh Kwon , Siddarth A. Krishnan , Takashi Ando , Michael P. Chudzik , Martin M. Frank , William K. Henson , Rashmi Jha , Yue Liang , Vijay Narayanan , Ravikumar Ramachandran , Keith Kwong Hon Wong
IPC分类号： H01L27/10
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/4966 , H01L29/517
摘要： A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.
摘要翻译：半导体器件包括：半导体衬底; 形成在衬底上的PFET，PFET包括设置在衬底上的SiGe层，设置在SiGe层上的高K电介质层，设置在高k电介质层上的第一金属层，设置在第一中间层上的第一中间层第一金属层，设置在第一中间层上的第二金属层，设置在第二金属层上的第二中间层和设置在第二中间层上的第三金属层; 形成在衬底上的NFET，NFET包括高k电介质层，高k电介质层设置在衬底上，第二中间层，第二中间层设置在高k电介质层上，并且第三金属层，第三金属层设置在第二中间层上。或者，省略第一金属层。制造该器件的方法包括提供SiO 2和α-硅层或dBARC层。

53. 发明授权

US09236314B2 High-K/metal gate stack using capping layer methods, IC and related transistors 有权
标题翻译：高K /金属栅极堆叠采用封盖层法，IC及相关晶体管
公开(公告)号：US09236314B2
公开(公告)日：2016-01-12
申请号：US13433659
申请日：2012-03-29
申请人： Michael P. Chudzik , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
发明人： Michael P. Chudzik , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
IPC分类号： H01L21/8238 , H01L29/49 , H01L29/51
CPC分类号： H01L21/823857 , H01L21/823842 , H01L29/4966 , H01L29/4975 , H01L29/517
摘要： Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.
摘要翻译：公开了使用具有高k /金属栅极叠层的封盖层的IC和相关晶体管。在一个实施例中，IC包括具有包括第一金属，第二金属和第一介电层的栅电极的第一类型晶体管，第一介电层包括氧; 通过隔离区与第一型晶体管分离的第二类型晶体管，第二类型晶体管具有包括具有适合于第二类型晶体管和第一介电层的功函数的第二金属的栅电极; 并且其中所述第一类型晶体管的栅极包括在所述第一金属和所述第二金属之间的稀土金属，并且所述第二类型晶体管的栅电极包括由所述稀土金属的氧化物制成的第二电介质层。

54. 发明授权

US09093495B2 Method and structure to reduce FET threshold voltage shift due to oxygen diffusion 有权
标题翻译：减少由于氧扩散引起的FET阈值电压偏移的方法和结构
公开(公告)号：US09093495B2
公开(公告)日：2015-07-28
申请号：US13342674
申请日：2012-01-03
申请人： Christopher Vincent Baiocco , Michael P. Chudzik , Deleep R. Nair , Jay M. Shah
发明人： Christopher Vincent Baiocco , Michael P. Chudzik , Deleep R. Nair , Jay M. Shah
IPC分类号： H01L21/02 , H01L21/762 , H01L29/66 , H01L29/78
CPC分类号： H01L21/76224 , H01L21/762 , H01L29/0649 , H01L29/66537 , H01L29/783
摘要： Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials.
摘要翻译：嵌入隔离结构中的氧气清除材料提供了从氧污染中改进的高介电常数（Hi-K）材料的保护，同时避免了包括这种Hi-K材料在内的晶体管的功函数和切换阈值偏移的变化。

55. 发明申请

US20130292778A1 Techniques for the Fabrication of Thick Gate Dielectric 失效
标题翻译：厚栅电介质制造技术
公开(公告)号：US20130292778A1
公开(公告)日：2013-11-07
申请号：US13464966
申请日：2012-05-05
申请人： Eduard Albert Cartier , Michael P. Chudzik , Andreas Kerber , Siddarth Krishnan , Naim Moumen
发明人： Eduard Albert Cartier , Michael P. Chudzik , Andreas Kerber , Siddarth Krishnan , Naim Moumen
IPC分类号： H01L27/092 , H01L21/76
CPC分类号： H01L21/823857 , H01L21/76224
摘要： A method for fabricating a CMOS device includes the following steps. A wafer is provided. STI is used to form at least one active area in the wafer. A silicon oxide layer is deposited onto the wafer covering the active area. A first high-k material is deposited onto the silicon oxide layer. Portions of the silicon oxide layer and the first high-k material are selectively removed, such that the silicon oxide layer and the first high-k material remain over one or more first regions of the active area and are removed from over one or more second regions of the active area. A second high-k material is deposited onto the first high-k material over the one or more first regions of the active area and onto a surface of the wafer in the one or more second regions of the active area. A CMOS device is also provided.
摘要翻译：一种制造CMOS器件的方法包括以下步骤。提供晶片。 STI用于在晶片中形成至少一个有效区域。氧化硅层沉积在覆盖有源区的晶片上。第一高k材料沉积在氧化硅层上。选择性地去除氧化硅层和第一高k材料的部分，使得氧化硅层和第一高k材料保留在有源区的一个或多个第一区上，并从一个或多个第二个活跃区域。在有源区域的一个或多个第一区域上并且在有源区域的一个或多个第二区域中的晶片的表面上沉积第二高k材料到第一高k材料上。还提供了CMOS器件。

56. 发明申请

US20130062677A1 SELF-ALIGNED BOTTOM PLATE FOR METAL HIGH-K DIELECTRIC METAL INSULATOR METAL (MIM) EMBEDDED DYNAMIC RANDOM ACCESS MEMORY 有权
标题翻译：用于金属高K介电金属绝缘体金属（MIM）嵌入式动态随机存取存储器的自对准底板
公开(公告)号：US20130062677A1
公开(公告)日：2013-03-14
申请号：US13228767
申请日：2011-09-09
申请人： Zhengwen Li , Damon B. Farmer , Michael P. Chudzik , Keith Kwong Hon Wong , Jian Yu , Zhen Zhang , Chengwen Pei
发明人： Zhengwen Li , Damon B. Farmer , Michael P. Chudzik , Keith Kwong Hon Wong , Jian Yu , Zhen Zhang , Chengwen Pei
IPC分类号： H01L21/20 , H01L27/06
CPC分类号： H01L27/10829 , H01L21/84 , H01L27/10861 , H01L27/1203 , H01L28/91 , H01L29/945
摘要： A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.
摘要翻译：提供一种存储器件和形成存储器件的方法，其包括具有金属半导体合金的下电极的电容器。在一个实施例中，存储器件包括存在于半导体衬底中的沟槽，其包括在掩埋介电层顶部上的绝缘（SOI）半导体层，其中所述掩埋介电层位于基底半导体层的顶部。电容器存在于沟槽中，其中电容器包括金属半导体合金的下电极，其具有与基底半导体层的上表面自对准的上边缘，高k电介质节点层和上层金属电极。存储器件还包括与电容器电连通的传输晶体管。

57. 发明授权

US08354309B2 Method of providing threshold voltage adjustment through gate dielectric stack modification 有权
标题翻译：通过栅介质叠层修改提供阈值电压调整的方法
公开(公告)号：US08354309B2
公开(公告)日：2013-01-15
申请号：US13347014
申请日：2012-01-10
申请人： Brian J. Greene , Michael P. Chudzik , Shu-Jen Han , William K. Henson , Yue Liang , Edward P. Maciejewski , Myung-Hee Na , Edward J. Nowak , Xiaojun Yu
发明人： Brian J. Greene , Michael P. Chudzik , Shu-Jen Han , William K. Henson , Yue Liang , Edward P. Maciejewski , Myung-Hee Na , Edward J. Nowak , Xiaojun Yu
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/823462 , H01L21/28229 , H01L21/84 , H01L27/1203
摘要： Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.
摘要翻译：在掺杂半导体阱上形成多种类型的栅叠层。在掺杂半导体阱上形成高介电常数（高k）栅极电介质。在一个器件区域中形成金属栅极层，而在其他器件区域中暴露高k栅极电介质。在其他器件区域中形成具有不同厚度的阈值电压调节氧化物层。然后在阈值电压调整氧化物层上形成导电栅极材料层。一种类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质。其他类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质和具有不同厚度的第一阈值电压调整氧化物部分。具有不同阈值电压的场效应晶体管通过采用具有相同掺杂剂浓度的不同栅极电介质叠层和掺杂半导体阱来提供。

58. 发明授权

US08232606B2 High-K dielectric and metal gate stack with minimal overlap with isolation region 有权
标题翻译：高K电介质和金属栅极堆叠与隔离区域重叠
公开(公告)号：US08232606B2
公开(公告)日：2012-07-31
申请号：US13150378
申请日：2011-06-01
申请人： Michael P. Chudzik , William K. Henson , Renee T. Mo , Jeffrey Sleight
发明人： Michael P. Chudzik , William K. Henson , Renee T. Mo , Jeffrey Sleight
IPC分类号： H01L29/76
CPC分类号： H01L29/517 , H01L21/28123 , H01L21/823842 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.
摘要翻译：公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。

59. 发明授权

US08105892B2 Thermal dual gate oxide device integration 有权
标题翻译：热双栅氧化器器件集成
公开(公告)号：US08105892B2
公开(公告)日：2012-01-31
申请号：US12542768
申请日：2009-08-18
申请人： Byeong Y. Kim , Michael P. Chudzik
发明人： Byeong Y. Kim , Michael P. Chudzik
IPC分类号： H01L21/8238
CPC分类号： H01L27/0922 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/517 , H01L29/7833
摘要： A method is provided that includes providing a semiconductor substrate including at least a thin gate oxide pFET device region and a thick gate oxide pFET device region and forming a thin gate oxide pFET within the thin gate oxide pFET device region and a thick gate oxide pFET within the thick gate oxide pFET device region. The thin gate oxide pFET that is formed includes a layer of SiGe on an upper surface of the thin gate oxide pFET device region, a high k gate dielectric located on an upper surface of the layer of SiGe, a pFET threshold voltage adjusting layer located on an upper surface of the high k gate dielectric, and a gate conductor material atop the pFET threshold voltage adjusting layer. The thick gate oxide pFET that is formed includes a thermal oxide located on an upper surface of the thick gate oxide pFET device region, a silicon layer located on an upper surface of the thermal oxide and a gate conductor material located atop the silicon layer.
摘要翻译：提供了一种方法，其包括提供至少包括薄栅极氧化物pFET器件区域和厚栅极氧化物pFET器件区域的半导体衬底，并在薄栅极氧化物pFET器件区域内形成薄栅极氧化物pFET，并在其内形成厚栅极氧化物pFET 厚栅氧化物pFET器件区域。所形成的薄栅氧化物pFET包括在薄栅极氧化物pFET器件区域的上表面上的SiGe层，位于SiGe层的上表面上的高k栅极电介质，pFET阈值电压调节层，位于高k栅极电介质的上表面，以及pFET阈值电压调节层顶部的栅极导体材料。形成的厚栅极氧化物pFET包括位于厚栅极氧化物pFET器件区域的上表面上的热氧化物，位于热氧化物的上表面上的硅层和位于硅层顶部的栅极导体材料。

60. 发明授权

US08021939B2 High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods 失效
标题翻译：高k介质和金属栅极堆叠与隔离区域和相关方法的重叠最小
公开(公告)号：US08021939B2
公开(公告)日：2011-09-20
申请号：US11954775
申请日：2007-12-12
申请人： Michael P. Chudzik , William K. Henson , Renee T. Mo , Jeffrey W Sleight
发明人： Michael P. Chudzik , William K. Henson , Renee T. Mo , Jeffrey W Sleight
IPC分类号： H01L21/8238
CPC分类号： H01L29/517 , H01L21/28123 , H01L21/823842 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.
摘要翻译：公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。

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