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    • 55. 发明授权
    • Self-aligned source and body contact structure for high performance DMOS
transistors and method of fabricating same
    • 用于高性能DMOS晶体管的自对准源极接触结构及其制造方法
    • US5684319A
    • 1997-11-04
    • US518785
    • 1995-08-24
    • Francois Hebert
    • Francois Hebert
    • H01L21/336H01L29/78
    • H01L29/66712H01L29/7802
    • A DMOS device structure, and method of manufacturing the same features a self-aligned source and body contact structure which requires no additional masks. Polysilicon spacers are used to form the source region at the periphery of the gate polysilicon. The preferred method of manufacturing uses five masks to produce a discrete DMOS semiconductor chip. An N- epitaxial layer is grown on an N+ substrate. Thick field oxide is grown. A first mask is used to etch an active region. Thin gate oxide is grown. Doped polysilicon is then deposited. A second mask is used to etch the polysilicon, thereby forming the gates. Insulating oxide is grown. A blanket P body implantation is performed. A thermal drive-in step laterally and vertically diffuses the implanted P type impurity throughout body regions. The insulating oxide is etched. A polysilicon layer is deposited and doped. A dry etch leaves polyslicon spacers along the edges of the gates. A P+ body contact implantation is performed, thereby forming body contact regions. A final annealing step causes vertical and lateral out-diffusion of the N type dopant from the N+ spacers down into substrate to form source N+ regions which partially underlie the gate polysilicon. A third mask is used to etch a gate contact area on a segment of the polysilicon above the field oxide. Metal is deposited, and a fourth photoresist mask delineates a gate pad region and a source pad region which also extends over the source contacts. A passivation layer is deposited and etched in the source and gate pad regions using a fifth mask. In another embodiment, a trench DMOS transistor is fabricated using an additional mask to guide a dry etch to "dig" the trenches.
    • DMOS器件结构及其制造方法具有不需要附加掩模的自对准源和体接触结构。 多晶硅间隔物用于在栅极多晶硅的外围形成源区。 优选的制造方法使用五个掩模来生产离散的DMOS半导体芯片。 在N +衬底上生长N-外延层。 生长厚场氧化物。 第一掩模用于蚀刻活性区域。 生长薄栅氧化物。 然后沉积掺杂的多晶硅。 使用第二掩模来蚀刻多晶硅,从而形成栅极。 生长绝缘氧化物。 进行毯子P体植入。 热驱动步骤横向和垂直地将注入的P型杂质扩散到整个体区域。 绝缘氧化物被蚀刻。 沉积并掺杂多晶硅层。 干蚀刻沿着门的边缘留下多晶硅间隔物。 进行P +体接触注入,从而形成身体接触区域。 最后的退火步骤使得N型掺杂剂从N +间隔物垂直和侧向向外扩散到衬底中以形成部分位于栅极多晶硅下面的源极N +区域。 第三掩模用于蚀刻场氧化物上方的多晶硅段上的栅极接触面积。 金属被沉积,并且第四光致抗蚀剂掩模描绘了栅极焊盘区域和也在源极触点上延伸的源焊盘区域。 使用第五掩模在源极和栅极焊盘区域中沉积和蚀刻钝化层。 在另一个实施例中,使用附加掩模制造沟槽DMOS晶体管,以引导干式蚀刻以“挖掘”沟槽。
    • 56. 发明授权
    • Planar selective field oxide isolation process using SEG/ELO
    • 使用SEG / ELO的平面选择场氧化物隔离工艺
    • US5681776A
    • 1997-10-28
    • US708359
    • 1996-09-04
    • Francois HebertDatong ChenRashid Bashir
    • Francois HebertDatong ChenRashid Bashir
    • H01L21/762H01L21/76
    • H01L21/76227
    • An isolation method for separating active regions on a semiconductor substrate is disclosed. Portions of the substrate not corresponding to the active regions are etched to a predetermined depth. After some oxide, nitride and dielectric deposition steps, a photoresist is patterned on the dielectric material such that the photoresist completely covers the active regions of the substrate and overlaps into the portions of the substrate that are eventually to represent field oxide regions. Any portion of the dielectric, nitride oxide layers that are not covered by the photoresist are removed and a combined step of selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) is performed. The exposed silicon is then oxidizing and the dielectric, nitride and oxide layers are removed from the active regions of the substrate. The semiconductor device is then ready for subsequent processing.
    • 公开了一种用于分离半导体衬底上的有源区的隔离方法。 将不对应于活性区域的基板的部分蚀刻到预定深度。 在一些氧化物,氮化物和电介质沉积步骤之后,光致抗蚀剂被图案化在电介质材料上,使得光致抗蚀剂完全覆盖衬底的有源区并且重叠到最终表示场氧化物区域的衬底部分中。 去除未被光致抗蚀剂覆盖的电介质氮氧化物层的任何部分,并执行选择性外延生长(SEG)和外延横向过度生长(ELO)的组合步骤。 然后将暴露的硅氧化,并从衬底的有源区域去除电介质,氮化物和氧化物层。 然后半导体器件准备好用于后续处理。
    • 57. 发明授权
    • Self-aligned polysilicon base contact in a bipolar junction transistor
    • 双极结晶体管中的自对准多晶硅基极接触
    • US5581114A
    • 1996-12-03
    • US482164
    • 1995-06-07
    • Rashid BashirFrancois Hebert
    • Rashid BashirFrancois Hebert
    • H01L21/8249H01L27/082H01L27/088H01L27/102
    • H01L21/8249Y10S148/01Y10S257/90
    • A bipolar transistor in accordance with the invention includes a polysilicon base contact (607A) which is self-aligned with a polysilicon emitter (303). The polysilicon emitter is formed from a first polysilicon layer overlying an intrinsic base region (502) in a substrate (201). An extrinsic base (504) in the substrate is in contact with the intrinsic base and is self-aligned with a spacer (406) adjacent to the emitter. The polysilicon base contact is formed from a second polysilicon layer (407) in contact with the extrinsic base and overlying the emitter. A second sidewall spacer (508) is formed on the second polysilicon layer on step caused by the emitter. A protective layer (509, 510) formed on portions of the second polysilicon layer protects the base contact when the second spacer and the underlying portion of the second polysilicon layer are removed. The separation between the polysilicon base contact and the polysilicon emitter is controlled by the thickness the second polysilicon layer and the thickness of the spacers so that the base contact is self-aligned with a fixed separation from the emitter. Layer and spacer thicknesses define separation between the emitter and the base contact and permit sub-micron active regions in the substrate.
    • 根据本发明的双极晶体管包括与多晶硅发射器(303)自对准的多晶硅基极接触(607A)。 多晶硅发射体由覆盖衬底(201)中的本征基极区(502)的第一多晶硅层形成。 衬底中的外在基极(504)与本征基极接触并且与邻近发射极的间隔物(406)自对准。 多晶硅基极接触由与外部基极接触并覆盖发射极的第二多晶硅层(407)形成。 第二侧壁间隔物(508)由发射极引起的步骤形成在第二多晶硅层上。 形成在第二多晶硅层的部分上的保护层(509,510)在第二间隔物和第二多晶硅层的下面部分被去除时保护基极接触。 多晶硅基底触点和多晶硅发射极之间的间隔由第二多晶硅层的厚度和间隔物的厚度来控制,使得基极接触件与发射极的固定分离自对准。 层和间隔物厚度限定了发射极和基极接触之间的间隔,并允许衬底中的亚微米有源区。
    • 58. 发明授权
    • Process for making self-aligned polysilicon base contact in a bipolar
junction transistor
    • 在双极结型晶体管中进行自对准多晶硅基极接触的工艺
    • US5451532A
    • 1995-09-19
    • US273530
    • 1994-07-11
    • Rashid BashirFrancois Hebert
    • Rashid BashirFrancois Hebert
    • H01L21/8249H01L21/8222
    • H01L21/8249Y10S148/01Y10S257/90
    • A bipolar transistor in accordance with the invention includes a polysilicon base contact (607A) which is self-aligned with a polysilicon emitter (303). The polysilicon emitter is formed from a first polysilicon layer overlying an intrinsic base region (502) in a substrate (201). An extrinsic base (504) in the substrate is in contact with the intrinsic base and is self-aligned with a spacer (406) adjacent to the emitter. The polysilicon base contact is formed from a second polysilicon layer (407) in contact with the extrinsic base and overlying the emitter. A second sidewall spacer (508) is formed on the second polysilicon layer on step caused by the emitter. A protective layer (509, 510) formed on portions of the second polysilicon layer protects the base contact when the second spacer and the underlying portion of the second polysilicon layer are removed. The separation between the polysilicon base contact and the polysilicon emitter is controlled by the thickness the second polysilicon layer and the thickness of the spacers so that the base contact is self-aligned with a fixed separation from the emitter. Layer and spacer thicknesses define separation between the emitter and the base contact and permit sub-micron active regions in the substrate.
    • 根据本发明的双极晶体管包括与多晶硅发射器(303)自对准的多晶硅基极接触(607A)。 多晶硅发射体由覆盖衬底(201)中的本征基极区(502)的第一多晶硅层形成。 衬底中的外在基极(504)与本征基极接触并且与邻近发射极的间隔物(406)自对准。 多晶硅基极接触由与外部基极接触并覆盖发射极的第二多晶硅层(407)形成。 第二侧壁间隔物(508)由发射极引起的步骤形成在第二多晶硅层上。 形成在第二多晶硅层的部分上的保护层(509,510)在去除第二间隔物和第二多晶硅层的下面部分时保护基极接触。 多晶硅基底触点和多晶硅发射极之间的间隔由第二多晶硅层的厚度和间隔物的厚度来控制,使得基极接触件与发射极的固定分离自对准。 层和间隔物厚度限定了发射极和基极接触之间的间隔,并允许衬底中的亚微米有源区。