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51. 发明授权

US06677210B1 High voltage transistors with graded extension 有权
标题翻译：具有分级延伸的高压晶体管
公开(公告)号：US06677210B1
公开(公告)日：2004-01-13
申请号：US10087881
申请日：2002-02-28
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L21336
CPC分类号： H01L29/66659 , H01L29/0619 , H01L29/0692 , H01L29/0847 , H01L29/0878 , H01L29/1033 , H01L29/1083 , H01L29/1095 , H01L29/4238 , H01L29/66689 , H01L29/7816 , H01L29/7835
摘要： High voltage transistors with high breakdown voltages are provided. These high voltage transistors are formed with graded drain extension regions. The concentration of charge carriers increases farther away from the gate across each drain extension region, causing severe electric fields to be moved away from the gate. Methods and structures of the present invention may be used to increase a transistor's breakdown voltage to the theoretical limit of the device. High voltage transistors with graded extension regions may be p-channel or n-channel MOSFETs.
摘要翻译：提供具有高击穿电压的高压晶体管。这些高压晶体管形成有渐变漏极延伸区域。电荷载流子的浓度越过每个漏极延伸区域越远离栅极，导致严重的电场移动离开栅极。本发明的方法和结构可用于将晶体管的击穿电压增加到器件的理论极限。具有分级扩展区域的高压晶体管可以是p沟道或n沟道MOSFET。

52. 发明授权

US06506648B1 Method of fabricating a high power RF field effect transistor with reduced hot electron injection and resulting structure 有权
标题翻译：制造具有减少的热电子注入和所得结构的高功率RF场效应晶体管的方法
公开(公告)号：US06506648B1
公开(公告)日：2003-01-14
申请号：US09145818
申请日：1998-09-02
申请人： Francois Hebert , Szehim Daniel Ng
发明人： Francois Hebert , Szehim Daniel Ng
IPC分类号： H01L21336
CPC分类号： H01L29/66659 , H01L21/743 , H01L29/1087 , H01L29/4175 , H01L29/41758 , H01L29/41775 , H01L29/42368 , H01L29/7835
摘要： Methods of fabricating a high power RF lateral diffused MOS transistor (LDMOS) having increased reliability includes fabricating an N-drift region for the drain prior to fabrication of the gate contact and other process steps in fabricating the transistor. The resulting device has reduced adverse affects from hot carrier injection including reduced threshold voltage shift over time and reduced maximum current reduction over time. Linearity of device is maximized along with increased reliability while channel length is reduced.
摘要翻译：制造具有增加的可靠性的高功率RF侧向扩散MOS晶体管（LDMOS）的方法包括在制造栅极接触之前制造用于漏极的N漂移区域以及制造晶体管的其它工艺步骤。所得到的器件减少了热载流子注入的不利影响，包括随时间降低的阈值电压偏移和随时间减小的最大电流减小。器件的线性度随着可靠性的增加而增加，而沟道长度减小。

53. 发明授权

US5912490A MOSFET having buried shield plate for reduced gate/drain capacitance 失效
公开(公告)号：US5912490A
公开(公告)日：1999-06-15
申请号：US905513
申请日：1997-08-04
申请人： Francois Hebert , Daniel Ng
发明人： Francois Hebert , Daniel Ng
IPC分类号： H01L23/552 , H01L27/088 , H01L29/06 , H01L29/40 , H01L29/78 , H01L29/72
CPC分类号： H01L29/7816 , H01L23/552 , H01L23/585 , H01L27/088 , H01L29/402 , H01L29/7801 , H01L29/7835 , H01L2924/0002 , H01L2924/3011
摘要： Gate to drain capacitance in a lateral DMOS and vertical DMOS field effect transistor is minimized by providing a conductive shield plate under the gate and between the gate and the drain of the transistor. In operation, the shield plate is preferably connected to a DC voltage potential and coupled to AC ground for RF power applications. The shield plate is readily fabricated in a conventional polysilicon gate process by adding one additional polysilicon deposition (or other suitable material), one additional mask, and one additional etch step. The shield plate can include a raised portion which provides lateral capacitive isolation between the gate and the drain. Alternatively, a shield contact can be provided above the shield plate and between the gate and drain to provide lateral isolation.

54. 发明授权

US5827762A Method for forming buried interconnect structue having stability at high temperatures 失效
标题翻译：用于形成在高温下具有稳定性的掩埋互连结构的方法
公开(公告)号：US5827762A
公开(公告)日：1998-10-27
申请号：US850603
申请日：1997-05-02
申请人： Rashid Bashir , Francois Hebert , Datong Chen
发明人： Rashid Bashir , Francois Hebert , Datong Chen
IPC分类号： H01L21/768 , H01L21/8238
CPC分类号： H01L21/76886
摘要： A buried interconnect structure which is stable at the high temperatures involved in BiCMOS, bipolar, and CMOS transistor process flows, and a method of making the same. The interconnect structure is fully insulated and can be used to form stable, doped structures suitable for use as electrodes and gate structures in a CMOS process, or to form low resistance contacts to N or P-type silicon as part of a bipolar process. Because the interconnect structure is buried and fully insulated from surrounding structures, it may be used to form complex, multi-level devices having a minimized geometry and increased circuit density.
摘要翻译：在BiCMOS，双极和CMOS晶体管工艺流程中涉及的高温下稳定的埋入式互连结构及其制造方法。互连结构是完全绝缘的，并且可以用于形成适合用作CMOS工艺中的电极和栅极结构的稳定的掺杂结构，或者作为双极工艺的一部分形成作为N型或P型硅的低电阻接触。因为互连结构被掩埋并且与周围结构完全绝缘，所以它可用于形成具有最小几何形状和增加的电路密度的复杂的多电平器件。

55. 发明授权

US5684319A Self-aligned source and body contact structure for high performance DMOS transistors and method of fabricating same 失效
标题翻译：用于高性能DMOS晶体管的自对准源极接触结构及其制造方法
公开(公告)号：US5684319A
公开(公告)日：1997-11-04
申请号：US518785
申请日：1995-08-24
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66712 , H01L29/7802
摘要： A DMOS device structure, and method of manufacturing the same features a self-aligned source and body contact structure which requires no additional masks. Polysilicon spacers are used to form the source region at the periphery of the gate polysilicon. The preferred method of manufacturing uses five masks to produce a discrete DMOS semiconductor chip. An N- epitaxial layer is grown on an N+ substrate. Thick field oxide is grown. A first mask is used to etch an active region. Thin gate oxide is grown. Doped polysilicon is then deposited. A second mask is used to etch the polysilicon, thereby forming the gates. Insulating oxide is grown. A blanket P body implantation is performed. A thermal drive-in step laterally and vertically diffuses the implanted P type impurity throughout body regions. The insulating oxide is etched. A polysilicon layer is deposited and doped. A dry etch leaves polyslicon spacers along the edges of the gates. A P+ body contact implantation is performed, thereby forming body contact regions. A final annealing step causes vertical and lateral out-diffusion of the N type dopant from the N+ spacers down into substrate to form source N+ regions which partially underlie the gate polysilicon. A third mask is used to etch a gate contact area on a segment of the polysilicon above the field oxide. Metal is deposited, and a fourth photoresist mask delineates a gate pad region and a source pad region which also extends over the source contacts. A passivation layer is deposited and etched in the source and gate pad regions using a fifth mask. In another embodiment, a trench DMOS transistor is fabricated using an additional mask to guide a dry etch to "dig" the trenches.
摘要翻译： DMOS器件结构及其制造方法具有不需要附加掩模的自对准源和体接触结构。多晶硅间隔物用于在栅极多晶硅的外围形成源区。优选的制造方法使用五个掩模来生产离散的DMOS半导体芯片。在N +衬底上生长N-外延层。生长厚场氧化物。第一掩模用于蚀刻活性区域。生长薄栅氧化物。然后沉积掺杂的多晶硅。使用第二掩模来蚀刻多晶硅，从而形成栅极。生长绝缘氧化物。进行毯子P体植入。热驱动步骤横向和垂直地将注入的P型杂质扩散到整个体区域。绝缘氧化物被蚀刻。沉积并掺杂多晶硅层。干蚀刻沿着门的边缘留下多晶硅间隔物。进行P +体接触注入，从而形成身体接触区域。最后的退火步骤使得N型掺杂剂从N +间隔物垂直和侧向向外扩散到衬底中以形成部分位于栅极多晶硅下面的源极N +区域。第三掩模用于蚀刻场氧化物上方的多晶硅段上的栅极接触面积。金属被沉积，并且第四光致抗蚀剂掩模描绘了栅极焊盘区域和也在源极触点上延伸的源焊盘区域。使用第五掩模在源极和栅极焊盘区域中沉积和蚀刻钝化层。在另一个实施例中，使用附加掩模制造沟槽DMOS晶体管，以引导干式蚀刻以“挖掘”沟槽。

56. 发明授权

US5681776A Planar selective field oxide isolation process using SEG/ELO 失效
标题翻译：使用SEG / ELO的平面选择场氧化物隔离工艺
公开(公告)号：US5681776A
公开(公告)日：1997-10-28
申请号：US708359
申请日：1996-09-04
申请人： Francois Hebert , Datong Chen , Rashid Bashir
发明人： Francois Hebert , Datong Chen , Rashid Bashir
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76227
摘要： An isolation method for separating active regions on a semiconductor substrate is disclosed. Portions of the substrate not corresponding to the active regions are etched to a predetermined depth. After some oxide, nitride and dielectric deposition steps, a photoresist is patterned on the dielectric material such that the photoresist completely covers the active regions of the substrate and overlaps into the portions of the substrate that are eventually to represent field oxide regions. Any portion of the dielectric, nitride oxide layers that are not covered by the photoresist are removed and a combined step of selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) is performed. The exposed silicon is then oxidizing and the dielectric, nitride and oxide layers are removed from the active regions of the substrate. The semiconductor device is then ready for subsequent processing.
摘要翻译：公开了一种用于分离半导体衬底上的有源区的隔离方法。将不对应于活性区域的基板的部分蚀刻到预定深度。在一些氧化物，氮化物和电介质沉积步骤之后，光致抗蚀剂被图案化在电介质材料上，使得光致抗蚀剂完全覆盖衬底的有源区并且重叠到最终表示场氧化物区域的衬底部分中。去除未被光致抗蚀剂覆盖的电介质氮氧化物层的任何部分，并执行选择性外延生长（SEG）和外延横向过度生长（ELO）的组合步骤。然后将暴露的硅氧化，并从衬底的有源区域去除电介质，氮化物和氧化物层。然后半导体器件准备好用于后续处理。

57. 发明授权

US5581114A Self-aligned polysilicon base contact in a bipolar junction transistor 失效
标题翻译：双极结晶体管中的自对准多晶硅基极接触
公开(公告)号：US5581114A
公开(公告)日：1996-12-03
申请号：US482164
申请日：1995-06-07
申请人： Rashid Bashir , Francois Hebert
发明人： Rashid Bashir , Francois Hebert
IPC分类号： H01L21/8249 , H01L27/082 , H01L27/088 , H01L27/102
CPC分类号： H01L21/8249 , Y10S148/01 , Y10S257/90
摘要： A bipolar transistor in accordance with the invention includes a polysilicon base contact (607A) which is self-aligned with a polysilicon emitter (303). The polysilicon emitter is formed from a first polysilicon layer overlying an intrinsic base region (502) in a substrate (201). An extrinsic base (504) in the substrate is in contact with the intrinsic base and is self-aligned with a spacer (406) adjacent to the emitter. The polysilicon base contact is formed from a second polysilicon layer (407) in contact with the extrinsic base and overlying the emitter. A second sidewall spacer (508) is formed on the second polysilicon layer on step caused by the emitter. A protective layer (509, 510) formed on portions of the second polysilicon layer protects the base contact when the second spacer and the underlying portion of the second polysilicon layer are removed. The separation between the polysilicon base contact and the polysilicon emitter is controlled by the thickness the second polysilicon layer and the thickness of the spacers so that the base contact is self-aligned with a fixed separation from the emitter. Layer and spacer thicknesses define separation between the emitter and the base contact and permit sub-micron active regions in the substrate.
摘要翻译：根据本发明的双极晶体管包括与多晶硅发射器（303）自对准的多晶硅基极接触（607A）。多晶硅发射体由覆盖衬底（201）中的本征基极区（502）的第一多晶硅层形成。衬底中的外在基极（504）与本征基极接触并且与邻近发射极的间隔物（406）自对准。多晶硅基极接触由与外部基极接触并覆盖发射极的第二多晶硅层（407）形成。第二侧壁间隔物（508）由发射极引起的步骤形成在第二多晶硅层上。形成在第二多晶硅层的部分上的保护层（509,510）在第二间隔物和第二多晶硅层的下面部分被去除时保护基极接触。多晶硅基底触点和多晶硅发射极之间的间隔由第二多晶硅层的厚度和间隔物的厚度来控制，使得基极接触件与发射极的固定分离自对准。层和间隔物厚度限定了发射极和基极接触之间的间隔，并允许衬底中的亚微米有源区。

58. 发明授权

US5451532A Process for making self-aligned polysilicon base contact in a bipolar junction transistor 失效
标题翻译：在双极结型晶体管中进行自对准多晶硅基极接触的工艺
公开(公告)号：US5451532A
公开(公告)日：1995-09-19
申请号：US273530
申请日：1994-07-11
申请人： Rashid Bashir , Francois Hebert
发明人： Rashid Bashir , Francois Hebert
IPC分类号： H01L21/8249 , H01L21/8222
CPC分类号： H01L21/8249 , Y10S148/01 , Y10S257/90
摘要： A bipolar transistor in accordance with the invention includes a polysilicon base contact (607A) which is self-aligned with a polysilicon emitter (303). The polysilicon emitter is formed from a first polysilicon layer overlying an intrinsic base region (502) in a substrate (201). An extrinsic base (504) in the substrate is in contact with the intrinsic base and is self-aligned with a spacer (406) adjacent to the emitter. The polysilicon base contact is formed from a second polysilicon layer (407) in contact with the extrinsic base and overlying the emitter. A second sidewall spacer (508) is formed on the second polysilicon layer on step caused by the emitter. A protective layer (509, 510) formed on portions of the second polysilicon layer protects the base contact when the second spacer and the underlying portion of the second polysilicon layer are removed. The separation between the polysilicon base contact and the polysilicon emitter is controlled by the thickness the second polysilicon layer and the thickness of the spacers so that the base contact is self-aligned with a fixed separation from the emitter. Layer and spacer thicknesses define separation between the emitter and the base contact and permit sub-micron active regions in the substrate.
摘要翻译：根据本发明的双极晶体管包括与多晶硅发射器（303）自对准的多晶硅基极接触（607A）。多晶硅发射体由覆盖衬底（201）中的本征基极区（502）的第一多晶硅层形成。衬底中的外在基极（504）与本征基极接触并且与邻近发射极的间隔物（406）自对准。多晶硅基极接触由与外部基极接触并覆盖发射极的第二多晶硅层（407）形成。第二侧壁间隔物（508）由发射极引起的步骤形成在第二多晶硅层上。形成在第二多晶硅层的部分上的保护层（509,510）在去除第二间隔物和第二多晶硅层的下面部分时保护基极接触。多晶硅基底触点和多晶硅发射极之间的间隔由第二多晶硅层的厚度和间隔物的厚度来控制，使得基极接触件与发射极的固定分离自对准。层和间隔物厚度限定了发射极和基极接触之间的间隔，并允许衬底中的亚微米有源区。

59. 发明授权

US5439833A Method of making truly complementary and self-aligned bipolar and CMOS transistor structures with minimized base and gate resistances and parasitic capacitance 失效
标题翻译：制造具有最小的基极和栅极电阻和寄生电容的真正互补和自对准双极和CMOS晶体管结构的方法
公开(公告)号：US5439833A
公开(公告)日：1995-08-08
申请号：US213630
申请日：1994-03-15
申请人： Francois Hebert , Datong Chen , Rashid Bashir
发明人： Francois Hebert , Datong Chen , Rashid Bashir
IPC分类号： H01L21/8249 , H01L27/06 , H01L21/265
CPC分类号： H01L27/0623 , H01L21/8249 , Y10S148/009
摘要： A truly complementary bipolar transistor structure and a combined bipolar and CMOS transistor structure are disclosed, each including a silicide layer formed upon a substrate that acts as an extrinsic base and gate. Optionally, a layer of polysilicon can be formed between the silicide layer and the substrate. An oxide layer (LTO) is formed or deposited over the silicide layer by chemical vapor deposition (CVD). Selected regions are defined and etched using a photoresist layer. Subsequent steps of implanting, etching and metalization are performed to produce transistors with reduced gate and extrinsic base resistances. Polysilicon may be used, instead of metal, as a contact in one embodiment of the invention.
摘要翻译：公开了一种真正互补的双极晶体管结构和组合的双极和CMOS晶体管结构，每个晶体管结构包括形成在用作外部基极和栅极的衬底上的硅化物层。可选地，可以在硅化物层和衬底之间形成多晶硅层。通过化学气相沉积（CVD）在硅化物层上形成或沉积氧化物层（LTO）。使用光致抗蚀剂层限定和蚀刻所选择的区域。进行植入，蚀刻和金属化的后续步骤以产生具有减小的栅极和非本征基极电阻的晶体管。在本发明的一个实施方案中，可以使用多晶硅代替金属作为接触。

60. 发明授权

US09524957B2 Back-to-back stacked dies 有权
标题翻译：背对背堆叠模具
公开(公告)号：US09524957B2
公开(公告)日：2016-12-20
申请号：US13358718
申请日：2012-01-26
申请人： Francois Hebert , Steven R. Rivet , Michael Althar , Peter Oaklander
发明人： Francois Hebert , Steven R. Rivet , Michael Althar , Peter Oaklander
IPC分类号： H01R43/00 , H01L25/16 , H01L23/373 , H01L23/433 , H01L23/495 , H01L23/00 , H01L23/31 , H01L23/64
CPC分类号： H01L25/18 , H01L23/3107 , H01L23/3114 , H01L23/367 , H01L23/3732 , H01L23/4334 , H01L23/49517 , H01L23/49541 , H01L23/49562 , H01L23/49575 , H01L23/645 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L25/16 , H01L2224/05553 , H01L2224/13147 , H01L2224/16245 , H01L2224/291 , H01L2224/2919 , H01L2224/32013 , H01L2224/32145 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48106 , H01L2224/48137 , H01L2224/48247 , H01L2224/48472 , H01L2224/49111 , H01L2224/49171 , H01L2224/73253 , H01L2224/73265 , H01L2224/83801 , H01L2224/83855 , H01L2224/92247 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/06589 , H01L2924/01015 , H01L2924/01029 , H01L2924/10162 , H01L2924/12032 , H01L2924/1306 , H01L2924/13064 , H01L2924/13091 , H01L2924/1425 , H01L2924/14253 , H01L2924/1426 , H01L2924/181 , Y10T29/49121 , H01L2924/00012 , H01L2924/00014 , H01L2924/0665 , H01L2924/014 , H01L2924/00
摘要： Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.
摘要翻译：本文公开的实施例提供了包括具有有源侧和背侧的第一管芯的电路，其中第一管芯被倒装芯片安装到载体上。电路还包括堆叠在第一管芯的背面上的第二管芯，其中第二管芯堆叠在第一管芯上，使得第二管芯的背面面向第一管芯的背面，第二管芯的有源侧面对远离第一个模具。

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