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1. 发明授权

US5683932A Method of fabricating a planarized trench and field oxide isolation structure 失效
标题翻译：制造平面化沟槽和场氧化物隔离结构的方法
公开(公告)号：US5683932A
公开(公告)日：1997-11-04
申请号：US516625
申请日：1995-08-18
申请人： Rashid Bashir , Francois Hebert , Datong Chen
发明人： Rashid Bashir , Francois Hebert , Datong Chen
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229 , H01L21/76232 , Y10S438/97
摘要： An isolation method for separating active regions in a semiconductor substrate by combining field oxide formation with trench isolation is disclosed. Deep trenches are etched in a silicon substrate. An oxide layer is deposited over the entire substrate such that the oxide layer also fills the trenches that have been etched. A layer of polysilicon is deposited over the wafer and etched back to form polysilicon spacers. These polysilicon spacers are used to align a photoresist mask that is used to etch the oxide overlying the active regions of the substrate, thereby resulting in fully planarized isolation regions with fully walled active regions.
摘要翻译：公开了通过将场氧化物形成与沟槽隔离组合来分离半导体衬底中的有源区的隔离方法。在硅衬底中蚀刻深沟槽。在整个基板上沉积氧化物层，使得氧化物层也填充已被蚀刻的沟槽。一层多晶硅沉积在晶片上并被回蚀以形成多晶硅间隔物。这些多晶硅间隔物用于对齐用于蚀刻覆盖衬底的有源区域的氧化物的光致抗蚀剂掩模，由此导致完全平坦化的具有完全有壁的活性区域的隔离区域。

2. 发明授权

US5411913A Simple planarized trench isolation and field oxide formation using poly-silicon 失效
标题翻译：使用多晶硅简单的平坦化沟槽隔离和场氧化物形成
公开(公告)号：US5411913A
公开(公告)日：1995-05-02
申请号：US236387
申请日：1994-04-29
申请人： Rashid Bashir , Francois Hebert , Datong Chen
发明人： Rashid Bashir , Francois Hebert , Datong Chen
IPC分类号： H01L21/3105 , H01L21/763 , H01L21/311 , H01L21/76
CPC分类号： H01L21/31056 , H01L21/763
摘要： A device isolation scheme that is particularly suited to the fabrication of high density, high performance CMOS, bipolar, or BiCMOS devices, and overcomes many of the problems associated with existing isolation methods. Photolithographic techniques are used to define active regions on a substrate. Using the photoresist as a mask for the active regions, the silicon in the inactive regions is etched. A pad oxide layer and nitride layer are then formed on the substrate. A layer of oxide is then deposited and photolithographic techniques are again used to define the locations for desired trench structures. After removal of the remaining photoresist, deep trenches are etched in the silicon substrate. An oxidation step is then carried out to provide a layer of oxide lining the trenches, followed by deposition of a layer of poly-silicon over the substrate, filling the trenches. The poly-silicon layer is etched back, removing it from the tops of the trenches and the field regions, and leaving a poly-silicon spacer on the sides of those portions of the previously deposited oxide layer which cover the active regions. The spacers are used to align a photoresist mask which is used to etch away the oxide layer on top of the active regions. The spacers are then removed while keeping the photoresist mask intact, thereby protecting the poly-silicon on top of the trenches. The photoresist mask is then removed and the poly-silicon on top of each trench is oxidized to cap the trench. The result is a highly planar surface in which active regions are separated by field oxide or poly-silicon filled trenches.
摘要翻译：特别适用于制造高密度，高性能CMOS，双极或BiCMOS器件的器件隔离方案，并克服了与现有隔离方法相关的许多问题。光刻技术用于定义衬底上的有源区。使用光致抗蚀剂作为有源区的掩模，蚀刻非活性区中的硅。然后在衬底上形成焊盘氧化物层和氮化物层。然后沉积一层氧化物，再次使用光刻技术来定义所需沟槽结构的位置。在除去剩余的光致抗蚀剂之后，在硅衬底中蚀刻深沟槽。然后进行氧化步骤以提供在沟槽内衬的氧化层，随后在衬底上沉积多晶硅层，填充沟槽。将多晶硅层回蚀刻，将其从沟槽和场区域的顶部除去，并且在覆盖活性区域的先前沉积的氧化物层的那些部分的侧面留下多晶硅间隔物。间隔物用于对准用于蚀刻掉活性区域顶部上的氧化物层的光致抗蚀剂掩模。然后除去间隔物，同时保持光致抗蚀剂掩模完好无损，从而保护沟槽顶部的多晶硅。然后去除光致抗蚀剂掩模，并且每个沟槽顶部上的多晶硅被氧化以覆盖沟槽。结果是高度平坦的表面，其中有源区域被场氧化物或多晶硅填充的沟槽分离。

3. 发明授权

US5691232A Planarized trench and field oxide isolation scheme 失效
标题翻译：平面化沟槽和场氧化物隔离方案
公开(公告)号：US5691232A
公开(公告)日：1997-11-25
申请号：US563862
申请日：1995-11-29
申请人： Rashid Bashir , Francois Hebert , Datong Chen
发明人： Rashid Bashir , Francois Hebert , Datong Chen
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229 , H01L21/76232 , Y10S438/97
摘要： An isolation method for separating active regions in a semiconductor substrate by combining field oxide formation with trench isolation is disclosed. Deep trenches are etched in a silicon substrate. An oxide layer is deposited over the entire substrate such that the oxide layer also fills the trenches that have been etched. Next, a layer of polysilicon is deposited over the wafer and etched back to form polysilicon spacers. These polysilicon spacers are used to align a photoresist mask that is used to etch the oxide overlying the active regions of the substrate, thereby resulting in fully planarized isolation regions with fully walled active regions.
摘要翻译：公开了通过将场氧化物形成与沟槽隔离组合来分离半导体衬底中的有源区的隔离方法。在硅衬底中蚀刻深沟槽。在整个基板上沉积氧化物层，使得氧化物层也填充已被蚀刻的沟槽。接下来，将多晶硅层沉积在晶片上并被回蚀以形成多晶硅间隔物。这些多晶硅间隔物用于对齐用于蚀刻覆盖衬底的有源区域的氧化物的光致抗蚀剂掩模，由此导致完全平坦化的具有完全有壁的活性区域的隔离区域。

4. 发明授权

US5827762A Method for forming buried interconnect structue having stability at high temperatures 失效
标题翻译：用于形成在高温下具有稳定性的掩埋互连结构的方法
公开(公告)号：US5827762A
公开(公告)日：1998-10-27
申请号：US850603
申请日：1997-05-02
申请人： Rashid Bashir , Francois Hebert , Datong Chen
发明人： Rashid Bashir , Francois Hebert , Datong Chen
IPC分类号： H01L21/768 , H01L21/8238
CPC分类号： H01L21/76886
摘要： A buried interconnect structure which is stable at the high temperatures involved in BiCMOS, bipolar, and CMOS transistor process flows, and a method of making the same. The interconnect structure is fully insulated and can be used to form stable, doped structures suitable for use as electrodes and gate structures in a CMOS process, or to form low resistance contacts to N or P-type silicon as part of a bipolar process. Because the interconnect structure is buried and fully insulated from surrounding structures, it may be used to form complex, multi-level devices having a minimized geometry and increased circuit density.
摘要翻译：在BiCMOS，双极和CMOS晶体管工艺流程中涉及的高温下稳定的埋入式互连结构及其制造方法。互连结构是完全绝缘的，并且可以用于形成适合用作CMOS工艺中的电极和栅极结构的稳定的掺杂结构，或者作为双极工艺的一部分形成作为N型或P型硅的低电阻接触。因为互连结构被掩埋并且与周围结构完全绝缘，所以它可用于形成具有最小几何形状和增加的电路密度的复杂的多电平器件。

5. 发明授权

US5681776A Planar selective field oxide isolation process using SEG/ELO 失效
标题翻译：使用SEG / ELO的平面选择场氧化物隔离工艺
公开(公告)号：US5681776A
公开(公告)日：1997-10-28
申请号：US708359
申请日：1996-09-04
申请人： Francois Hebert , Datong Chen , Rashid Bashir
发明人： Francois Hebert , Datong Chen , Rashid Bashir
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76227
摘要： An isolation method for separating active regions on a semiconductor substrate is disclosed. Portions of the substrate not corresponding to the active regions are etched to a predetermined depth. After some oxide, nitride and dielectric deposition steps, a photoresist is patterned on the dielectric material such that the photoresist completely covers the active regions of the substrate and overlaps into the portions of the substrate that are eventually to represent field oxide regions. Any portion of the dielectric, nitride oxide layers that are not covered by the photoresist are removed and a combined step of selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) is performed. The exposed silicon is then oxidizing and the dielectric, nitride and oxide layers are removed from the active regions of the substrate. The semiconductor device is then ready for subsequent processing.
摘要翻译：公开了一种用于分离半导体衬底上的有源区的隔离方法。将不对应于活性区域的基板的部分蚀刻到预定深度。在一些氧化物，氮化物和电介质沉积步骤之后，光致抗蚀剂被图案化在电介质材料上，使得光致抗蚀剂完全覆盖衬底的有源区并且重叠到最终表示场氧化物区域的衬底部分中。去除未被光致抗蚀剂覆盖的电介质氮氧化物层的任何部分，并执行选择性外延生长（SEG）和外延横向过度生长（ELO）的组合步骤。然后将暴露的硅氧化，并从衬底的有源区域去除电介质，氮化物和氧化物层。然后半导体器件准备好用于后续处理。

6. 发明授权

US5439833A Method of making truly complementary and self-aligned bipolar and CMOS transistor structures with minimized base and gate resistances and parasitic capacitance 失效
标题翻译：制造具有最小的基极和栅极电阻和寄生电容的真正互补和自对准双极和CMOS晶体管结构的方法
公开(公告)号：US5439833A
公开(公告)日：1995-08-08
申请号：US213630
申请日：1994-03-15
申请人： Francois Hebert , Datong Chen , Rashid Bashir
发明人： Francois Hebert , Datong Chen , Rashid Bashir
IPC分类号： H01L21/8249 , H01L27/06 , H01L21/265
CPC分类号： H01L27/0623 , H01L21/8249 , Y10S148/009
摘要： A truly complementary bipolar transistor structure and a combined bipolar and CMOS transistor structure are disclosed, each including a silicide layer formed upon a substrate that acts as an extrinsic base and gate. Optionally, a layer of polysilicon can be formed between the silicide layer and the substrate. An oxide layer (LTO) is formed or deposited over the silicide layer by chemical vapor deposition (CVD). Selected regions are defined and etched using a photoresist layer. Subsequent steps of implanting, etching and metalization are performed to produce transistors with reduced gate and extrinsic base resistances. Polysilicon may be used, instead of metal, as a contact in one embodiment of the invention.
摘要翻译：公开了一种真正互补的双极晶体管结构和组合的双极和CMOS晶体管结构，每个晶体管结构包括形成在用作外部基极和栅极的衬底上的硅化物层。可选地，可以在硅化物层和衬底之间形成多晶硅层。通过化学气相沉积（CVD）在硅化物层上形成或沉积氧化物层（LTO）。使用光致抗蚀剂层限定和蚀刻所选择的区域。进行植入，蚀刻和金属化的后续步骤以产生具有减小的栅极和非本征基极电阻的晶体管。在本发明的一个实施方案中，可以使用多晶硅代替金属作为接触。

7. 发明授权

US5385861A Planarized trench and field oxide and poly isolation scheme 失效
标题翻译：平面化沟槽和场氧化物和多晶隔离方案
公开(公告)号：US5385861A
公开(公告)日：1995-01-31
申请号：US213144
申请日：1994-03-15
申请人： Rashid Bashir , Francois Hebert , Datong Chen
发明人： Rashid Bashir , Francois Hebert , Datong Chen
IPC分类号： H01L21/762 , H01L21/763 , H01L21/76
CPC分类号： H01L21/76227 , H01L21/763 , Y10S148/05
摘要： A novel device isolation scheme for separating active regions on a semiconductor substrate by combining field oxide formation with trench isolation is disclosed. According to this scheme, shallow and deep trenches are etched into the semiconductor substrate. A layer of nitride is deposited over the entire substrate followed by a layer of poly-silicon. Oxide spacers on the poly-silicon and a photoresist mask is aligned within the oxide spacers, thereby permitting the selective etching of the poly-silicon layer. The poly-silicon layer overlying the active regions of the semiconductor substrate are etched away. Then an oxidation step is performed such that the poly-silicon layer filling the shallow trenches is oxidized while the poly-silicon filling the deep trenches remains unoxidized. The alignment of the photoresist becomes highly non-critical because of the use of the oxide spacers and fully walled junctions are provided.
摘要翻译：公开了一种用于通过组合场氧化物形成和沟槽隔离来分离半导体衬底上的有源区的新型器件隔离方案。根据该方案，将浅沟槽和深沟槽蚀刻到半导体衬底中。一层氮化物沉积在整个衬底上，随后是一层多晶硅。在多晶硅和光致抗蚀剂掩模之间的氧化物间隔物在氧化物间隔物内对准，从而允许多晶硅层的选择性蚀刻。覆盖半导体衬底的有源区的多晶硅层被蚀刻掉。然后执行氧化步骤，使得填充浅沟槽的多晶硅层被氧化，而填充深沟槽的多晶硅保持未氧化。由于使用氧化物间隔物并且提供了完全的壁结，因此光致抗蚀剂的取向变得非常关键。

8. 发明授权

US5930635A Complementary Si/SiGe heterojunction bipolar technology 失效
标题翻译：互补Si / SiGe异质结双极技术
公开(公告)号：US5930635A
公开(公告)日：1999-07-27
申请号：US850610
申请日：1997-05-02
申请人： Rashid Bashir , Francois Hebert
发明人： Rashid Bashir , Francois Hebert
IPC分类号： H01L21/8228 , H01L21/331
CPC分类号： H01L21/8228
摘要： A method of manufacturing truly complementary bipolar transistors on a common substrate. The method results in the fabrication of vertical NPN and PNP transistors which have an identical structure and mode of operation, with both devices operating in the downward direction. The inventive method permits independent control of the characteristics of the two devices, producing a closely matched performance for both devices.
摘要翻译：在公共衬底上制造真正互补的双极晶体管的方法。该方法导致制造具有相同结构和操作模式的垂直NPN和PNP晶体管，两个器件在向下的方向上工作。本发明的方法允许独立控制两个装置的特性，从而产生两个装置的紧密匹配的性能。

9. 发明授权

US5856239A Tungsten silicide/ tungsten polycide anisotropic dry etch process 失效
标题翻译：硅化钨/聚硅氧烷多向干蚀刻工艺
公开(公告)号：US5856239A
公开(公告)日：1999-01-05
申请号：US850573
申请日：1997-05-02
申请人： Rashid Bashir , Abul Ehsanul Kabir , Francois Hebert
发明人： Rashid Bashir , Abul Ehsanul Kabir , Francois Hebert
IPC分类号： H01L21/3213 , H01L21/00
CPC分类号： H01L21/32137
摘要： A process for anisotropically etching a tungsten silicide or tungsten polycide structure. If the silicide/polycide film has an overlying oxide layer, the insulating layer is removed by a gas mixture composed of CHF.sub.3 and C.sub.2 F.sub.6. The WSi.sub.x silicide layer is then etched in a reactive ion etch using a gas mixture formed from Cl.sub.2 and C.sub.2 F.sub.6, with sufficient O.sub.2 added to control polymer formation and prevent undercutting of the silicide. The polysilicon layer is then etched using a gas mixture formed from Cl.sub.2 and C.sub.2 F.sub.6. The result is a highly anisotropic etch process which preserves the critical dimension of the etched structures. The etch parameters may be varied to produce a tapered sidewall profile for use in the formation of butted contacts without the need for a contact mask.
摘要翻译：用于各向异性蚀刻硅化钨或聚钨酸钨结构的方法。如果硅化物/多硅化物膜具有上覆氧化物层，则通过由CHF 3和C 2 F 6组成的气体混合物除去绝缘层。然后使用由Cl 2和C 2 F 6形成的气体混合物在反应离子蚀刻中对WSix硅化物层进行蚀刻，加入足够的O 2以控制聚合物形成并防止硅化物的底切。然后使用由Cl 2和C 2 F 6形成的气体混合物来蚀刻多晶硅层。结果是高度各向异性的蚀刻工艺，其保留蚀刻结构的临界尺寸。可以改变蚀刻参数以产生用于形成对接触点的锥形侧壁轮廓，而不需要接触掩模。

10. 发明授权

US5581114A Self-aligned polysilicon base contact in a bipolar junction transistor 失效
标题翻译：双极结晶体管中的自对准多晶硅基极接触
公开(公告)号：US5581114A
公开(公告)日：1996-12-03
申请号：US482164
申请日：1995-06-07
申请人： Rashid Bashir , Francois Hebert
发明人： Rashid Bashir , Francois Hebert
IPC分类号： H01L21/8249 , H01L27/082 , H01L27/088 , H01L27/102
CPC分类号： H01L21/8249 , Y10S148/01 , Y10S257/90
摘要： A bipolar transistor in accordance with the invention includes a polysilicon base contact (607A) which is self-aligned with a polysilicon emitter (303). The polysilicon emitter is formed from a first polysilicon layer overlying an intrinsic base region (502) in a substrate (201). An extrinsic base (504) in the substrate is in contact with the intrinsic base and is self-aligned with a spacer (406) adjacent to the emitter. The polysilicon base contact is formed from a second polysilicon layer (407) in contact with the extrinsic base and overlying the emitter. A second sidewall spacer (508) is formed on the second polysilicon layer on step caused by the emitter. A protective layer (509, 510) formed on portions of the second polysilicon layer protects the base contact when the second spacer and the underlying portion of the second polysilicon layer are removed. The separation between the polysilicon base contact and the polysilicon emitter is controlled by the thickness the second polysilicon layer and the thickness of the spacers so that the base contact is self-aligned with a fixed separation from the emitter. Layer and spacer thicknesses define separation between the emitter and the base contact and permit sub-micron active regions in the substrate.
摘要翻译：根据本发明的双极晶体管包括与多晶硅发射器（303）自对准的多晶硅基极接触（607A）。多晶硅发射体由覆盖衬底（201）中的本征基极区（502）的第一多晶硅层形成。衬底中的外在基极（504）与本征基极接触并且与邻近发射极的间隔物（406）自对准。多晶硅基极接触由与外部基极接触并覆盖发射极的第二多晶硅层（407）形成。第二侧壁间隔物（508）由发射极引起的步骤形成在第二多晶硅层上。形成在第二多晶硅层的部分上的保护层（509,510）在第二间隔物和第二多晶硅层的下面部分被去除时保护基极接触。多晶硅基底触点和多晶硅发射极之间的间隔由第二多晶硅层的厚度和间隔物的厚度来控制，使得基极接触件与发射极的固定分离自对准。层和间隔物厚度限定了发射极和基极接触之间的间隔，并允许衬底中的亚微米有源区。

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