专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20130268732A1 SYSTEM AND METHOD FOR CACHE ACCESS 有权
标题翻译：用于缓存访问的系统和方法
公开(公告)号：US20130268732A1
公开(公告)日：2013-10-10
申请号：US13440728
申请日：2012-04-05
申请人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell
发明人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F1/3225 , G06F1/3275 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： The rows of a cache are generally maintained in a low power state. In response to a memory access operation, the data processor predicts a plurality of cache rows that may be targeted by the operation, and transitions each of the plurality of cache rows to an active state to prepare them for access. The plurality of cache rows are predicted based on speculatively decoding a portion of a base address and a corresponding portion of an offset without performing a full addition of the portions. Because a full addition is not performed, the speculative decoding can be performed at sufficient speed to allow the set of rows to be transitioned to the active state before full decoding of the memory address is completed. The cache row associated with the memory address is therefore ready for access when decoding is complete, maintaining low latency for cache accesses.
摘要翻译：缓存的行通常维持在低功率状态。响应于存储器访问操作，数据处理器预测可能由操作定向的多个高速缓存行，并且将多个高速缓存行中的每一个转换为活动状态以准备它们进行访问。基于对基本地址的一部分和偏移的对应部分的推测性解码来预测多个高速缓存行，而不执行部分的完全添加。由于没有执行完全相加，所以可以以足够的速度执行推测解码，以便在存储器地址的完全解码完成之前允许该组行转换到活动状态。因此，当解码完成时，与存储器地址相关联的高速缓存行可以进行访问，从而保持高速缓存访问的低延迟。

52. 发明申请

US20130265818A1 WRITE CONTENTION-FREE, NOISE-TOLERANT MULTI-PORT BITCELL 有权
标题翻译：无限制，无噪声多端口BITCELL
公开(公告)号：US20130265818A1
公开(公告)日：2013-10-10
申请号：US13441414
申请日：2012-04-06
申请人： Ambica Ashok , Ravindraraj Ramaraju , Andrew C. Russell
发明人： Ambica Ashok , Ravindraraj Ramaraju , Andrew C. Russell
IPC分类号： G11C11/413
CPC分类号： G11C8/16 , G11C7/12 , G11C7/18 , G11C8/14 , G11C11/419
摘要： A multi-port memory cell of a multi-port memory array includes a first inverter that inverter is disabled by a first subset of write word lines and a second inverter, cross coupled with the first inverter, wherein the second inverter is disabled by a second subset of the plurality of write word lines. A first selection circuit has data inputs coupled to a first subset of a plurality of write bit lines, selection inputs coupled to the first subset of the plurality of write word lines, and an output coupled to the input of the second inverter. The second selection circuit has data inputs coupled to a second subset of the plurality of write bit lines, selection inputs coupled to the second subset of the plurality of write word lines, and an output coupled to the input of the first inverter.
摘要翻译：多端口存储器阵列的多端口存储单元包括第一反相器，反相器被写入字线的第一子集禁止，第二反相器与第一反相器交叉耦合，其中第二反相器被第二反相器禁用多个写入字线的子集。第一选择电路具有耦合到多个写位线的第一子集的数据输入，耦合到多个写字线的第一子集的选择输入以及耦合到第二反相器的输入的输出。第二选择电路具有耦合到多个写位线的第二子集的数据输入，耦合到多个写字线的第二子集的选择输入以及耦合到第一反相器的输入的输出。

53. 发明授权

US08484523B2 Sequential digital circuitry with test scan 有权
标题翻译：具有测试扫描的顺序数字电路
公开(公告)号：US08484523B2
公开(公告)日：2013-07-09
申请号：US12729826
申请日：2010-03-23
申请人： Ravindraraj Ramaraju , Prashant U. Kenkare , Gary A. Mussemann , Mihir S. Sabnis
发明人： Ravindraraj Ramaraju , Prashant U. Kenkare , Gary A. Mussemann , Mihir S. Sabnis
IPC分类号： G01R31/28
CPC分类号： G06F11/267 , G01R31/318541 , G01R31/318575
摘要： A digital scan chain system having test scan has a plurality of flip-flop modules, each of the plurality of flip-flop modules having a first data bit input, a second data bit input, a test bit input, a clock input, a first data bit output, a second data bit output, and a test bit output. The test bit output of a first flip-flop module is directly connected to the test bit input of a second flip-flop module with no intervening circuitry. First and second multiplexed master/slave flip-flops are directly serially connected. A clocked latch is coupled to the output of the second multiplexed master/slave flip-flop and provides the test bit output. The clocked latch is clocked only during a test mode to save power.
摘要翻译：具有测试扫描的数字扫描链系统具有多个触发器模块，多个触发器模块中的每一个具有第一数据位输入，第二数据位输入，测试位输入，时钟输入，第一数据位输出，第二数据位输出和测试位输出。第一触发器模块的测试位输出直接连接到第二触发器模块的测试位输入，而没有中间电路。第一和第二复用主/从触发器直接串行连接。时钟锁存器耦合到第二复用主/从触发器的输出并提供测试位输出。时钟锁存器仅在测试模式下计时才能节省电量。

54. 发明申请

US20130154707A1 RECOVERABLE AND RECONFIGURABLE PIPELINE STRUCTURE FOR STATE-RETENTION POWER GATING 有权
标题翻译：用于状态保持功率补偿的可恢复和可重新配置的管道结构
公开(公告)号：US20130154707A1
公开(公告)日：2013-06-20
申请号：US13403597
申请日：2012-02-23
申请人： Shayan Zhang , William C. Moyer , Ravindraraj Ramaraju
发明人： Shayan Zhang , William C. Moyer , Ravindraraj Ramaraju
IPC分类号： H03K3/00
CPC分类号： H03K3/35606 , H03K3/356008
摘要： A system, electronic circuit, and method are disclosed. A method embodiment comprises receiving a control signal associated with a power gating operation mode of an electronic circuit, applying a reference voltage to the electronic circuit based upon the power gating operation mode, and maintaining data representing a state of a logic stage of the electronic circuit based upon the power gating operation mode. Maintaining comprises, in the described embodiment, storing data of a state of a first logic stage of the electronic circuit within a first storage element in a first power gating operation mode, and recovering data of a state of a second logic stage of the electronic circuit utilizing the data of the state of the first logic stage of the electronic circuit within the first storage element in a second power gating operation mode.
摘要翻译：公开了一种系统，电子电路和方法。方法实施例包括接收与电子电路的电源门控操作模式相关联的控制信号，基于电源门控操作模式将参考电压施加到电子电路，以及维护表示电子电路的逻辑级状态的数据基于电源门控操作模式。在所描述的实施例中，维护包括在第一电源门控操作模式中将电子电路的第一逻辑级的状态的数据存储在第一存储元件内，以及恢复电子电路的第二逻辑级的状态的数据在第二电源门控操作模式中利用第一存储元件内的电子电路的第一逻辑级的状态的数据。

55. 发明申请

US20130046928A1 Memory Management Unit Tag Memory 有权
标题翻译：内存管理单元标签内存
公开(公告)号：US20130046928A1
公开(公告)日：2013-02-21
申请号：US13213900
申请日：2011-08-19
申请人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare , Jogendra C. Sarker
发明人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare , Jogendra C. Sarker
IPC分类号： G06F12/02
CPC分类号： G06F12/1027 , G06F9/355 , G06F9/3824 , G06F9/3832 , G11C15/04
摘要： A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).
摘要翻译：一种方法和数据处理系统，用于通过将标记存储器单元（114）与操作数加法器电路（112）并行放置来访问存储器阵列中的入口，以使标签查找和直接产生投机方式命中/未命中信息（126）不使用操作数加法器的输出和从操作数（111,113）中读出。将来自操作数（111,113）的PGZ编码的地址位（0:51）与进位值（Cout48）一起施加到内容寻址存储器阵列（114），以产生两个推测的命中/未命中信号。从最低有效基址和偏移地址位计算的和值（EA51）确定选择哪种推测性命中/未命中信号用于输出（126）。

56. 发明授权

US08379468B2 Word line fault detection 有权
标题翻译：字线故障检测
公开(公告)号：US08379468B2
公开(公告)日：2013-02-19
申请号：US13169397
申请日：2011-06-27
申请人： Ravindraraj Ramaraju , Alexander B. Hoefler
发明人： Ravindraraj Ramaraju , Alexander B. Hoefler
IPC分类号： G11C29/00
CPC分类号： G11C29/025 , G11C11/40 , G11C29/024 , G11C2029/1202 , G11C2029/2602
摘要： In a memory having a word line driver and a ROM having N bit positions and a plurality of rows in which each row is coupled to a corresponding word line of the word line driver and stores a unique N bit value, a method includes activating, by the word line driver, a selected word line, and, for each bit position, determining whether a value of a true bit line of the bit position is at a same logic state as a value of a complementary bit line of the bit position when the word line driver activates the selected word line. In response to determining that a value of the true bit line is at the same logic state as the value of the complementary bit line for any of the N bit positions, providing a multiple word line fault indicator indicating that multiple word lines are activated simultaneously.
摘要翻译：在具有字线驱动器和具有N位位置的ROM的存储器和多行中，其中每行耦合到字线驱动器的对应字线并存储唯一的N位值，该方法包括通过字线驱动器，所选字线，并且对于每个位位置，确定位位置的真位线的值是否与位位置的互补位线的值处于与位位置的互补位线的值相同的逻辑状态字线驱动程序激活所选字线。响应于确定真位位线的值与用于任何N位位置的互补位线的值处于相同的逻辑状态，提供指示多个字线同时被激活的多字线故障指示符。

57. 发明授权

US08319548B2 Integrated circuit having low power mode voltage regulator 有权
标题翻译：集成电路具有低功耗模式电压调节器
公开(公告)号：US08319548B2
公开(公告)日：2012-11-27
申请号：US12622277
申请日：2009-11-19
申请人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg , Hector Sanchez , Bradley J. Garni
发明人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg , Hector Sanchez , Bradley J. Garni
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , G11C5/147
摘要： A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.
摘要翻译：电压调节器调节节点处的电压，并且具有耦合到节点的电路以向节点提供电流。耦合在节点和第一电源电压端子之间的调节晶体管具有并联耦合的禁用晶体管，并且通过将第一电源电压端子直接连接到节点来选择性地禁止。反相级具有连接到调节晶体管的输出端。负载晶体管具有耦合到第二电源电压端子的第一电流电极和连接在一起并耦合到反相级的输入端的控制电极和第二电流电极。感测晶体管具有耦合到负载晶体管的第二电流电极的第一电流电极，直接连接到节点的控制电极和耦合到第一电源电压端子的第二电流电极。

58. 发明授权

US08143929B2 Flip-flop having shared feedback and method of operation 有权
标题翻译：触发器具有共享的反馈和操作方法
公开(公告)号：US08143929B2
公开(公告)日：2012-03-27
申请号：US12607574
申请日：2009-10-28
申请人： Ravindraraj Ramaraju , Prashant U. Kenkare
发明人： Ravindraraj Ramaraju , Prashant U. Kenkare
IPC分类号： H03K3/356
CPC分类号： H03K3/356156 , H03K3/356173
摘要： A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, the second node is coupled to a third node to couple the first data signal to the third node. The first node is decoupled from the second node and a first step of latching the first data signal at the third node is performed, wherein the first step of latching is through the second node while the second node is coupled to the third node. The second node is decoupled from the third node and a second step of latching is performed wherein the first data signal latched at the third node while the second node is decoupled from the third node.
摘要翻译：一种操作电路的方法包括在第一节点处接收第一数据信号。第一节点耦合到第二节点以将第一数据信号耦合到第二节点。在将第一节点耦合到第二节点之后，第二节点耦合到第三节点以将第一数据信号耦合到第三节点。执行第一节点与第二节点的耦合，并且执行在第三节点处锁存第一数据信号的第一步骤，其中锁定的第一步骤是通过第二节点，而第二节点耦合到第三节点。第二节点与第三节点分离，并执行锁定的第二步骤，其中第一数据信号在第三节点处锁存，而第二节点与第三节点分离。

59. 发明申请

US20120033520A1 MEMORY WITH LOW VOLTAGE MODE OPERATION 有权
标题翻译：低电压模式运行的存储器
公开(公告)号：US20120033520A1
公开(公告)日：2012-02-09
申请号：US12850533
申请日：2010-08-04
申请人： Huy B. Nguyen , Troy L. Cooper , Ravindraraj Ramaraju , Andrew C. Russell
发明人： Huy B. Nguyen , Troy L. Cooper , Ravindraraj Ramaraju , Andrew C. Russell
IPC分类号： G11C5/14
CPC分类号： G11C11/417
摘要： A memory comprising memory cells wherein the memory is configured to operate in a normal voltage mode and a low voltage mode. The method includes during the normal voltage mode, operating the memory cells at a first voltage across each of the memory cells. The method further includes upon transitioning from the normal voltage mode to the low voltage mode, operating the memory cells at a second voltage across each of the memory cells, wherein the second voltage is lower than the first voltage. The method further includes performing an access on a subset of the memory cells while maintaining the second voltage across the memory cells.
摘要翻译：一种存储器，包括存储器单元，其中存储器被配置为在正常电压模式和低电压模式下操作。该方法包括在正常电压模式期间，以每个存储器单元的第一电压操作存储器单元。该方法还包括在从正常电压模式转换到低电压模式时，在每个存储单元上以第二电压操作存储单元，其中第二电压低于第一电压。该方法还包括在保持存储器单元两端的第二电压的同时对存储器单元的子集执行访问。

60. 发明申请

US20120032655A1 MULTISTAGE VOLTAGE REGULATOR CIRCUIT 有权
标题翻译：多电平电压调节器电路
公开(公告)号：US20120032655A1
公开(公告)日：2012-02-09
申请号：US12853106
申请日：2010-08-09
申请人： Ravindraraj Ramaraju , Kenneth R. Burch , Charles E. Seaberg
发明人： Ravindraraj Ramaraju , Kenneth R. Burch , Charles E. Seaberg
IPC分类号： G05F1/10
CPC分类号： G11C5/147 , G05F1/00 , G05F1/577
摘要： A circuit including a multistage voltage regulator having a plurality of stages each including a regulated node and a bias transistor. The bias transistors and regulated nodes are configured to control the voltage of the regulated nodes. For at least some of the stages, the regulated nodes are coupled to voltage supply terminals of circuit modules of the stages.
摘要翻译：一种电路，包括具有多个级的多级稳压器，每个级包括调节节点和偏置晶体管。偏置晶体管和调节节点配置为控制受调节节点的电压。对于至少一些级，调节节点耦合到级的电路模块的电压端。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式