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51. 发明授权

US06272603B1 Cache coherency protocol having hovering (H), recent (R), and tagged (T) states 失效
标题翻译：具有悬停（H），最近（R）和标记（T）状态的高速缓存一致性协议
公开(公告)号：US06272603B1
公开(公告)日：2001-08-07
申请号：US09024319
申请日：1998-02-17
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1208
CPC分类号： G06F12/0833
摘要： A cache and method of maintaining cache coherency in a data processing system are described. The data processing system includes a system memory, a plurality of processors, and a plurality of caches coupled to an interconnect. According to the method, a first data item is stored in a first of the caches in association with an address tag indicating an address of the first data item. A coherency indicator in the first cache is set to a first state that indicates that the address tag is valid and that the first data item is invalid. If, while the coherency indicator is set to the first state, the first cache receives a data transfer on the interconnect associated with the address indicated by the address tag, where the data transfer includes a second data item that is modified with respect to a corresponding data item in the system memory, the second data item is stored in the first cache in association with the address tag. In addition, the coherency indicator is updated to a second state indicating that the second data item is valid and that the first cache is responsible for writing back the second data item to system memory.
摘要翻译：描述了在数据处理系统中维持高速缓存一致性的缓存和方法。数据处理系统包括系统存储器，多个处理器以及耦合到互连的多个高速缓存。根据该方法，第一数据项与指示第一数据项的地址的地址标签相关联地存储在第一缓存中。第一高速缓存中的一致性指示符被设置为指示地址标签有效并且第一数据项无效的第一状态。如果在一致性指示符被设置为第一状态的情况下，第一高速缓存接收与由地址标签指示的地址相关联的互连上的数据传输，其中数据传输包括相对于对应的修改修改的第二数据项系统存储器中的数据项，第二数据项与地址标签相关联地存储在第一高速缓存中。此外，一致性指示符被更新为指示第二数据项有效的第二状态，并且第一高速缓存负责将第二数据项写回系统存储器。

52. 发明授权

US06263407B1 Cache coherency protocol including a hovering (H) state having a precise mode and an imprecise mode 失效
标题翻译：缓存一致性协议包括具有精确模式和不精确模式的悬停（H）状态
公开(公告)号：US06263407B1
公开(公告)日：2001-07-17
申请号：US09024612
申请日：1998-02-17
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0833
摘要： A first data item is stored in a first cache in association with an address tag indicating an address of the data item. A coherency indicator in the first cache is set to a first state that indicates that the first data item is valid. In response to another cache indicating an intent to store to the address indicated by the address tag while the coherency indicator is set to the first state, the coherency indicator is updated to a second state that indicates that the address tag is valid and that the first data item is invalid. Thereafter, in response to detection of a remotely-sourced data transfer that is associated with the address indicated by the address tag and that includes a second data item, a determination is made, in response to a mode of operation of the first cache, whether or not to update the first cache. In response to a determination to make an update to the first cache, the first data item is replaced by storing the second data item in association with the address tag and the coherency indicator is updated to a third state that indicates that the second data item is valid. In one embodiment, the operating modes of the first cache include a precise mode in which cache updates are always performed and an imprecise mode in which cache updates are selectively performed. The operating mode of the first cache may be set by either hardware or software.
摘要翻译：与指示数据项的地址的地址标签相关联地将第一数据项存储在第一高速缓存中。第一高速缓存中的一致性指示符被设置为指示第一数据项有效的第一状态。响应于指示在将一致性指示符设置为第一状态时存储到由地址标签指示的地址的意图的另一高速缓存，将一致性指示符更新为指示地址标签有效的第二状态，并且第一数据项无效。此后，响应于与由地址标签指示的地址相关联并且包括第二数据项的远程来源的数据传输的检测，响应于第一高速缓存的操作模式，确定是否或不更新第一个缓存。响应于对第一高速缓存进行更新的确定，通过与地址标签相关联地存储第二数据项来替换第一数据项，并且一致性指示符被更新为指示第二数据项是有效。在一个实施例中，第一高速缓存的操作模式包括总是执行高速缓存更新的精确模式以及选择性地执行高速缓存更新的不精确模式。第一缓存的操作模式可以由硬件或软件来设置。

53. 发明授权

US06185658B2 Cache with enhanced victim selection using the coherency states of cache lines 失效
标题翻译：使用高速缓存行的一致性状态的增强的受害者选择的缓存
公开(公告)号：US06185658B2
公开(公告)日：2001-02-06
申请号：US08992137
申请日：1997-12-17
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/126
摘要： A method of evicting a cache block from a congruence class in a cache of a multi-processor computer system. After a cache miss, one of the cache blocks in the congruence class is selected for eviction based on the cache coherency states of the cache blocks. Any block having an Invalid state is preferably selected but, if such a block is not present, then one is preferably selected that has an invalid-type state, such as the new Hover state. If there are many blocks in the Hover state, then the least recently used is deallocated. If neither of these types of blocks are present, then a block is preferably selected for deallocation which is in the Modified state. This intelligent approach to victim selection generally improves cache performance.
摘要翻译：一种从多处理器计算机系统的高速缓存中的同余类驱逐高速缓存块的方法。在高速缓存未命中之后，基于高速缓存块的高速缓存一致性状态，选择同余类中的一个缓存块进行驱逐。优选地选择具有无效状态的块，但是如果不存在这样的块，则优选地选择具有诸如新的悬停状态的无效类型状态的块。如果悬停状态有多个块，那么最近最少使用的块被取消分配。如果这些类型的块都不存在，则优选地选择处于修改状态的解除分配的块。这种对受害者选择的智能方法通常提高了缓存性能。

54. 发明授权

US6145059A Cache coherency protocols with posted operations and tagged coherency states 失效
标题翻译：具有发布操作和标记的一致性状态的缓存一致性协议
公开(公告)号：US6145059A
公开(公告)日：2000-11-07
申请号：US24383
申请日：1998-02-17
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F12/0831
摘要： A method of avoiding deadlocks in cache coherency protocol for a multi-processor computer system, by loading a memory value into a plurality of cache blocks, assigning a first coherency state having a higher collision priority to only one of the cache blocks, and assigning one or more additional coherency states having lower collision priorities to all of the remaining cache blocks. Different system bus codes can be used to indicate the priority of conflicting requests (e.g., DClaim operations) to modify the memory value. The invention also allows folding or elimination of redundant DClaim operations, and can be applied in a global versus local manner within a multi-processor computer system having processing units grouped into at least two clusters.
摘要翻译：一种通过将存储器值加载到多个高速缓存块中来避免多处理器计算机系统的高速缓存一致性协议中的死锁的方法，将具有较高冲突优先级的第一相关性状态分配给仅一个高速缓存块，并且分配一个或更多的附加一致性状态对所有剩余的高速缓存块具有较低的冲突优先级。可以使用不同的系统总线代码来指示冲突请求的优先级（例如，DClaim操作）来修改存储器值。本发明还允许折叠或消除冗余DClaim操作，并且可以在具有被分组为至少两个簇的处理单元的多处理器计算机系统内以全局与局部方式应用。

55. 发明授权

US6145038A Method and system for early slave forwarding of strictly ordered bus operations 失效
标题翻译：严格有序的公共汽车运行的早期从机转发的方法和系统
公开(公告)号：US6145038A
公开(公告)日：2000-11-07
申请号：US833228
申请日：1997-10-31
申请人： Jerry Don Lewis , John Steven Dodson , Ravi Kumar Arimilli
发明人： Jerry Don Lewis , John Steven Dodson , Ravi Kumar Arimilli
IPC分类号： G06F12/08 , G06F13/18 , G06F13/42 , G06F15/16 , G06F15/173 , G06F13/14
CPC分类号： G06F13/4213
摘要： A system and method for transferring bus operations in a processing system which includes at least one processor, the method and system include issuing a plurality of ordered bus operations by the at least one processor, wherein the plurality of bus operations include a first bus operation and a second bus operation, wherein the second bus operation is issued next after the first bus operation is issued. It also determines if a first response for the first bus operation has been received by the at least one processor prior to issuing the second bus operation, wherein the first response indicates that the first bus operation can be transferred. If the first response for the first bus operation is received by the at least one processor prior to issuing the second bus operation, a signal is provided along with the second bus operation, wherein the signal indicates that the processor will not issue a second response for the second bus operation, wherein the second response indicates that the second bus operation should be reissued.
摘要翻译：一种用于在包括至少一个处理器的处理系统中传送总线操作的系统和方法，所述方法和系统包括由所述至少一个处理器发出多个有序总线操作，其中所述多个总线操作包括第一总线操作和第二总线操作，其中在发出第一总线操作之后接下来发出第二总线操作。它还确定在发出第二总线操作之前是否由至少一个处理器接收到第一总线操作的第一响应，其中第一响应指示可以传送第一总线操作。如果在发出第二总线操作之前由至少一个处理器接收到第一总线操作的第一响应，则与第二总线操作一起提供信号，其中该信号指示处理器将不会发出第二响应所述第二总线操作，其中所述第二响应指示应该重新发出所述第二总线操作。

56. 发明授权

US6128707A Adaptive writeback of cache line data in a computer operated with burst mode transfer cycles 失效
标题翻译：在使用突发模式传输周期操作的计算机中缓存线数据的自适应回写
公开(公告)号：US6128707A
公开(公告)日：2000-10-03
申请号：US176721
申请日：1998-10-21
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F12/0879
摘要： System and method for selectively adapting the burst mode writeback from cache to main memory consistent with the extent of a cache line actually modified by the processor and at the granularity of the bus connecting the cache to main memory. A cache controller speculatively reads a cache line with each address issued by this processor. When the address is related to a read cycle of the processor, the data is forwarded to the processor. When the address is related to a write cycle of the processor, the data read from the cache is compared to the write data from the processor to detect changes at a granularity consist with the size of the system data bus. The cache line stored in the cache upon such writing is marked at the granularity of the system data bus with tag bits to indicate which portions have been modified. Upon deallocation, the tag bits stored in the cache directory identify those portions of the cache lines requiring transmission back to main memory as an aspect of the burst writeback operation.
摘要翻译：系统和方法用于根据由处理器实际修改的高速缓存线的范围，以及将高速缓存连接到主存储器的总线的粒度，选择性地将缓存模式回写从高速缓存重新调整到主存储器。高速缓存控制器推测性地读取由该处理器发出的每个地址的高速缓存行。当地址与处理器的读取周期相关时，数据被转发到处理器。当地址与处理器的写入周期相关时，将从高速缓存读取的数据与来自处理器的写入数据进行比较，以以系统数据总线的大小包含的粒度来检测变化。在写入时存储在高速缓存中的高速缓存行以带有标记位的系统数据总线的粒度标记，以指示哪些部分已被修改。在解除分配时，存储在高速缓存目录中的标签位将突发回写操作的一个方面标识出需要传输回主存储器的那些部分。

57. 发明授权

US6101582A Dcbst with icbi mechanism 失效
标题翻译： Dcbst与icbi机制
公开(公告)号：US6101582A
公开(公告)日：2000-08-08
申请号：US24639
申请日：1998-02-17
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0833
摘要： Depending on a processor or instruction mode, a data cache block store (dcbst) or equivalent instruction is treated differently. A coherency maintenance mode for the instruction, in which the instruction is utilized to maintain coherency between bifurcated data and instruction caches, may be entered by setting bits in a processor register or by setting hint bits within the instruction. In the coherency maintenance mode, the instruction both pushes modified data to system memory and invalidates the cache entry in instruction caches. Subsequent instruction cache block invalidate (icbi) or equivalent instructions targeting the same cache location are no-oped when issued by a processor following a data cache block store or equivalent instruction executed in coherency maintenance mode. Execution of the data cache clock store instruction in coherency maintenance mode results in a novel system bus operation being initiated on the system bus. The bus operation directs other devices having bifurcated data and instruction caches to clean the specified cache entry in their data cache to at least the point of instruction/data cache coherency and invalidate the specified cache entry in their instruction cache. When repeatedly employed in sequence to write one or more pages of data to system memory, the mechanism for maintaining coherency saves processor cycles and reduces both address and data bus traffic.
摘要翻译：根据处理器或指令模式，数据高速缓存块存储（dcbst）或等效指令的处理方式不同。可以通过设置处理器寄存器中的位或通过在指令内设置提示位来输入用于指令用于维持分支数据和指令高速缓存之间的一致性的指令的一致性维护模式。在相干维护模式下，指令将修改的数据推送到系统存储器，并使指令高速缓存中的高速缓存条目无效。随后指令高速缓存块无效（icbi）或针对同一高速缓存位置的等效指令在由数据高速缓存块存储器执行的处理器发出或在相干性维护模式下执行的等效指令时不会执行。在一致性维护模式下执行数据高速缓存时钟存储指令导致在系统总线上启动新颖的系统总线操作。总线操作指示具有分叉数据和指令高速缓存的其他设备将其数据高速缓存中的指定高速缓存条目清理为至少指令/数据高速缓存一致性点，并使其指令高速缓存中指定的高速缓存条目无效。当重复按顺序将一个或多个数据页写入系统存储器时，用于维持一致性的机制节省了处理器周期，并减少了地址和数据总线流量。

58. 发明授权

US5937172A Apparatus and method of layering cache and architectural specific functions to permit generic interface definition 失效
公开(公告)号：US5937172A
公开(公告)日：1999-08-10
申请号：US839445
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis , Derek Edward Williams
IPC分类号： G06F12/08 , G06F13/16 , G06F13/00
CPC分类号： G06F12/0897 , G06F12/0893 , G06F13/1694
摘要： Cache and architectural functions within a cache controller are layered and provided with generic interfaces. Layering cache and architectural operations allows the definition of generic interfaces between controller logic and bus interface units within the controller. The generic interfaces are defined by extracting the essence of supported operations into a generic protocol. The interfaces themselves may be pulsed or held interfaces, depending on the character of the operation. Because the controller logic is isolated from the specific protocols required by a processor or bus architecture, the design may be directly transferred to new controllers for different protocols or processors by modifying the bus interface units appropriately.

59. 发明授权

US5924121A Adaptive writeback of cache line data in a computer operated with burst mode transfer cycles 失效
公开(公告)号：US5924121A
公开(公告)日：1999-07-13
申请号：US771995
申请日：1996-12-23
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0804 , G06F12/0879
摘要： System and method for selectively adapting the burst mode writeback from cache to main memory consistent with the extent of a cache line actually modified by the processor and at the granularity of the bus connecting the cache to main memory. A cache controller speculatively reads a cache line with each address issued by this processor. When the address is related to a read cycle of the processor, the data is forwarded to the processor. When the address is related to a write cycle of the processor, the data read from the cache is compared to the write data from the processor to detect changes at a granularity consist with the size of the system data bus. The cache line stored in the cache upon such writing is marked at the granularity of the system data bus with tag bits to indicate which portions have been modified. Upon deallocation, the tag bits stored in the cache directory identify those portions of the cache lines requiring transmission back to main memory as an aspect of the burst writeback operation.

60. 发明授权

US5909698A Cache block store instruction operations where cache coherency is achieved without writing all the way back to main memory 失效
标题翻译：高速缓存块存储指令操作，其中实现高速缓存一致性，而不需要一直返回到主存储器
公开(公告)号：US5909698A
公开(公告)日：1999-06-01
申请号：US818845
申请日：1997-03-17
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0804 , G06F12/0808
摘要： In a processor employing separate instruction and data caches in at least one cache hierarchy level, a cache control instruction forces modified data within the separate data cache to a lower cache hierarchy level. An existing cache access attribute is employed to distinguish between occasions when the data must be written all the way to main memory and occasions when the data need only be written to a cache hierarchy level from which fetches are made to the separate instruction cache. Thus, the separate instruction and data caches may be made coherent without writing all the way to main memory, but the ability to write modified data to main memory whenever necessary is preserved. Utilization of the existing attribute avoids increasing processor complexity and/or resources.
摘要翻译：在处理器中，在至少一个高速缓存层级中使用单独的指令和数据高速缓存，高速缓存控制指令强制单独的数据高速缓存内的修改的数据到较低的高速缓存层级。采用现有的高速缓存访问属性来区分当数据必须一直写入主存储器的情况，并且当数据只需要写入到从其提取到高速缓存层级的高速缓存层级时。因此，分离的指令和数据高速缓存可以一致地进行，而不必一直写入主存储器，而是保存在必要时将修改的数据写入主存储器的能力。现有属性的利用避免了增加的处理器复杂性和/或资源。

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