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51. 发明授权

US5953283A Multi-port SRAM with reduced access requirements 失效
标题翻译：多端口SRAM，具有降低的访问要求
公开(公告)号：US5953283A
公开(公告)日：1999-09-14
申请号：US127332
申请日：1998-07-31
申请人： David Meltzer , Joel Abraham Silberman
发明人： David Meltzer , Joel Abraham Silberman
IPC分类号： G11C13/00 , G11C8/16 , G11C8/00
CPC分类号： G11C8/16
摘要： An improved multi-port SRAM that requires fewer access means, bit lines and sense amplifiers for multiport access. The number of access means can be reduced to ceiling (log.sub.2 B), where B is the number of access ports. The number of bit line sense amplifiers needed to achieve multiport access can also be reduced by the same factor as the number of access devices per cell. An efficient means is provided to select a correct access device among the plurality of access devices within the array and to condition a correct multiplexer select signal to couple a correct bit as specified by the port read address to the port read output. The access device selection can be implemented by a tree representation of all possible bit line and multiplexer select combinations. The tree representation can be implemented in hardware or software. Examples are provided of both a circuit and a tree walking algorithm that gives priority by port order. Alternatively, logic to select the bit lines and controls could give priority in bit order. In either case, examples are provided for modifying the strict priority order to avoid conflicts and obtain a correct solution.
摘要翻译：一种改进的多端口SRAM，其需要较少的访问方式，位线和用于多端口访问的读出放大器。访问方式的数量可以减少到上限（log2B），其中B是接入端口的数量。实现多端口访问所需的位线读出放大器的数量也可以减少与每个单元的访问设备数量相同的因素。提供了一种有效的方法来选择阵列内的多个访问设备中的正确的访问设备，并且调整正确的多路复用器选择信号以将由端口读取地址指定的正确位耦合到端口读取输出。访问设备选择可以通过所有可能的位线和多路复用器选择组合的树形表示来实现。树表示可以在硬件或软件中实现。提供了通过端口顺序优先的电路和树行走算法的示例。或者，选择位线和控制的逻辑可以按位顺序给出优先级。在这两种情况下，都提供了修改严格优先顺序以避免冲突并获得正确解决方案的示例。

52. 发明授权

US08380964B2 Processor including age tracking of issue queue instructions 有权
标题翻译：处理器包括发布队列指令的年龄跟踪
公开(公告)号：US08380964B2
公开(公告)日：2013-02-19
申请号：US12417878
申请日：2009-04-03
申请人： James Wilson Bishop , Mary Douglass Brown , Jeffrey Carl Brownscheidle , Robert Allen Cordes , Maureen Anne Delaney , Jafar Nahidi , Dung Quoc Nguyen , Joel Abraham Silberman
发明人： James Wilson Bishop , Mary Douglass Brown , Jeffrey Carl Brownscheidle , Robert Allen Cordes , Maureen Anne Delaney , Jafar Nahidi , Dung Quoc Nguyen , Joel Abraham Silberman
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40
CPC分类号： G06F9/3855
摘要： An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store IDS. The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update. The issue queue may selectively clock a row and a column of cells of the age matrix that correspond to a dispatched instruction's queue position while leaving other cells unclocked to conserve power.
摘要翻译：信息处理系统包括具有可执行年龄跟踪操作的指令发布队列（IQ）的处理器。问题队列IQ维护或存储可能在内部数据存储IDS中发出无序的指令。 IDS组织了队列位置（QPOS）寻址布置中的指令。 IQ的年龄矩阵维护IDS内的这些指令的相对指令老化记录。年龄矩阵更新锁存器或其他存储单元数据，以反映在IQ调度操作期间IDS指令年龄的变化。在发送一个或多个指令期间，年龄矩阵可以仅更新需要数据改变的锁存器以反映改变的IDS指令年龄。年龄矩阵采用行和列数据和时钟控制来单独更新需要更新的锁存器。问题队列可以选择性地对与分派指令的队列位置相对应的年龄矩阵的一行和一列单元进行计时，同时使其他单元不被锁定以节省功率。

53. 发明申请

US20110185159A1 PROCESSOR INCLUDING AGE TRACKING OF ISSUE QUEUE INSTRUCTIONS 有权
标题翻译：处理器包括年龄跟踪问题的指令
公开(公告)号：US20110185159A1
公开(公告)日：2011-07-28
申请号：US12417878
申请日：2009-04-03
申请人： James Wilson Bishop , Mary Douglass Brown , Jeffrey Carl Brownscheidle , Robert Allen Cordes , Maureen Anne Delaney , Jafar Nahidi , Dung Quoc Nguyen , Joel Abraham Silberman
发明人： James Wilson Bishop , Mary Douglass Brown , Jeffrey Carl Brownscheidle , Robert Allen Cordes , Maureen Anne Delaney , Jafar Nahidi , Dung Quoc Nguyen , Joel Abraham Silberman
IPC分类号： G06F9/312
CPC分类号： G06F9/3855
摘要： An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store IDS. The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update. The issue queue may selectively clock a row and a column of cells of the age matrix that correspond to a dispatched instruction's queue position while leaving other cells unclocked to conserve power.
摘要翻译：信息处理系统包括具有可执行年龄跟踪操作的指令发布队列（IQ）的处理器。问题队列IQ维护或存储可能在内部数据存储IDS中发出无序的指令。 IDS组织了队列位置（QPOS）寻址布置中的指令。 IQ的年龄矩阵维护IDS内的这些指令的相对指令老化记录。年龄矩阵更新锁存器或其他存储单元数据，以反映在IQ调度操作期间IDS指令年龄的变化。在发送一个或多个指令期间，年龄矩阵可以仅更新需要数据改变的锁存器以反映改变的IDS指令年龄。年龄矩阵采用行和列数据和时钟控制来单独更新需要更新的锁存器。问题队列可以选择性地对与分派指令的队列位置相对应的年龄矩阵的一行和一列单元进行计时，同时使其他单元不被锁定以节省功率。

54. 发明授权

US06816396B2 Apparatus for detecting multiple hits in a CAMRAM memory array 失效
标题翻译：用于检测CAMRAM存储器阵列中的多个命中的装置
公开(公告)号：US06816396B2
公开(公告)日：2004-11-09
申请号：US10405736
申请日：2003-04-01
申请人： Chiaming Chai , Jeffrey Herbert Fischer , Michael Thaithanh Phan , Joel Abraham Silberman
发明人： Chiaming Chai , Jeffrey Herbert Fischer , Michael Thaithanh Phan , Joel Abraham Silberman
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： A CAMRAM capable of detecting multiple hit is disclosed. The CAMRAM includes a random address memory, a content-addressable memory, a set of index address lines and a set of multiple-hit detection address lines. The index address lines and the multiple-hit detection address lines are complementarily connected to a set of matchlines via transistors. Coupled to the index address lines and the multiple-hit detection address lines, a comparator circuit is capable of outputting a multi-hit signal when more than one of the matchlines are turned on simultaneously during an address comparison operation.
摘要翻译：公开了一种能够检测多次命中的CAMRAM。 CAMRAM包括随机地址存储器，内容寻址存储器，一组索引地址线和一组多命中检测地址线。索引地址线和多命中检测地址线通过晶体管互补地连接到一组匹配线。耦合到索引地址线和多命中检测地址线，当地址比较操作期间多于一条匹配线同时导通时，比较器电路能够输出多命中信号。

55. 发明授权

US06604191B1 Method and apparatus for accelerating instruction fetching for a processor 失效
标题翻译：用于加速处理器的指令获取的方法和装置
公开(公告)号：US06604191B1
公开(公告)日：2003-08-05
申请号：US09498932
申请日：2000-02-04
申请人： Brian King Flacks , David Meltzer , Joel Abraham Silberman
发明人： Brian King Flacks , David Meltzer , Joel Abraham Silberman
IPC分类号： G06F1200
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/3804 , G06F12/0875
摘要： An instruction fetching system (and/or architecture) which may be utilized by a high-frequency short-pipeline microprocessor, for efficient fetching of both in-line and target instructions. The system contains an instruction fetching unit (IFU), having a control logic and associated components for controlling a specially designed instruction cache (I-cache). The I-cache is a sum-address cache, i.e., it receives two address inputs, which compiled by a decoder to provide the address of the line of instructions desired fetch. The I-cache is designed with an array of cache lines that can contain 32 instructions, and three buffers that each have a capacity of 32 instructions. The three buffers include a Predicted (PRED) buffer that holds the instructions which are currently being executed, a NEXT buffer that holds the instructions which are to be executed after the instructions in the PRED buffer, and an ALT buffer that holds the alternate set of instructions when a branch is predicted taken/not taken and is utilized along with the PRED buffer to permit branch target retrieval within I-cache prior to a prediction.
摘要翻译：可以由高频短流水线微处理器利用的指令获取系统（和/或架构），用于有效地提取在线和目标指令。该系统包含指令提取单元（IFU），具有用于控制专门设计的指令高速缓存（I-cache）的控制逻辑和相关组件。 I缓存是和地址高速缓存，即它接收两个地址输入，其由解码器编译以提供期望提取的指令行的地址。 I缓存设计有可以包含32个指令的高速缓存行数组，每个缓冲区的容量为32个指令。三个缓冲器包括保存当前正在执行的指令的预测（PRED）缓冲器，保存在PRED缓冲器中的指令之后要执行的指令的NEXT缓冲器，以及保存该替换组的ALT缓冲器预测采取/未采取分支时使用指令，并与PRED缓冲区一起使用，以允许在预测之前在I缓存中进行分支目标检索。

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