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1. 发明授权

US06604191B1 Method and apparatus for accelerating instruction fetching for a processor 失效
标题翻译：用于加速处理器的指令获取的方法和装置
公开(公告)号：US06604191B1
公开(公告)日：2003-08-05
申请号：US09498932
申请日：2000-02-04
申请人： Brian King Flacks , David Meltzer , Joel Abraham Silberman
发明人： Brian King Flacks , David Meltzer , Joel Abraham Silberman
IPC分类号： G06F1200
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/3804 , G06F12/0875
摘要： An instruction fetching system (and/or architecture) which may be utilized by a high-frequency short-pipeline microprocessor, for efficient fetching of both in-line and target instructions. The system contains an instruction fetching unit (IFU), having a control logic and associated components for controlling a specially designed instruction cache (I-cache). The I-cache is a sum-address cache, i.e., it receives two address inputs, which compiled by a decoder to provide the address of the line of instructions desired fetch. The I-cache is designed with an array of cache lines that can contain 32 instructions, and three buffers that each have a capacity of 32 instructions. The three buffers include a Predicted (PRED) buffer that holds the instructions which are currently being executed, a NEXT buffer that holds the instructions which are to be executed after the instructions in the PRED buffer, and an ALT buffer that holds the alternate set of instructions when a branch is predicted taken/not taken and is utilized along with the PRED buffer to permit branch target retrieval within I-cache prior to a prediction.
摘要翻译：可以由高频短流水线微处理器利用的指令获取系统（和/或架构），用于有效地提取在线和目标指令。该系统包含指令提取单元（IFU），具有用于控制专门设计的指令高速缓存（I-cache）的控制逻辑和相关组件。 I缓存是和地址高速缓存，即它接收两个地址输入，其由解码器编译以提供期望提取的指令行的地址。 I缓存设计有可以包含32个指令的高速缓存行数组，每个缓冲区的容量为32个指令。三个缓冲器包括保存当前正在执行的指令的预测（PRED）缓冲器，保存在PRED缓冲器中的指令之后要执行的指令的NEXT缓冲器，以及保存该替换组的ALT缓冲器预测采取/未采取分支时使用指令，并与PRED缓冲区一起使用，以允许在预测之前在I缓存中进行分支目标检索。

2. 发明授权

US6138208A Multiple level cache memory with overlapped L1 and L2 memory access 失效
标题翻译：具有重叠的L1和L2存储器访问的多级高速缓存
公开(公告)号：US6138208A
公开(公告)日：2000-10-24
申请号：US59000
申请日：1998-04-13
申请人： Sang Hoo Dhong , Harm Peter Hofstee , David Meltzer , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , David Meltzer , Joel Abraham Silberman
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0884
摘要： A method of providing simultaneous, or overlapped, access to multiple cache levels to reduce the latency penalty for a higher level cache miss. A request for a value (data or instruction) is issued by the processor, and is forwarded to the lower level of the cache before determining whether a cache miss of the value has occurred at the higher level of the cache. In the embodiment wherein the lower level is an L2 cache, the L2 cache may supply the value directly to the processor. Address decoders are operated in parallel at the higher level of the cache to satisfy a plurality of simultaneous memory requests. One of the addresses (selected by priority logic based on hit/miss information from the higher level of the cache) is gated by a multiplexer to a plurality of memory array word line drivers of the lower level of the cache. Some bits in the address which do not require virtual-to-real translation can be immediately decoded.
摘要翻译：提供对多个高速缓存级别的同时或重叠访问以减少对于较高级别的高速缓存未命中的延迟损失的方法。处理器发出值（数据或指令）的请求，并且在确定高速缓存的较高级别是否发生了该值的高速缓存未命中之前被转发到高速缓存的较低级。在其中较低级别是L2高速缓存的实施例中，L2高速缓存可以将该值直接提供给处理器。地址解码器在高速缓存的较高级并行操作以满足多个同时的存储器请求。其中一个地址（由基于来自高速缓存的较高级别的命中/未命中信息的优先级逻辑选择）由多路复用器选通到高速缓存的较低级的多个存储器阵列字线驱动器。可以立即解码地址中的一些不需要虚拟到实际转换的位。

3. 发明授权

US6065110A Method and apparatus for loading an instruction buffer of a processor capable of out-of-order instruction issue 失效
标题翻译：用于加载能够无序指令发出的处理器的指令缓冲器的方法和装置
公开(公告)号：US6065110A
公开(公告)日：2000-05-16
申请号：US20631
申请日：1998-02-09
申请人： David Meltzer , Joel Abraham Silberman
发明人： David Meltzer , Joel Abraham Silberman
IPC分类号： G06F12/08 , G06F9/32 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/3836 , G06F9/3838 , G06F9/384
摘要： A method and apparatus for loading an instruction buffer of a processor capable of out-of-order instruction issue are disclosed. The processor capable of out-of-order instruction issue includes an instruction cache having multiple cache lines. The instruction cache is coupled to an instruction buffer via a multiplexor. The instruction buffer includes several slots, and these slots are sequentially filled by instructions from the instruction cache under the supervision of the multiplexor. The slot in which the first instruction resides is dictated by a fetch address. Any empty slot in the instruction buffer will be filled with instructions from a subsequent cache line of the instruction cache if the first instruction does not reside in the first slot of the instruction buffer.
摘要翻译：公开了一种用于加载能够无序指令发布的处理器的指令缓冲器的方法和装置。能够无序指令的处理器包括具有多个高速缓存行的指令高速缓存。指令高速缓存通过多路复用器耦合到指令缓冲器。指令缓冲器包括几个时隙，并且这些时隙由多路复用器的监督下的来自指令高速缓存的指令顺序地填充。第一条指令所在的时隙由取出地址决定。如果第一条指令不在指令缓冲区的第一个时隙中，指令缓冲区中的任何空的槽将被来自指令高速缓存的后续高速缓存行的指令填充。

4. 发明授权

US6038659A Method for using read-only memory to generate controls for microprocessor 失效
标题翻译：使用只读存储器生成微处理器控制的方法
公开(公告)号：US6038659A
公开(公告)日：2000-03-14
申请号：US968120
申请日：1997-11-12
申请人： Sang Hoo Dhong , Harm Peter Hofstee , David Meltzer , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , David Meltzer , Joel Abraham Silberman
IPC分类号： G06F9/30 , G06F9/318
CPC分类号： G06F9/382 , G06F9/30145 , G06F9/30196
摘要： A circuit for generating control signals used in a microprocessor has a storage array, such as a read-only memory (ROM) array, which contains a plurality of predefined logic patterns. An entry of the ROM array is selected, such as by the use of an address decoder, to choose a specific pattern, and the specific pattern is then modified based on a dynamic signal to generate an output control signal. The microprocessor may further predecode a base instruction using operation and operand source bits to yield a predecoded instruction having an address field whose value corresponds to the specific pattern. The dynamic signal can be based on whether an operand should be forwarded from a microprocessor component, and the specific pattern is then equivalent to a value for control signals required to execute an instruction when assuming that the operand should not be forwarded. Special control states can also be implemented, such as stall, halt, or scan data, through the use of particular code points in the ROM.
摘要翻译：用于产生在微处理器中使用的控制信号的电路具有存储阵列，诸如只读存储器（ROM）阵列，其包含多个预定逻辑模式。选择ROM阵列的入口，例如通过使用地址解码器来选择特定模式，然后基于动态信号修改特定模式以产生输出控制信号。微处理器可以进一步使用操作和源位来对基本指令进行预解码，以产生具有对应于特定模式的地址字段的预解码指令。动态信号可以基于操作数是否应该从微处理器组件转发，并且特定模式然后等于假设不应该转发操作数时执行指令所需的控制信号的值。还可以通过使用ROM中的特定代码点来实现特殊控制状态，例如停止，停止或扫描数据。

5. 发明授权

US5953283A Multi-port SRAM with reduced access requirements 失效
标题翻译：多端口SRAM，具有降低的访问要求
公开(公告)号：US5953283A
公开(公告)日：1999-09-14
申请号：US127332
申请日：1998-07-31
申请人： David Meltzer , Joel Abraham Silberman
发明人： David Meltzer , Joel Abraham Silberman
IPC分类号： G11C13/00 , G11C8/16 , G11C8/00
CPC分类号： G11C8/16
摘要： An improved multi-port SRAM that requires fewer access means, bit lines and sense amplifiers for multiport access. The number of access means can be reduced to ceiling (log.sub.2 B), where B is the number of access ports. The number of bit line sense amplifiers needed to achieve multiport access can also be reduced by the same factor as the number of access devices per cell. An efficient means is provided to select a correct access device among the plurality of access devices within the array and to condition a correct multiplexer select signal to couple a correct bit as specified by the port read address to the port read output. The access device selection can be implemented by a tree representation of all possible bit line and multiplexer select combinations. The tree representation can be implemented in hardware or software. Examples are provided of both a circuit and a tree walking algorithm that gives priority by port order. Alternatively, logic to select the bit lines and controls could give priority in bit order. In either case, examples are provided for modifying the strict priority order to avoid conflicts and obtain a correct solution.
摘要翻译：一种改进的多端口SRAM，其需要较少的访问方式，位线和用于多端口访问的读出放大器。访问方式的数量可以减少到上限（log2B），其中B是接入端口的数量。实现多端口访问所需的位线读出放大器的数量也可以减少与每个单元的访问设备数量相同的因素。提供了一种有效的方法来选择阵列内的多个访问设备中的正确的访问设备，并且调整正确的多路复用器选择信号以将由端口读取地址指定的正确位耦合到端口读取输出。访问设备选择可以通过所有可能的位线和多路复用器选择组合的树形表示来实现。树表示可以在硬件或软件中实现。提供了通过端口顺序优先的电路和树行走算法的示例。或者，选择位线和控制的逻辑可以按位顺序给出优先级。在这两种情况下，都提供了修改严格优先顺序以避免冲突并获得正确解决方案的示例。

6. 发明授权

US07885359B2 Sampling demodulator for amplitude shift keying (ASK) radio receiver 有权
标题翻译：用于幅移键控（ASK）无线电接收机的采样解调器
公开(公告)号：US07885359B2
公开(公告)日：2011-02-08
申请号：US11839347
申请日：2007-08-15
申请人： David Meltzer
发明人： David Meltzer
IPC分类号： H03D1/24
CPC分类号： H04L27/06 , H04L7/0331 , H04L25/068
摘要： A method, algorithm, circuits, and/or systems for amplitude shift keying (ASK) modulation are disclosed. In one embodiment, a sampling demodulator includes a comparator configured to compare an ASK modulated input to a predetermined voltage level and provide a comparison result, a pulse stretcher with a sampler configured to sample the comparison result a plurality of times for each of a plurality of cycles of the ASK modulated input to generate a bit stream and digital logic configured to determine a value for each data bit in the ASK modulated input from the bit stream, and a digital filter configured to filter an output of the digital logic, thereby providing a demodulated signal.
摘要翻译：公开了一种用于幅移键控（ASK）调制的方法，算法，电路和/或系统。在一个实施例中，采样解调器包括比较器，其被配置为将ASK调制输入与预定电压电平进行比较并提供比较结果;脉冲展宽器，其具有被配置为针对多个 ASK调制输入的周期以产生比特流，以及数字逻辑，被配置为确定来自比特流的ASK调制输入中的每个数据比特的值，以及数字滤波器，其被配置为对数字逻辑的输出进行滤波，从而提供解调信号。

7. 发明申请

US20080267313A1 Dual Demodulation Mode AM Radio 失效
标题翻译：双解调模式AM收音机
公开(公告)号：US20080267313A1
公开(公告)日：2008-10-30
申请号：US11740159
申请日：2007-04-25
申请人： David Meltzer , Gregory A. Blum , Muralikumar A. Padaparambil
发明人： David Meltzer , Gregory A. Blum , Muralikumar A. Padaparambil
IPC分类号： H03C5/00
CPC分类号： H03D1/22
摘要： Apparatuses and methods for receiving an amplitude modulated signal in one of two modes depending on the quality of the received signal. In a first mode, the amplitude modulated signal is converted directly to a baseband signal. In a second mode, the amplitude modulated signal is converted to an intermediate frequency signal. The present invention advantageously combines direct conversion and image-rejection heterodyne receiver topologies with a relatively large degree of component reuse and relatively few additional components.
摘要翻译：根据接收信号的质量，以两种模式之一接收幅度调制信号的装置和方法。在第一模式中，幅度调制信号被直接转换为基带信号。在第二模式中，幅度调制信号被转换成中频信号。本发明有利地将直接转换和图像抑制外差接收器拓扑与相对较大程度的组件重用和相对较少的附加组件相结合。

8. 发明授权

US07268635B2 Circuits for voltage-controlled ring oscillators and method of generating a periodic signal 失效
标题翻译：用于压控环形振荡器的电路和产生周期信号的方法
公开(公告)号：US07268635B2
公开(公告)日：2007-09-11
申请号：US11119311
申请日：2005-04-29
申请人： David Meltzer
发明人： David Meltzer
IPC分类号： H03B5/24
CPC分类号： H03K3/0315
摘要： Circuits and methods and for generating oscillator outputs using standard integrated circuit components. The basic circuit generally includes two inverters and a variable capacitor to configure a delay of the circuit input and/or output. The oscillator circuit generally includes a plurality of inverter circuits, at least one of which uses a variable capacitor to adjust a delay between stages, and thereby adjust a frequency of oscillation. Thus, the oscillator outputs may be tuned using a single control voltage. The method generally includes the steps of (1) applying an operating voltage to a ring oscillator comprising a plurality of stages; and (2) applying a control voltage to a variable capacitor coupled to a node between at least two of those stages. The circuits have particular advantage in quadrature oscillators, and may be easily implemented using widely available CMOS technology.
摘要翻译：电路和方法，并使用标准集成电路组件产生振荡器输出。基本电路通常包括两个反相器和可变电容器，以配置电路输入和/或输出的延迟。振荡电路通常包括多个反相器电路，其中至少一个使用可变电容器来调整级之间的延迟，从而调节振荡频率。因此，可以使用单个控制电压来调谐振荡器输出。该方法通常包括以下步骤：（1）将工作电压施加到包括多个级的环形振荡器; 以及（2）将控制电压施加到耦合到这些级中的至少两个级之间的节点的可变电容器。这些电路在正交振荡器中具有特别的优点，并且可以使用广泛可用的CMOS技术容易地实现。

9. 发明授权

US07224180B2 Methods and systems for rise-time improvements in differential signal outputs 失效
标题翻译：差分信号输出上升时间的方法和系统
公开(公告)号：US07224180B2
公开(公告)日：2007-05-29
申请号：US10991724
申请日：2004-11-18
申请人： Michael Hargrove , David Meltzer
发明人： Michael Hargrove , David Meltzer
IPC分类号： H03K17/16 , H03H7/38 , H01P5/12
CPC分类号： H04L25/0278 , H01L23/60 , H01L23/645 , H01L24/48 , H01L24/49 , H01L27/0248 , H01L2223/6611 , H01L2224/48091 , H01L2224/48463 , H01L2224/4911 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01057 , H01L2924/01082 , H01L2924/14 , H01L2924/19042 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H03K19/00323 , H03K19/013 , H04L25/0272 , H04L25/028 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A method for maintaining signal integrity of a differential output signal generated from a differential driver is disclosed. The method includes receiving the differential output signal from the differential driver. Once received, the method includes tuning the differential output signal by exposing the differential output signal to an inductance. The inductance is configured to reduce signal mismatch between complementary signals of the differential output signal. The signal mismatch is a result of having each of the complementary signals exposed to different capacitive loading. A device and system is also provided, which include integrating an inductor between the output leads of a differential driver. The inductor is sized for the particular frequency of operation, and the inductor provides an inductance that assists in eliminating mismatch between the complementary signals of the differential output. A reduction and/or elimination of the mismatch will assist in improving the rise-time of the differential signals.
摘要翻译：公开了一种用于维持从差分驱动器产生的差分输出信号的信号完整性的方法。该方法包括从差分驱动器接收差分输出信号。一旦接收到，该方法包括通过将差分输出信号暴露于电感来调谐差分输出信号。电感被配置为减小差分输出信号的互补信号之间的信号失配。信号失配是使每个互补信号暴露于不同的电容负载的结果。还提供了一种设备和系统，其包括在差分驱动器的输出引线之间集成电感器。电感器的尺寸适用于特定的工作频率，电感器提供的电感有助于消除差分输出的互补信号之间的失配。减少和/或消除失配将有助于改善差分信号的上升时间。

10. 发明申请

US20060250198A1 Integrated resonator structure and methods for its manufacture and use 有权
标题翻译：集成谐振器结构及其制造和使用的方法
公开(公告)号：US20060250198A1
公开(公告)日：2006-11-09
申请号：US11125378
申请日：2005-05-09
申请人： David Meltzer , Michael Hargrove
发明人： David Meltzer , Michael Hargrove
IPC分类号： H03H7/01
CPC分类号： H01L28/10 , H01F17/0013 , H03H2001/0064
摘要： An improved integrated LC resonator and methods for making and using the same are disclosed. The resonator includes (i) a first capacitor plate; (ii) an inductor over and in electrical communication with the first capacitor plate; and (iii) a second capacitor plate over and in electrical communication with the inductor. The method of making includes sequentially forming a first capacitor plate, a first dielectric layer thereon, a first via and an inductor, a second dielectric layer on the inductor, and a second via and a second capacitor plate. Each of the capacitor plates and the inductor are generally formed in different integrated circuit layers (for example, different metallization layers). Embodiments of the present invention can advantageously provide an integrated LC resonator tank having: (i) relatively high Q by reducing or minimizing parasitic effects; and (ii) relatively high shielding from the semiconductor substrate.
摘要翻译：公开了一种改进的集成LC谐振器及其制造和使用方法。谐振器包括（i）第一电容器板; （ii）与所述第一电容器板电连接的电感器; 和（iii）在电感器上并与电感器电连通的第二电容器板。制造方法包括依次形成第一电容器板，第一电介质层，第一通孔和电感器，电感器上的第二电介质层，以及第二通孔和第二电容器板。每个电容器板和电感器通常形成在不同的集成电路层（例如，不同的金属化层）中。本发明的实施例可以有利地提供一种集成的LC谐振器箱，其具有：（i）通过减小或最小化寄生效应来实现相对较高的Q; 和（ii）与半导体衬底相对较高的屏蔽。

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