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51. 发明授权

US5702976A Shallow trench isolation using low dielectric constant insulator 失效
标题翻译：使用低介电常数绝缘子的浅沟槽隔离
公开(公告)号：US5702976A
公开(公告)日：1997-12-30
申请号：US547620
申请日：1995-10-24
申请人： Klaus F. Schuegraf , Aftab Ahmad
发明人： Klaus F. Schuegraf , Aftab Ahmad
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced wench depth helps to eliminate the formation of voids during the trench refill process and provides for greater planarity in the final isolation structure. Effective device isolation is achieved with a reduced trench depth by utilizing refilling dielectric materials having low dielectric constant.
摘要翻译：公开了一种浅沟槽隔离，其中沟槽深度减小到超过现有技术工艺中所达到的深度。减小的深度深度有助于消除在沟槽再填充过程期间形成空隙，并且在最终隔离结构中提供更大的平坦度。通过利用具有低介电常数的再填充介电材料，通过减小沟槽深度实现有效的器件隔离。

52. 发明授权

US5668037A Method of forming a resistor and integrated circuitry having a resistor construction 失效
标题翻译：形成电阻器的方法和具有电阻器结构的集成电路
公开(公告)号：US5668037A
公开(公告)日：1997-09-16
申请号：US679705
申请日：1996-07-11
申请人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
发明人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
IPC分类号： H01L21/02 , H01L27/06 , H01L27/08 , H01L21/70
CPC分类号： H01L28/20 , H01L27/0629 , H01L27/0802 , Y10S148/136
摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.
摘要翻译：从半导体材料形成电阻器的方法包括：a）提供衬底; b）在衬底上提供半导体材料层; c）在半导体材料层中提供一对开口; d）用导电材料堵塞所述一对开口，以在所述半导体材料内限定一对导电柱，所述一对支柱具有在其间延伸的半导体材料以提供电阻器结构; 以及e）为每个导电柱提供导电节点。结合电阻器结构的集成电路包括：i）半导体材料层; ii）设置在半导体材料层内的一对导电柱，所述一对柱彼此分离，从而具有在其间延伸的半导体材料的质量; 以及iii）与每个相应的导电柱电连接的导电节点。或者，使用不同的浓度扩散区域在半导体衬底内提供电阻器。

53. 发明授权

US5382533A Method of manufacturing small geometry MOS field-effect transistors having improved barrier layer to hot electron injection 失效
标题翻译：制造具有改进的阻挡层到热电子注入的小几何MOS场效应晶体管的方法
公开(公告)号：US5382533A
公开(公告)日：1995-01-17
申请号：US79322
申请日：1993-06-18
申请人： Aftab Ahmad , Randhir P. S. Thakur
发明人： Aftab Ahmad , Randhir P. S. Thakur
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51 , H01L21/265
CPC分类号： H01L29/512 , H01L21/28176 , H01L29/518 , H01L29/6659 , Y10S438/91
摘要： A process for suppressing hot electrons in sub half micron MOS devices wherein a gate oxide and a gate electrode are formed on the surface of a silicon substrate and source and drain regions are ion implanted into the silicon substrate using the gate electrode as a mask. The process includes forming a layer of silicon dioxide over the gate electrode and over the source and drain regions of the substrate, and then introducing a barrier layer forming element into the layer of silicon dioxide to form a thin barrier region to hot electrons at the interface between the silicon substrate and the silicon dioxide. In a preferred embodiment of the invention, nitrogen is introduced into the silicon dioxide by heating the wafer in a rapid thermal processor and in the presence of a nitrogen containing gas at an elevated temperature for a predetermined time. The nitrogen containing gas may be selected from the group consisting of nitrogen trifluoride, ammonia and nitrous oxide. In an alternative embodiment of the invention, fluorine atoms are introduced into the silicon substrate either as the sole barrier layer forming element (silicon fluoride) or prior to the formation of the thin silicon nitride region. The fluorine atoms form good strong silicon-fluorine bonds in the silicon substrate and thereby further enhance the hot electron suppression. In a third embodiment, nitrogen and fluorine are reacted in a rapid thermal processor to form a composite barrier layer of Si.sub.3 N.sub.4 and SF.
摘要翻译：用于抑制半微米MOS器件中的热电子的方法，其中在硅衬底的表面上形成栅极氧化物和栅电极，并且使用栅电极作为掩模将源极和漏极区域离子注入到硅衬底中。该方法包括在栅电极上方和衬底的源极和漏极区上形成二氧化硅层，然后将阻挡层形成元件引入到二氧化硅层中以在界面处形成热电子的薄屏障区在硅衬底和二氧化硅之间。在本发明的一个优选实施方案中，通过在快速热处理器中加热晶片并且在含氮气体存在下在升高的温度下将氮气引入二氧化硅中达预定时间。含氮气体可以选自三氟化氮，氨和一氧化二氮。在本发明的替代实施例中，氟原子作为唯一的阻挡层形成元件（氟化硅）或在形成薄氮化硅区之前被引入到硅衬底中。氟原子在硅衬底中形成良好的强硅 - 氟键，从而进一步增强热电子抑制。在第三实施例中，氮和氟在快速热处理器中反应以形成Si 3 N 4和SF的复合势垒层。

54. 发明授权

US5208176A Method of fabricating an enhanced dynamic random access memory (DRAM) cell capacitor using multiple polysilicon texturization 失效
标题翻译：使用多个多晶硅纹理化制造增强型动态随机存取存储器（DRAM）单元电容器的方法
公开(公告)号：US5208176A
公开(公告)日：1993-05-04
申请号：US603528
申请日：1990-10-25
申请人： Aftab Ahmad , Pierre C. Fazan , Ruojia Lee
发明人： Aftab Ahmad , Pierre C. Fazan , Ruojia Lee
IPC分类号： H01L21/308 , H01L21/32 , H01L21/334
CPC分类号： H01L29/66181 , H01L21/3081 , H01L21/32 , Y10S438/964
摘要： A DRAM cell having a doped monocrystalline silicon substrate for the cell's lower capacitor plate whose surface has been texturized multiple times to enhance cell capacitance. After texturization, a thin silicon nitride layer is deposited on top of the texturized substrate, followed by the deposition of a poly layer, which functions as the cell's upper, or field, capacitor plate. The nitride layer, conformal and thin compared to the surface texture of the mono substrate, transfers the texture of the substrate to the cell plate layer. The effective capacitor plate area is substantially augmented, resulting in a cell capacitance increase of at least approximately fifty percent compared to a conventional planar cell utilizing identical wafer area. The substrate is texturized by texturizing a thin polycrystalline silicon (poly) starter layer that has been deposited on top of the substrate by using an anisotropic etch or wet oxidation step, and then allowing the poly starter layer to be consumed, transferring the texture created on the poly starter layer to the underlying substrate. By subjecting the starter layer to either an etch or an oxidation step, atoms at the grain boundaries of the starter layer react more rapidly, thus establishing the texturization pattern. Once established, the starter layer's texturization pattern is transferred to the monocrystalline silicon surface by either etching or oxidizing the starter layer. Performing this texturization process multiple times produces greater texturization due to the consumption of the successive poly starter layers along their respective, uniquely superimposed grain boundaries.
摘要翻译：具有用于电池的下电容器板的掺杂单晶硅衬底的DRAM单元，其表面已被多次构造以增强单元电容。在纹理化之后，将薄的氮化硅层沉积在纹理化衬底的顶部上，随后沉积多层，其用作电池的上部或场域电容器板。与单基板的表面纹理相比，保形和薄的氮化物层将基板的纹理转移到单元板层。与使用相同晶片面积的常规平面单元相比，有效电容器板面积基本上增加，导致电池电容增加至少约百分之五十。通过使用各向异性蚀刻或湿氧化步骤，已经沉积在衬底的顶部上的薄多晶硅（多晶）起始层进行纹理化，然后允许多晶硅起始层被消耗，转移在多晶硅起始层到底层基板。通过使起始层进行蚀刻或氧化步骤，起始层的晶界处的原子反应更快，从而建立了纹理化模式。一旦建立，起始层的纹理化图案通过蚀刻或氧化起始层被转移到单晶硅表面。由于沿着它们各自的独特叠加的晶界而消耗连续的多晶硅起始层，多次进行这种纹理化过程会产生更大的纹理化。

55. 发明授权

US08869627B2 Multi-phase flow metering system 有权
标题翻译：多相流量计量系统
公开(公告)号：US08869627B2
公开(公告)日：2014-10-28
申请号：US13544671
申请日：2012-07-09
申请人： Luai M. Al-Hadhrami , Shafiqur Rehman , Aftab Ahmad
发明人： Luai M. Al-Hadhrami , Shafiqur Rehman , Aftab Ahmad
IPC分类号： G01F1/74
CPC分类号： G01F1/74 , G01F15/08
摘要： The multi-phase flow metering system facilitates the measurement of the flow of oil, gas, and/or other materials from one or more producing petroleum wells. The system has an expansion chamber to separate liquid and as phases. The gas rises through a pipe extending from the top of the expansion chamber. Liquids flow from the bottom of the expansion chamber through a generally U-shaped line having a sediment trap therein. Separate metering devices are provided in the gas outflow line and in the liquid line for accurately measuring the flow of each phase, and in the inlet line for measuring temperature, pressure, and flow at that point. The system includes float valves at the inlet to the gas outflow line and at the liquid phase outlet to control flow through the system. The gas outflow line may continue as a separate line, or reconnect to the liquid outflow line.
摘要翻译：多相流量计量系统有助于测量来自一个或多个生产石油井的油，气和/或其它材料的流动。该系统具有用于分离液体和分相的膨胀室。气体通过从膨胀室的顶部延伸的管道上升。液体从膨胀室的底部流过其中具有沉淀物捕集器的大致U形的管线。在气体流出管线和液体管线中设置有单独的计量装置，用于精确地测量每个相的流量，以及在该点处测量温度，压力和流量的入口管线。该系统包括在气体流出管线和液相出口的入口处的浮阀，以控制通过系统的流量。气体流出管线可以作为单独的管线继续，或者重新连接到液体流出管线。

56. 发明授权

US07071067B1 Fabrication of integrated devices using nitrogen implantation 失效
公开(公告)号：US07071067B1
公开(公告)日：2006-07-04
申请号：US09397952
申请日：1999-09-17
申请人： Aftab Ahmad
发明人： Aftab Ahmad
IPC分类号： H01L21/8236 , H01L21/425 , H01L21/4763
CPC分类号： H01L29/518 , H01L21/26506 , H01L21/28176 , H01L21/2822 , H01L21/823864 , H01L29/42368 , H01L29/6659
摘要： A process is provided for forming an isolating nitride film to isolate gate polysilicon of a gate structure. Specifically, the process comprises providing a channel region defined by a source and drain region of a semiconductor substrate having a gate structure comprising an isolating oxide layer positioned on the channel region and the polysilicon layer positioned on the oxide layer. More specifically, the process comprises the steps of forming the nitrogen implanted regions over the semiconductor substrate by implanting nitrogen atoms into those regions and growing spacers from exposed portions of the polysilicon layer. During the spacer growth, the spacer grows vertically as well as laterally extending under the polysilicon edges. Diffusion of nitrogen atoms to the substrate surface forms silicon nitride under the gate edges, which minimizes current leakages into gate polysilicon.

57. 发明授权

US06858507B2 Graded LDD implant process for sub-half-micron MOS devices 失效
标题翻译：用于半微米MOS器件的渐变LDD注入工艺
公开(公告)号：US06858507B2
公开(公告)日：2005-02-22
申请号：US10198941
申请日：2002-07-19
申请人： Aftab Ahmad , Charles Dennison
发明人： Aftab Ahmad , Charles Dennison
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/10 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/28247 , H01L21/823814 , H01L29/1083 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , Y10S257/90 , Y10S257/917 , H01L2924/00
摘要： A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N-LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.
摘要翻译：在N-LDD区域和N +源极和漏极的产生期间，在低和高剂量砷植入物之后执行低剂量磷植入物，对轻掺杂漏极（LDD）N沟道MOSFET的结点进行分级的方法。磷植入物被驱动以扩散到电极/ LDD结和LDD /通道结两者。

58. 发明授权

US06831347B1 Shallow trench isolation using low dielectric constant insulator 失效
标题翻译：使用低介电常数绝缘子的浅沟槽隔离
公开(公告)号：US06831347B1
公开(公告)日：2004-12-14
申请号：US08932228
申请日：1997-09-17
申请人： Klaus F. Schuegraf , Aftab Ahmad
发明人： Klaus F. Schuegraf , Aftab Ahmad
IPC分类号： H01L2900
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to eliminate the formation of voids during the trench refill process and provides for greater planarity in the final isolation structure. Effective device isolation is achieved with a reduced trench depth by utilizing refilling dielectric materials having low dielectric constant.
摘要翻译：公开了一种浅沟槽隔离，其中沟槽深度减小到超过现有技术工艺中所达到的深度。减小的沟槽深度有助于在沟槽再填充过程期间消除空隙的形成，并且在最终隔离结构中提供更大的平坦度。通过利用具有低介电常数的再填充介电材料，通过减小沟槽深度实现有效的器件隔离。

59. 发明授权

US06346439B1 Semiconductor transistor devices and methods for forming semiconductor transistor devices 失效
标题翻译：半导体晶体管器件和用于形成半导体晶体管器件的方法
公开(公告)号：US06346439B1
公开(公告)日：2002-02-12
申请号：US08677266
申请日：1996-07-09
申请人： Aftab Ahmad , David J. Keller
发明人： Aftab Ahmad , David J. Keller
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L21/823814 , H01L21/823864 , H01L29/6659 , H01L29/7833
摘要： The invention includes a method for forming graded junction regions comprising: a) providing a semiconductor material wafer; b) providing a transistor gate over the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) providing sidewall spacers adjacent the sidewalls of the transistor gate, the sidewall spacers having a lateral thickness; d) decreasing the lateral thickness of the sidewall spacers; and e) after decreasing the lateral thickness of the sidewall spacers, implanting a conductivity-enhancing dopant into the semiconductor material to form graded junction regions operatively adjacent the transistor gate. The invention also includes a semiconductor transistor device comprising: a) a region of a semiconductor material wafer; b) a transistor gate over a portion of the region of the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) opposing source/drain regions operatively adjacent the transistor gate, each source/drain region having an inner lateral boundary; d) opposing sidewall spacers adjacent the sidewalls of the transistor gate, each sidewall spacer having an outer lateral edge, the sidewall spacers and source/drain regions being paired such that the outer lateral edges of the sidewall spacers are displaced laterally inwardly relative to the inner lateral boundaries of the source/drain regions; and e) lateral gaps, the lateral gaps extending from the outer lateral edges of the sidewall spacers to the inner lateral boundaries of the source/drain regions.
摘要翻译：本发明包括一种用于形成渐变连接区域的方法，包括：a）提供半导体材料晶片; b）在所述半导体材料晶片上提供晶体管栅极，所述晶体管栅极具有相对的侧向侧壁; c）提供与所述晶体管栅极的侧壁相邻的侧壁间隔件，所述侧壁间隔件具有横向厚度; d）减小侧壁间隔物的横向厚度; 以及e）在减小所述侧壁间隔物的横向厚度之后，将导电性增强掺杂剂注入到所述半导体材料中以形成与所述晶体管栅极可操作地相邻的渐变连接区域。本发明还包括半导体晶体管器件，其包括：a）半导体材料晶片的区域; b）在所述半导体材料晶片的所述区域的一部分上的晶体管栅极，所述晶体管栅极具有相对的侧向侧壁; c）与所述晶体管栅极可操作地相邻的源极/漏极区域，每个源极/漏极区域具有内侧边界; d）与晶体管栅极的侧壁相邻的相对的侧壁间隔件，每个侧壁间隔件具有外侧边缘，所述侧壁间隔件和源极/漏极区域成对，使得侧壁间隔件的外侧边缘相对于内侧源极/漏极区域的横向边界; 以及e）横向间隙，所述侧向间隙从所述侧壁间隔物的外侧边缘延伸到所述源极/漏极区域的内侧边界。

60. 发明授权

US6136637A Method of forming CMOS circuitry including patterning conductive material overlying field isolation oxide 失效
标题翻译：形成CMOS电路的方法，包括图案化覆盖场隔离氧化物的导电材料层
公开(公告)号：US6136637A
公开(公告)日：2000-10-24
申请号：US124560
申请日：1998-07-28
申请人： Aftab Ahmad , David J. Keller , Tyler A. Lowrey
发明人： Aftab Ahmad , David J. Keller , Tyler A. Lowrey
IPC分类号： H01L21/8234 , H01L21/8239 , H01L21/8242 , H01L21/8238
CPC分类号： H01L27/10873 , H01L21/823425 , H01L21/823475 , H01L27/1052 , H01L27/10894
摘要： A method for forming CMOS DRAM circuitry is disclosed and which includes forming a substrate comprising an array NMOS region, a peripheral NMOS region, and a peripheral PMOS region; forming a pair of insulated and spaced gate lines in the array NMOS region; forming at least one electrically conductive plug in the array NMOS region and which spans between the pair of gate lines; forming a barrier layer over the pair of gate lines in the array NMOS region, the peripheral NMOS and the peripheral PMOS region; and patterning and etching in the peripheral PMOS region to form peripheral PMOS region gate lines including removing a portion of the barrier layer in the PMOS peripheral region and leaving barrier layer material in the NMOS region masking over the electrically conductive plug
摘要翻译：公开了一种用于形成CMOS DRAM电路的方法，其包括形成包括阵列NMOS区，外围NMOS区和外围PMOS区的衬底; 在阵列NMOS区域中形成一对绝缘和间隔开的栅极线; 在所述阵列NMOS区域中形成至少一个导电插塞，并跨越所述一对栅极线; 在阵列NMOS区域，外围NMOS和外围PMOS区域中的一对栅极线上形成阻挡层; 并且在外围PMOS区域中图案化和蚀刻以形成外围PMOS区域栅极线，包括去除PMOS外围区域中的一部分势垒层，并且使阻挡层材料留在导电插塞

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