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51. 发明授权

US07495494B2 Parallel trimming method and apparatus for a voltage controlled delay loop 有权
标题翻译：用于电压控制延迟回路的平行修整方法和装置
公开(公告)号：US07495494B2
公开(公告)日：2009-02-24
申请号：US11141703
申请日：2005-05-31
申请人： Ronald L. Freyman , Mohammad S. Mobin , Vladimir Sindalovsky , Lane A. Smith
发明人： Ronald L. Freyman , Mohammad S. Mobin , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H03H11/26
CPC分类号： H03L7/0814 , H04L7/0337
摘要： A parallel trimming method and apparatus are provided for a voltage controlled delay loop. A plurality of delay units in a voltage controlled delay loop are trimmed. Each delay unit comprises a delay element and a latch buffer. A reference signal is applied to each of the delay units and a position of an edge (such as a rising or falling edge) associated with each of the delay units is identified. The edges of the delay units are then aligned by adjusting a trim setting of the respective latch buffer.
摘要翻译：提供了一种用于电压控制延迟环路的并行修整方法和装置。电压控制延迟环中的多个延迟单元被修整。每个延迟单元包括延迟元件和锁存缓冲器。参考信号被施加到每个延迟单元，并且识别与每个延迟单元相关联的边缘（例如上升沿或下降沿）的位置。然后通过调整相应的锁存缓冲器的修整设置来对准延迟单元的边缘。

52. 发明申请

US20100128828A1 METHODS AND APPARATUS FOR ADAPTING ONE OR MORE EQUALIZATION PARAMETERS BY REDUCING GROUP DELAY SPREAD 有权
标题翻译：通过减少组延迟扩展来适应一个或多个均衡参数的方法和装置
公开(公告)号：US20100128828A1
公开(公告)日：2010-05-27
申请号：US12323155
申请日：2008-11-25
申请人： Mohammad S. Mobin , Kenneth W. Paist , Lane A. Smith
发明人： Mohammad S. Mobin , Kenneth W. Paist , Lane A. Smith
IPC分类号： H04B1/10
CPC分类号： H04L25/03006 , H04L2025/0349
摘要： Methods and apparatus are provided for adapting one or more equalization parameters in a communications system by reducing group delay spread. According to one aspect of the invention, one or more equalization parameters in a communications system are adapted by detecting one or more predefined run length patterns in a received signal, such as a plurality of consecutive same-valued bits; evaluating a transition latch value for each of the detected predefined run length patterns, wherein the transition latch value provides an indication of whether the received signal is under-equalized or over-equalized; and adjusting the one or more equalization parameters of the communications system based on the evaluation of the transition latch value. The adjusted equalization parameters may be employed to equalize intersymbol interference. A data eye monitor can be employed to evaluate the transition latch value.
摘要翻译：提供了用于通过减少组延迟扩展来调整通信系统中的一个或多个均衡参数的方法和装置。根据本发明的一个方面，通信系统中的一个或多个均衡参数通过检测接收信号中的一个或多个预定义的游程长度模式来适配，诸如多个连续的同值比特; 评估所检测到的预定游程长度模式中的每一个的转换锁存值，其中所述转换锁存值提供所述接收信号是否欠均衡或过均衡的指示; 以及基于所述转换锁存器值的评估来调整所述通信系统的一个或多个均衡参数。可以采用经调整的均衡参数来均衡码间干扰。数据眼监视器可用于评估转换锁存值。

53. 发明申请

US20100054383A1 METHODS AND APPARATUS FOR GENERATING EARLY OR LATE SAMPLING CLOCKS FOR CDR DATA RECOVERY 有权
标题翻译：用于生成CDR数据恢复的早期或最后采样时钟的方法和装置
公开(公告)号：US20100054383A1
公开(公告)日：2010-03-04
申请号：US12199904
申请日：2008-08-28
申请人： Mohammad S. Mobin , Kenneth W. Paist , Lane A. Smith , Paul H. Tracy , William B. Wilson
发明人： Mohammad S. Mobin , Kenneth W. Paist , Lane A. Smith , Paul H. Tracy , William B. Wilson
IPC分类号： H04L7/00
CPC分类号： H04L7/0337
摘要： Methods and apparatus are provided for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to ideal transition and sample points. An early sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the transition clock signals to generate one or more early clock signals. A late sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the data sampling clock signals to generate one or more late clock signals. The early clock signals can be employed, for example, in a threshold-based decision feedback equalizer. The late clock signals can be employed, for example, in a classical decision feedback equalizer.
摘要翻译：提供了用于CDR数据采样的时钟相位发生器的方法和装置，其相对于理想的转换和采样点产生早和/或晚的采样时钟。通过产生具有基本均匀的相位分离的多个过渡和数据采样时钟信号来产生早期采样时钟; 以及延迟所述转换时钟信号中的至少一个以产生一个或多个早期时钟信号。通过产生具有基本均匀的相位分离的多个过渡和数据采样时钟信号来产生延迟采样时钟; 以及延迟所述数据采样时钟信号中的至少一个以产生一个或多个后期时钟信号。早期的时钟信号可以用于例如基于阈值的判决反馈均衡器中。后期时钟信号可以用于例如经典的判决反馈均衡器中。

54. 发明申请

US20090168862A1 Methods and Apparatus for Detecting and Decoding Adaptive Equalization Training Frames 有权
标题翻译：用于检测和解码自适应均衡训练帧的方法和装置
公开(公告)号：US20090168862A1
公开(公告)日：2009-07-02
申请号：US11967463
申请日：2007-12-31
申请人： Yasser Ahmed , Xingdong Dai , Mohammad S. Mobin , Lane A. Smith
发明人： Yasser Ahmed , Xingdong Dai , Mohammad S. Mobin , Lane A. Smith
IPC分类号： H04L27/01
CPC分类号： H04L27/01 , H04L7/0066 , H04L7/0083 , H04L25/4904
摘要： Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame maker and a predefined binary value in an output of the logic function.
摘要翻译：提供了用于检测和解码自适应均衡训练帧（具有包括二进制和二进制零序列的帧标记）的方法和装置。通过移位接收到的数据来检测训练帧; 在移位的接收数据的一端插入至少一个二进制值以产生所接收数据的修改版本; 对所接收的数据应用逻辑功能以及当对应的位位置具有不同值时识别的接收数据的修改版本; 以及当所述逻辑功能的输出在第二二进制值的字符串的大致中间具有第一二进制值时，检测所述帧标记。使用框架制造商的近似中心之间的距离和逻辑功能的输出中的预定二进制值对训练帧进行解码。

55. 发明申请

US20090097541A1 Methods And Apparatus For Determining Receiver Filter Coefficients For A Plurality Of Phases 有权
标题翻译：用于确定多个相位的接收器滤波器系数的方法和装置
公开(公告)号：US20090097541A1
公开(公告)日：2009-04-16
申请号：US11870908
申请日：2007-10-11
申请人： Pervez M. Aziz , Mohammad S. Mobin , Lane A. Smith
发明人： Pervez M. Aziz , Mohammad S. Mobin , Lane A. Smith
IPC分类号： H03H7/30
CPC分类号： H04L1/205
摘要： Methods and apparatus are provided for determining receiver filter coefficients for a plurality of phases. One or more coefficients for a receiver filter are determined by determining a first coefficient for a first phase of a data eye; and determining a second coefficient for a second phase of the data eye. The receiver filter may be, for example, a decision-feedback equalizer. The first and second coefficients may be determined by performing an LMS adaptation of decision-feedback equalization coefficients. In another embodiment, the first and second coefficients may be determined by obtaining eye opening metrics from a data eye monitor corresponding to each of the respective first phase and the second phase; and determining the respective first and second coefficients based on the eye opening metrics. The first and second phases can correspond to odd and even phases.
摘要翻译：提供了用于确定多个相位的接收机滤波器系数的方法和装置。通过确定数据眼的第一阶段的第一系数来确定接收机滤波器的一个或多个系数; 以及确定所述数据眼睛的第二阶段的第二系数。接收机滤波器可以是例如判决反馈均衡器。可以通过执行判决反馈均衡系数的LMS适应来确定第一和第二系数。在另一个实施例中，可以通过从对应于相应的第一阶段和第二阶段中的每一个的数据眼睛监视器获得眼睛开度度量来确定第一和第二系数; 以及基于所述眼睛开度度量确定相应的第一和第二系数。第一和第二相可以对应于奇数和偶数相。

56. 发明授权

US08107522B2 Methods and apparatus for determining receiver filter coefficients for a plurality of phases 有权
标题翻译：用于确定多个相位的接收机滤波器系数的方法和装置
公开(公告)号：US08107522B2
公开(公告)日：2012-01-31
申请号：US11870908
申请日：2007-10-11
申请人： Pervez M. Aziz , Mohammad S. Mobin , Lane A. Smith
发明人： Pervez M. Aziz , Mohammad S. Mobin , Lane A. Smith
IPC分类号： H03H7/30
CPC分类号： H04L1/205
摘要： Methods and apparatus are provided for determining receiver filter coefficients for a plurality of phases. One or more coefficients for a receiver filter are determined by determining a first coefficient for a first phase of a data eye; and determining a second coefficient for a second phase of the data eye. The receiver filter may be, for example, a decision-feedback equalizer. The first and second coefficients may be determined by performing an LMS adaptation of decision-feedback equalization coefficients. In another embodiment, the first and second coefficients may be determined by obtaining eye opening metrics from a data eye monitor corresponding to each of the respective first phase and the second phase; and determining the respective first and second coefficients based on the eye opening metrics. The first and second phases can correspond to odd and even phases.
摘要翻译：提供了用于确定多个相位的接收机滤波器系数的方法和装置。通过确定数据眼的第一阶段的第一系数来确定接收机滤波器的一个或多个系数; 以及确定所述数据眼睛的第二阶段的第二系数。接收机滤波器可以是例如判决反馈均衡器。可以通过执行判决反馈均衡系数的LMS适应来确定第一和第二系数。在另一个实施例中，可以通过从对应于相应的第一阶段和第二阶段中的每一个的数据眼睛监视器获得眼睛开度度量来确定第一和第二系数; 以及基于所述眼睛开度度量确定相应的第一和第二系数。第一和第二相可以对应于奇数和偶数相。

57. 发明授权

US08369470B2 Methods and apparatus for adapting one or more equalization parameters by reducing group delay spread 有权
标题翻译：通过减少组延迟扩展来适应一个或多个均衡参数的方法和装置
公开(公告)号：US08369470B2
公开(公告)日：2013-02-05
申请号：US12323155
申请日：2008-11-25
申请人： Mohammad S. Mobin , Kenneth W. Paist , Lane A. Smith
发明人： Mohammad S. Mobin , Kenneth W. Paist , Lane A. Smith
IPC分类号： H03D1/06 , H03K5/01
CPC分类号： H04L25/03006 , H04L2025/0349
摘要： Methods and apparatus are provided for adapting one or more equalization parameters in a communications system by reducing group delay spread. According to one aspect of the invention, one or more equalization parameters in a communications system are adapted by detecting one or more predefined run length patterns in a received signal, such as a plurality of consecutive same-valued bits; evaluating a transition latch value for each of the detected predefined run length patterns, wherein the transition latch value provides an indication of whether the received signal is under-equalized or over-equalized; and adjusting the one or more equalization parameters of the communications system based on the evaluation of the transition latch value. The adjusted equalization parameters may be employed to equalize intersymbol interference. A data eye monitor can be employed to evaluate the transition latch value.
摘要翻译：提供了用于通过减少组延迟扩展来调整通信系统中的一个或多个均衡参数的方法和装置。根据本发明的一个方面，通信系统中的一个或多个均衡参数通过检测接收信号中的一个或多个预定义的游程长度模式来适配，诸如多个连续的同值比特; 评估所检测到的预定游程长度模式中的每一个的转换锁存值，其中所述转换锁存值提供所述接收信号是否欠均衡或过均衡的指示; 以及基于所述转换锁存器值的评估来调整所述通信系统的一个或多个均衡参数。可以采用经调整的均衡参数来均衡码间干扰。数据眼监视器可用于评估转换锁存值。

58. 发明授权

US08428195B2 Methods and apparatus for detecting and decoding adaptive equalization training frames 有权
标题翻译：用于检测和解码自适应均衡训练帧的方法和装置
公开(公告)号：US08428195B2
公开(公告)日：2013-04-23
申请号：US11967463
申请日：2007-12-31
申请人： Yasser Ahmed , Xingdong Dai , Mohammad S. Mobin , Lane A. Smith
发明人： Yasser Ahmed , Xingdong Dai , Mohammad S. Mobin , Lane A. Smith
IPC分类号： H04L27/06
CPC分类号： H04L27/01 , H04L7/0066 , H04L7/0083 , H04L25/4904
摘要： Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame maker and a predefined binary value in an output of the logic function.
摘要翻译：提供了用于检测和解码自适应均衡训练帧（具有包括二进制和二进制零序列的帧标记）的方法和装置。通过移位接收到的数据来检测训练帧; 在移位的接收数据的一端插入至少一个二进制值以产生所接收数据的修改版本; 对所接收的数据应用逻辑功能以及当对应的位位置具有不同值时识别的接收数据的修改版本; 以及当所述逻辑功能的输出在第二二进制值的字符串的大致中间具有第一二进制值时，检测所述帧标记。使用框架制造商的近似中心之间的距离和逻辑功能的输出中的预定二进制值对训练帧进行解码。

59. 发明授权

US08407511B2 Method and apparatus for generating early or late sampling clocks for CDR data recovery 有权
标题翻译：用于生成用于CDR数据恢复的早期或晚期采样时钟的方法和装置
公开(公告)号：US08407511B2
公开(公告)日：2013-03-26
申请号：US12199904
申请日：2008-08-28
申请人： Mohammad S. Mobin , Kenneth W. Paist , Lane A. Smith , Paul H. Tracy , William B. Wilson
发明人： Mohammad S. Mobin , Kenneth W. Paist , Lane A. Smith , Paul H. Tracy , William B. Wilson
IPC分类号： H04L7/00 , G06F1/00
CPC分类号： H04L7/0337
摘要： Methods and apparatus are provided for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to ideal transition and sample points. An early sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the transition clock signals to generate one or more early clock signals. A late sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the data sampling clock signals to generate one or more late clock signals. The early clock signals can be employed, for example, in a threshold-based decision feedback equalizer. The late clock signals can be employed, for example, in a classical decision feedback equalizer.
摘要翻译：提供了用于CDR数据采样的时钟相位发生器的方法和装置，其相对于理想的转换和采样点产生早和/或晚的采样时钟。通过产生具有基本均匀的相位分离的多个过渡和数据采样时钟信号来产生早期采样时钟; 以及延迟所述转换时钟信号中的至少一个以产生一个或多个早期时钟信号。通过产生具有基本均匀的相位分离的多个过渡和数据采样时钟信号来产生延迟采样时钟; 以及延迟所述数据采样时钟信号中的至少一个以产生一个或多个后期时钟信号。早期的时钟信号可以用于例如基于阈值的判决反馈均衡器中。后期时钟信号可以用于例如经典的判决反馈均衡器中。

60. 发明授权

US07706487B2 Method for training a transceiver for high speed communications 有权
标题翻译：用于训练用于高速通信的收发器的方法
公开(公告)号：US07706487B2
公开(公告)日：2010-04-27
申请号：US10964056
申请日：2004-10-12
申请人： Pervez Mirza Aziz , Donald Raymond Laturell , Mohammad Shafiul Mobin , Gregory W. Sheets , Lane A. Smith
发明人： Pervez Mirza Aziz , Donald Raymond Laturell , Mohammad Shafiul Mobin , Gregory W. Sheets , Lane A. Smith
IPC分类号： H04B1/10
CPC分类号： G01R31/31715 , H04B3/04 , H04L25/03038 , H04L2025/03356 , H04L2025/03477 , H04L2025/03617
摘要： In training a SERDES, a Common Electrical Interface (CEI) training frame, having certain bits of information embedded therein, is transmitted over a path which comprises transmitter, channel, and receiver components. The present invention analyzes the resulting received signal and determines the effective aggregate channel impulse response of these three components. The invention then determines an estimate of the inverse of this aggregate channel and uses this determination to reduce distortions that have been introduced into a signal that has been transmitted over the path.
摘要翻译：在训练SERDES时，通过包含发射机，信道和接收机组件的路径发送具有嵌入其中的某些信息位的公共电接口（CEI）训练帧。本发明分析所得到的接收信号并确定这三个分量的有效总信道脉冲响应。然后，本发明确定该聚合信道的逆的估计，并且使用该确定来减少已经被引入到已经通过该路径传输的信号中的失真。

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