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    • 56. 发明申请
    • Use Of The PIGD Protein For Catalyzing 1,4-Additions Of 2-Oxoalkanoates To Alpha, Beta-Unsaturated Ketones
    • 使用PIGD蛋白,用于催化1,4-加成的2-氧代链烷酸酯至α,β-不饱和酮
    • US20100305337A1
    • 2010-12-02
    • US12599373
    • 2008-04-18
    • Michael MüllerCarola DresenMichael Richter
    • Michael MüllerCarola DresenMichael Richter
    • C07D333/16C07D307/02C07C45/00
    • C12P7/26
    • The present invention relates to the preparation of compounds of the general formula II which can be obtained by 1,4 addition of 2-oxoalkanoates or 2-oxocarboxylic acids onto the appropriate ketones. The present invention also relates to the use of the PigD protein for catalysis of 1,4 additions of 2-oxoalkanoates/-carboxylic acids, for example pyruvate/pyruvic acid or 2-oxobutyrate/2-oxobutyric acid, onto aliphatic, aromatic and heterocyclic α,β-unsaturated ketones. The 1,4 additions are effected here with CO2 elimination. The use of the PigD protein as a catalyst in the aforementioned 1,4 additions enables the synthesis of addition products with stereoactive centers these addition products being preparable with an enantiomeric excess of more than 80% ee. The aliphatic, aromatic and heterocyclic α,β-unsaturated ketones which are suitable for the process are represented by the general formula I:
    • 本发明涉及通过在适当的酮上加入2-氧代链烷酸酯或2-氧代羧酸得到的通式II化合物的制备。 本发明还涉及PigD蛋白用于在脂族,芳族和杂环上加成1,4-加成的2-氧代链烷酸酯/羧酸(例如丙酮酸/丙酮酸或2-氧代丁酸/ 2-氧代丁酸)的用途 α,β-不饱和酮。 这里添加1,4添加物可以消除二氧化碳。 在上述1,4添加物中使用PigD蛋白作为催化剂使得能够用立体中心合成加成产物,这些加成产物可以被制备成具有超过80%ee的对映体过量。 适用于该方法的脂族,芳族和杂环α,β-不饱和酮由通式I表示:
    • 60. 发明授权
    • Edge pad architecture for semiconductor memory
    • 半导体存储器的边缘焊盘结构
    • US07405957B2
    • 2008-07-29
    • US11320266
    • 2005-12-28
    • Josef SchnellMichael RichterMichael A. Killian
    • Josef SchnellMichael RichterMichael A. Killian
    • G11C5/06
    • G11C5/025H01L27/105
    • A memory includes a wafer having at least a first and second edge, at least one memory bank array, a data path, and a plurality of data pads. The data path is coupled to the memory bank array. The plurality of data pads are coupled to the data path and configured with the data path to bus data to and from the memory bank array. The data pads are further configured such that each of the data pads are located adjacent the first and second edges of the wafer. The memory component is configurable for alternative applications such that in a first application all of the data pads used to bus data are located only on the first edge of the wafer and such that in a second application at least one of the data pads used to bus data is located on the first edge of the wafer and at least one of the data pads used to bus data is located on the second edge of the wafer.
    • 存储器包括具有至少第一和第二边缘,至少一个存储体阵列,数据路径和多个数据焊盘的晶片。 数据路径耦合到存储体阵列。 多个数据焊盘耦合到数据路径并配置有与存储体阵列的总线数据的数据路径。 数据焊盘被进一步配置成使得每个数据焊盘位于晶片的第一和第二边缘附近。 存储器组件可配置用于替代应用,使得在第一应用中,用于总线数据的所有数据焊盘仅位于晶片的第一边缘上,并且使得在第二应用中,至少一个数据焊盘用于总线 数据位于晶片的第一边缘上,并且用于总线数据的至少一个数据焊盘位于晶片的第二边缘上。