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51. 发明授权

US06836849B2 Method and apparatus for controlling power and performance in a multiprocessing system according to customer level operational requirements 有权
标题翻译：根据客户级操作要求，在多处理系统中控制功率和性能的方法和装置
公开(公告)号：US06836849B2
公开(公告)日：2004-12-28
申请号：US09826986
申请日：2001-04-05
申请人： Bishop Chapman Brock , Harm Peter Hofstee , Mark A. Johnson , Thomas Walter Keller, Jr. , Kevin John Nowka
发明人： Bishop Chapman Brock , Harm Peter Hofstee , Mark A. Johnson , Thomas Walter Keller, Jr. , Kevin John Nowka
IPC分类号： G06F126
CPC分类号： G06F1/3203
摘要： A method and controller for managing power and performance of a multiprocessor (MP) system is described. The controller receives sensor data corresponding to physical parameters within the MP system. The controller also receives quality of service and policy parameters corresponding to the MP system. The quality of service parameters define commitments to customers for utilization of the MP system. The policy parameters correspond to operation limits on inputs and outputs of the MP system. The operation input limits relate to the cost and availability of power or individual processor availability. The operation output limits relate to the amount of heat, acoustic noise levels, EMC levels, etc. that the individual or group of processors in the MP system are allowed to generate in a particular environment. A controller receives the physical parameters, the quality of service parameters and policy parameters and determines performance goals for the MP system and processors within the MP system. Then controller generates controls and applies them to individual processors to achieve the performance goals.
摘要翻译：描述了一种用于管理多处理器（MP）系统的功率和性能的方法和控制器。控制器接收与MP系统内的物理参数对应的传感器数据。控制器还接收与MP系统对应的服务质量和策略参数。服务质量参数定义了对客户使用MP系统的承诺。策略参数对应于MP系统的输入和输出的操作限制。操作输入限制涉及功率或单个处理器可用性的成本和可用性。操作输出限制涉及允许MP系统中的个体或一组处理器在特定环境中生成的热量，声学噪声水平，EMC等级等。控制器接收物理参数，服务质量参数和策略参数，并确定MP系统中的MP系统和处理器的性能目标。然后控制器生成控件并将其应用于各个处理器以实现性能目标。

52. 发明授权

US06717882B1 Cell circuit for multiport memory using 3-way multiplexer 失效
标题翻译：使用3路复用器的多端口存储器的单元电路
公开(公告)号：US06717882B1
公开(公告)日：2004-04-06
申请号：US10273590
申请日：2002-10-17
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Shoji Onishi , Osamu Takahashi
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Shoji Onishi , Osamu Takahashi
IPC分类号： G11C800
CPC分类号： G11C8/16
摘要： An improved cell circuit for data readout for use in a multiport memory is provided. The multiport memory stores write data signals. The cell circuit includes a plurality of multiplexers each coupled to a discharge device. Each of the multiplexers receives a subset of the write data signals and a plurality of read wordline signals and selects an output enable signal among the subset of the write data signals based on the read wordline signals. Each of the discharge devices are coupled to one of the multiplexers for receiving the output enable signal to generate a drive signal for driving one or more bitlines of the multiport memory.
摘要翻译：提供用于多端口存储器中的用于数据读出的改进的单元电路。多端口存储器存储写入数据信号。电池电路包括多个多路复用器，每个多路复用器耦合到放电装置。每个多路复用器接收写入数据信号的子集和多个读取字线信号，并且基于所读取的字线信号在写入数据信号的子集中选择输出使能信号。每个放电装置耦合到多路复用器中的一个，用于接收输出使能信号，以产生用于驱动多端口存储器的一个或多个位线的驱动信号。

53. 发明授权

US06600959B1 Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arrays 失效
标题翻译：使用动态可编程逻辑阵列实现微处理器控制逻辑的方法和装置
公开(公告)号：US06600959B1
公开(公告)日：2003-07-29
申请号：US09498934
申请日：2000-02-04
申请人： Paula Kristine Coulman , Sang Hoo Dhong , Brian King Flachs , Harm Peter Hofstee , Jaehong Park , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi
发明人： Paula Kristine Coulman , Sang Hoo Dhong , Brian King Flachs , Harm Peter Hofstee , Jaehong Park , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： G05B1918
CPC分类号： H03K17/693 , H03K5/06
摘要： A method and apparatus for using dynamic programmable logic arrays in microprocessor control logic provide decreased power and increased clock frequencies for data processing systems, by using programmable logic arrays exclusively for the control logic. The method and apparatus further simplify the design of the control logic and closure of timing within the microprocessor, by providing overlap of control logic evaluations and data transfers within the microprocessor.
摘要翻译：在微处理器控制逻辑中使用动态可编程逻辑阵列的方法和装置通过专门用于控制逻辑的可编程逻辑阵列来为数据处理系统提供降低的功率和增加的时钟频率。该方法和装置通过在微处理器内提供控制逻辑评估和数据传输的重叠来进一步简化控制逻辑的设计和微处理器内的定时闭合。

54. 发明授权

US08295056B2 Silicon carrier structure and method of forming same 有权
标题翻译：硅载体结构及其形成方法
公开(公告)号：US08295056B2
公开(公告)日：2012-10-23
申请号：US12507591
申请日：2009-07-22
申请人： Paul Stephen Andry , Harm Peter Hofstee , George A. Katopis , John Ulrich Knickerbocker , Robert K. Montoye , Chirag S. Patel
发明人： Paul Stephen Andry , Harm Peter Hofstee , George A. Katopis , John Ulrich Knickerbocker , Robert K. Montoye , Chirag S. Patel
IPC分类号： H05K7/00
CPC分类号： H01L25/0655 , H01L23/147 , H01L23/60 , H01L25/0652 , H01L2224/16225 , H01L2924/10253 , H01L2924/157 , Y02T10/82 , H01L2924/00
摘要： A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.
摘要翻译：一种用于电子封装的硅载体结构包括基底，设置在基底基板上的硅载体衬底，设置在硅载体衬底上的存储芯片，设置在硅载体衬底上的微处理器芯片，设置在硅衬底上的输入/输出芯片硅载体衬底和设置在硅载体衬底上的时钟芯片。

55. 发明授权

US08229989B2 Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units 有权
标题翻译：用于控制单指令多数据（SIMD）浮点单元中舍入模式的方法
公开(公告)号：US08229989B2
公开(公告)日：2012-07-24
申请号：US12238500
申请日：2008-09-26
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译：公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的方法。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

56. 发明授权

US07617338B2 Memory with combined line and word access 有权
标题翻译：内存具有组合的行和字访问
公开(公告)号：US07617338B2
公开(公告)日：2009-11-10
申请号：US11050040
申请日：2005-02-03
申请人： Sang Hoo Dhong , Brian King Flachs , Harm Peter Hofstee , Osamu Takahashi
发明人： Sang Hoo Dhong , Brian King Flachs , Harm Peter Hofstee , Osamu Takahashi
IPC分类号： G06F13/28 , G06F5/00
CPC分类号： G06F13/28 , G06F13/1626 , G06F13/1663
摘要： A system for a processor with memory with combined line and word access is presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank using multiplexers and latches to direct data. The system processes 16 byte load/sore requests using a narrow read/write memory access and also processes 128 byte DMA and instruction fetch requests using a wide read/write memory access. During DMA requests, the system writes/reads sixteen DMA operations to memory on one instruction cycle. By doing this, the memory is available to process load/store or instruction fetch requests during fifteen other instruction cycles.
摘要翻译：提出了一种具有组合线和字访问的存储器的处理器的系统。系统执行窄读/写存储器访问，并使用多路复用器和锁存器对相同存储体进行宽读/写存储器存取以指导数据。该系统使用窄读/写存储器访问处理16字节加载/请求请求，并使用宽读/写存储器访问处理128字节的DMA和指令提取请求。在DMA请求期间，系统在一个指令周期内将16个DMA操作写入/读取存储器。通过这样做，内存可用于在十五个其他指令周期内处理加载/存储或指令提取请求。

57. 发明申请

US20080263336A1 Processor Having Efficient Function Estimate Instructions 审中-公开
标题翻译：具有高效功能估计指令的处理器
公开(公告)号：US20080263336A1
公开(公告)日：2008-10-23
申请号：US12145482
申请日：2008-06-24
申请人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F9/302
CPC分类号： G06F7/483 , G06F7/535 , G06F7/5443 , G06F7/5525 , G06F9/30014 , G06F2207/5356
摘要： High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.
摘要翻译：高精度浮点函数估计分为两个指令：低精度表查找指令和线性插值指令。可以使用该方案来实现不同功能的估计：为每个不同的功能提供单独的表查找指令，而仅需要单个插补指令，因为单个内插指令可以执行任何功能的内插步骤估计。因此，与专用硬件相比，产生的开销大大降低，同时仍保持统一的FPU延迟，这允许更简单的控制逻辑。

58. 发明授权

US07279996B2 Method of functionality testing for a ring oscillator 失效
公开(公告)号：US07279996B2
公开(公告)日：2007-10-09
申请号：US11204408
申请日：2005-08-16
申请人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
发明人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , H03K5/133
摘要： A method and apparatus is provided for testing the logic functionality and electrical continuity of a ring oscillator comprising an odd number of inverters connected to form a closed loop. In the method and apparatus, a known value is forced through the ring oscillator, to test the complete circuit path thereof. Thus, a low overhead deterministic test of the functionality of the ring oscillator is provided. In a useful embodiment of the invention, a method is provided for testing functionality and electrical continuity in a ring oscillator, wherein a first test device is inserted between the input of a first inverter and the output of an adjacent second inverter. The first test device is then operated to apply first and second test bits as input test signals to the first inverter input. The embodiment further comprises detecting the response to the applied first and second test bit signals at the output of the second inverter, and using the detected responses in providing an evaluation of functionality of the ring oscillator.

59. 发明授权

US07233212B2 Oscillator array with row and column control 有权
标题翻译：具有行和列控制的振荡器阵列
公开(公告)号：US07233212B2
公开(公告)日：2007-06-19
申请号：US11095895
申请日：2005-03-31
申请人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
发明人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
IPC分类号： H03B29/00 , H03K3/03
CPC分类号： G06F7/588 , H03K3/0315 , H03K3/84
摘要： A circuit topology which can be used to create an array of individually tuned oscillators operating at different frequencies determined by common control inputs and an easily managed variation in design dimensions of several components is provided. An array of oscillators are provided arranged in columns and rows. Each oscillator in a column is unique from the other oscillators in the column based on number of stages in the oscillator and fanout so that each oscillator will operate at a unique frequency. Oscillators of different columns within the array may differ by a common setting of the selects to these oscillators and the physical ordering of the oscillators in the column to further reduce the possibility of injection locking. A base delay cell provides selects to each column of oscillators such that each column may be programmed to operate at a different frequency from its neighbors.
摘要翻译：提供了一种电路拓扑结构，可用于创建由通用控制输入确定的不同频率运行的单独调谐的振荡器阵列，以及易于管理的多个组件的设计尺寸变化。提供了一列列和列排列的振荡器阵列。列中的每个振荡器都基于列中的其他振荡器是独特的，基于振荡器和扇出的级数，使得每个振荡器将以唯一的频率工作。阵列中不同列的振荡器可能会通过对这些振荡器的选择的共同设置以及列中的振荡器的物理顺序而不同，以进一步降低注入锁定的可能性。基本延迟单元为每列振荡器提供选择，使得每列可被编程为以与其邻居不同的频率工作。

60. 发明授权

US07043579B2 Ring-topology based multiprocessor data access bus 失效
标题翻译：基于环形拓扑的多处理器数据访问总线
公开(公告)号：US07043579B2
公开(公告)日：2006-05-09
申请号：US10313741
申请日：2002-12-05
申请人： Sang Hoo Dhong , Harm Peter Hofstee , John Samuel Liberty , Peichun Peter Liu
发明人： Sang Hoo Dhong , Harm Peter Hofstee , John Samuel Liberty , Peichun Peter Liu
IPC分类号： G06F13/00
CPC分类号： G06F13/4243
摘要： The present invention provides a data access ring. The data access ring has a plurality of attached processor units (APUs) and a local store associated with each APU. The data access ring has a data command ring, coupled to the plurality of APUs. The data command ring is employable to carry indicia of a selection of one of the plurality of APUs to the APUs. The data access ring also has a data address ring, coupled to the plurality of APUs. The data address ring is further employable to carry indicia of a memory location to the selected APU a predetermined number of clock cycles after the data command ring carries the indicia of the selection of one of the plurality of APUs. The data access ring also has a data transfer ring, coupled to the plurality of APUs. The data transfer ring is employable to transfer data to or from the memory location associated with the APU a predetermined number of clock cycles after the data address ring carries the indicia of the memory location to the selected APU.
摘要翻译：本发明提供一种数据访问环。数据访问环具有多个附接的处理器单元（APU）和与每个APU相关联的本地存储器。数据访问环具有耦合到多个APU的数据命令环。数据命令环可用于将多个APU中的一个APU的选择的标记携带到APU。数据访问环还具有耦合到多个APU的数据地址环。数据地址环还可用于在数据命令环携带多个APU中的一个APU的选择的标记之后，将所选择的APU的存储位置的标记携带预定数量的时钟周期。数据访问环还具有耦合到多个APU的数据传送环。在数据地址环将存储器位置的标记传送到所选择的APU之后，数据传送环可用于将数据传送到与APU相关联的存储器位置的数据到预定数量的时钟周期。

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