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51. 发明授权

US06358844B1 Tungsten deposition process with dual-step nucleation 有权
标题翻译：钨沉积工艺与双步成核
公开(公告)号：US06358844B1
公开(公告)日：2002-03-19
申请号：US09585183
申请日：2000-06-01
申请人： Mei-Yun Wang , Shau-Lin Shue
发明人： Mei-Yun Wang , Shau-Lin Shue
IPC分类号： H01L2144
CPC分类号： H01L21/76877 , H01L21/28556 , H01L21/76876
摘要： A tungsten plug deposition process that incorporates a dual-step nucleation method and the semiconductor structure formed by such method are disclosed. In the tungsten plug deposition process, a first nucleation layer is formed in the via openings in the semiconductor substrate by flowing a reactant gas mixture of WF6/SiH4 at a first mix ratio between 1:1 and 1:10 in a chemical vapor deposition chamber. A second nucleation layer is then formed on top of the first nucleation layer by flowing a reactant gas mixture of WF6/SiH4 at a second mix ratio between 2:1 and 5:1 into the chemical vapor deposition chamber. A total thickness of less than 500 Å for the first and second nucleation layers is normally sufficient. The first nucleation layer formed is a silicon rich layer, or a WSix layer, while the second nucleation layer is substantially W. The present invention novel method produces tungsten plugs that have significantly improved step coverage and cumulative resistance properties, while not sacrificing any electro-migration resistance.
摘要翻译：公开了一种结合双步成核方法的钨丝塞沉积工艺和通过这种方法形成的半导体结构。在钨插塞沉积工艺中，通过在化学气相沉积室中以1:1和1:10之间的第一混合比流过WF6 / SiH4的反应气体混合物，在半导体衬底的通路孔中形成第一成核层。然后通过以2:1和5:1的第二混合比将WF6 / SiH4的反应气体混合物流入化学气相沉积室，在第一成核层的顶部上形成第二成核层。通常第一和第二成核层的总厚度小于500埃。所形成的第一成核层是富硅层或WSix层，而第二成核层基本上是W。本发明新颖的方法生产出具有显着改善的台阶覆盖率和累积电阻特性的钨丝塞，同时不牺牲任何电 - 迁移阻力。

52. 发明授权

US06451701B1 Method for making low-resistance silicide contacts between closely spaced electrically conducting lines for field effect transistors 有权
标题翻译：用于场效应晶体管的紧密间隔的导电线之间制造低电阻硅化物接触的方法
公开(公告)号：US06451701B1
公开(公告)日：2002-09-17
申请号：US09993068
申请日：2001-11-14
申请人： Mei-Yun Wang , Shwangming Jeng , Shau-Lin Shue
发明人： Mei-Yun Wang , Shwangming Jeng , Shau-Lin Shue
IPC分类号： H01L21425
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/31155
摘要： A method for making reliable low-resistance contacts between closely spaced FET gate electrodes having high-aspect-ratio spacings. Polysilicon gate electrodes are formed. A conformal insulating layer is deposited and anisotropically etched back to form sidewall spacers on the gate electrodes. During conventional etch-back, the etch rate of the insulating layer between the closely spaced gate electrodes is slower resulting in a residual oxide that prevents the formation of reliable low-resistance contacts. This residual oxide requires an overetch in a hydrofluoric acid solution prior to forming silicide contacts. The wet overetch results in device degradation. A nitrogen or germanium implant is used to amorphize the oxide and to increase the wet etch rate of the residual oxide. Using this amorphization the wet etch that is commonly used as a pre-clean prior to forming silicide contacts can be used to remove the residual silicon oxide without overetching. The implant also results in a smoother interface between the silicide and the silicon substrate, which results in lower sheet resistance.
摘要翻译：一种用于在具有高纵横比间隔的紧密间隔的FET栅电极之间进行可靠的低电阻接触的方法。形成多晶硅栅电极。沉积保形绝缘层并各向异性地回蚀以在栅电极上形成侧壁间隔物。在传统的回蚀期间，绝缘层在紧密间隔的栅电极之间的蚀刻速率较慢，导致残留的氧化物阻止形成可靠的低电阻触点。在形成硅化物接触之前，该残余氧化物需要在氢氟酸溶液中进行过蚀刻。湿过滤会导致设备退化。氮或锗植入物用于使氧化物非晶化并增加残余氧化物的湿蚀刻速率。使用这种非晶化，通常在形成硅化物接触之前通常用作预清洁的湿法蚀刻可以用于除去剩余的氧化硅而不进行过蚀刻。该植入物还导致硅化物和硅衬底之间更平滑的界面，这导致较低的薄层电阻。

53. 发明授权

US6096651A Key-hole reduction during tungsten plug formation 有权
标题翻译：钨丝塞形成期间的关键孔减少
公开(公告)号：US6096651A
公开(公告)日：2000-08-01
申请号：US228126
申请日：1999-01-11
申请人： Mei-Yun Wang , Chen-Hua Yu , Shau-Lin Shue
发明人： Mei-Yun Wang , Chen-Hua Yu , Shau-Lin Shue
IPC分类号： H01L21/768 , H01L21/302
CPC分类号： H01L21/76865 , H01L21/76804 , H01L21/76843 , H01L21/76862
摘要： The problem of key-hole formation during the filling of small diameter via holes has been overcome by means of soft sputtering in argon after the barrier layer is in place. This sputtering step may be used twice--once to widen the mouth of a newly formed via hole, and a second time after the barrier layer is in place, thereby widening the mouth further (as well as removing oxide from the surface of the barrier layer). In an alternate optional embodiment, widening of the via hole mouth may be limited to a single sputtering step after the barrier layer has been laid down. In either case, this is followed by filling of the via hole which occurs without any key-hole formation.
摘要翻译：通过在阻挡层就位之后的氩气中的软溅射，克服了在小直径通孔填充期间形成孔洞的问题。该溅射步骤可以使用两次一次来加宽新形成的通孔的口，并且在阻挡层就位之后的第二次，从而进一步扩大口（以及从阻挡层的表面去除氧化物））。在替代的可选实施例中，通孔口的加宽可以在阻挡层被铺设之后被限制到单个溅射步骤。在任一种情况下，随后填充通孔而没有任何键孔形成。

54. 发明授权

US08836127B2 Interconnect with flexible dielectric layer 有权
标题翻译：与柔性介电层互连
公开(公告)号：US08836127B2
公开(公告)日：2014-09-16
申请号：US12621569
申请日：2009-11-19
申请人： Ching-Yu Lo , Bo-Jiun Lin , Hai-Ching Chen , Tien-I Bao , Shau-Lin Shue , Chen-Hua Yu
发明人： Ching-Yu Lo , Bo-Jiun Lin , Hai-Ching Chen , Tien-I Bao , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L23/522 , H01L23/532 , H01L23/00
CPC分类号： H01L23/53295 , H01L23/5329 , H01L24/02 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/15788 , H01L2924/351 , H01L2924/00
摘要： An integrated circuit device has a dual damascene structure including a lower via portion and an upper line portion. The lower via portion is formed in a polyimide layer, and the upper line portion is formed in an inter-metal dielectric (IMD) layer formed of USG or polyimide. A passivation layer is formed on the IMD layer, and a bond pad is formed overlying the passivation layer to electrically connect the upper line portion.
摘要翻译：集成电路装置具有双镶嵌结构，其包括下通孔部分和上线部分。下通孔部分形成在聚酰亚胺层中，并且上部分部分形成在由USG或聚酰亚胺形成的金属间电介质（IMD）层中。在IMD层上形成钝化层，并且形成覆盖钝化层的接合焊盘以电连接上部线部分。

55. 发明授权

US08791549B2 Wafer backside interconnect structure connected to TSVs 有权
标题翻译：晶圆背面互连结构连接到TSV
公开(公告)号：US08791549B2
公开(公告)日：2014-07-29
申请号：US12832019
申请日：2010-07-07
申请人： Ming-Fa Chen , Wen-Chih Chiou , Shau-Lin Shue
发明人： Ming-Fa Chen , Wen-Chih Chiou , Shau-Lin Shue
IPC分类号： H01L29/40 , H01L23/48 , H01L23/52
CPC分类号： H01L24/81 , H01L21/76807 , H01L21/76813 , H01L21/76816 , H01L21/76841 , H01L21/76843 , H01L21/76877 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/0401 , H01L2224/05022 , H01L2224/05025 , H01L2224/05546 , H01L2224/05547 , H01L2224/05567 , H01L2224/0557 , H01L2224/05571 , H01L2224/06181 , H01L2224/13007 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/13144 , H01L2224/13155 , H01L2224/14181 , H01L2224/811 , H01L2224/8136 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/19041 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.
摘要翻译：集成电路结构包括具有前表面和后表面的半导体衬底; 穿过半导体衬底的导电通孔; 以及在半导体衬底的后表面上的金属特征。金属特征包括覆盖并接触导电通孔的金属焊盘以及导电通孔上方的金属线。金属线包括双镶嵌结构。集成电路结构还包括覆盖金属线的凸块。

56. 发明申请

US20120293782A1 Methods and Systems for Lithography Alignment 审中-公开
标题翻译：光刻对准方法与系统
公开(公告)号：US20120293782A1
公开(公告)日：2012-11-22
申请号：US13564085
申请日：2012-08-01
申请人： Hsiao-Tzu Lu , Hung Chang Hsieh , Kuei Shun Chen , Hsueh-Hung Fu , Ching-Hua Hsieh , Shau-Lin Shue
发明人： Hsiao-Tzu Lu , Hung Chang Hsieh , Kuei Shun Chen , Hsueh-Hung Fu , Ching-Hua Hsieh , Shau-Lin Shue
IPC分类号： G03B27/42
CPC分类号： G03F7/70725 , G03F7/70358 , G03F7/70783 , H01L21/67288
摘要： Methods and systems for lithographically exposing a substrate based on a curvature profile of the substrate.
摘要翻译：基于基板的曲率轮廓光刻曝光基板的方法和系统。

57. 发明授权

US08252682B2 Method for thinning a wafer 有权
标题翻译：减薄晶片的方法
公开(公告)号：US08252682B2
公开(公告)日：2012-08-28
申请号：US12704695
申请日：2010-02-12
申请人： Ku-Feng Yang , Weng-Jin Wu , Hsin-Hsien Lu , Chia-Lin Yu , Chu-Sung Shih , Fu-Chi Hsu , Shau-Lin Shue
发明人： Ku-Feng Yang , Weng-Jin Wu , Hsin-Hsien Lu , Chia-Lin Yu , Chu-Sung Shih , Fu-Chi Hsu , Shau-Lin Shue
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L21/76898 , H01L2224/02372
摘要： A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer. One or more electrical contacts are formed in the dielectric layer for electrical connection to the exposed one or more TSVs.
摘要翻译：提供了一种用于薄化晶片的方法。在一个实施例中，提供具有多个半导体芯片的晶片，晶片具有第一侧和与第一侧相对的第二侧，其中每个芯片包括一组穿通硅通孔（TSV），每个TSV 基本上被衬垫层和阻挡层密封。提供晶片载体以附接到晶片的第二侧。晶片的第一侧变薄并且凹陷以部分地暴露衬里层，阻挡层和从晶片突出的TSV的部分。隔离层沉积在晶片的第一侧和衬垫层，阻挡层和TSV的顶部之上。此后，绝缘层沉积在隔离层上。然后将绝缘层平坦化以暴露TSV的顶部。电介质层沉积在晶片的平坦化第一侧上。在电介质层中形成一个或多个电触头，用于与暴露的一个或多个TSV电连接。

58. 发明申请

US20110115088A1 INTERCONNECT WITH FLEXIBLE DIELECTRIC LAYER 有权
标题翻译：与柔性电介质层互连
公开(公告)号：US20110115088A1
公开(公告)日：2011-05-19
申请号：US12621569
申请日：2009-11-19
申请人： Ching-Yu Lo , Bo-Jiun Lin , Hai-Ching Chen , Tien-I Bao , Shau-Lin Shue , Chen-Hua Yu
发明人： Ching-Yu Lo , Bo-Jiun Lin , Hai-Ching Chen , Tien-I Bao , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L23/48
CPC分类号： H01L23/53295 , H01L23/5329 , H01L24/02 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/15788 , H01L2924/351 , H01L2924/00
摘要： An integrated circuit device has a dual damascene structure including a lower via portion and an upper line portion. The lower via portion is formed in a polyimide layer, and the upper line portion is formed in an inter-metal dielectric (IMD) layer formed of USG or polyimide. A passivation layer is formed on the IMD layer, and a bond pad is formed overlying the passivation layer to electrically connect the upper line portion.
摘要翻译：集成电路装置具有双镶嵌结构，其包括下通孔部分和上线部分。下通孔部分形成在聚酰亚胺层中，并且上部分部分形成在由USG或聚酰亚胺形成的金属间电介质（IMD）层中。在IMD层上形成钝化层，并且形成覆盖钝化层的接合焊盘以电连接上部线部分。

59. 发明授权

US07888719B2 Semiconductor memory structures 有权
标题翻译：半导体存储器结构
公开(公告)号：US07888719B2
公开(公告)日：2011-02-15
申请号：US11752736
申请日：2007-05-23
申请人： Shau-Lin Shue , Chao-An Jong
发明人： Shau-Lin Shue , Chao-An Jong
IPC分类号： H01L29/94 , H01L29/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/16
摘要： A semiconductor structure includes a first conductive layer coupled to a transistor. A first dielectric layer is over the first conductive layer. A second conductive layer is within the first dielectric layer, contacting a portion of a top surface of the first conductive layer. The second conductive layer includes a cap portion extending above a top surface of the first dielectric layer. A first dielectric spacer is between the first dielectric layer and the second conductive layer. A phase change material layer is above a top surface of the second conductive layer. A third conductive layer is over the phase change material layer. A second dielectric layer is over the first dielectric layer. A second dielectric spacer is on a sidewall of the cap portion, wherein a thermal conductivity of the second dielectric spacer is less than that of the first dielectric layer or that of the second dielectric layer.
摘要翻译：半导体结构包括耦合到晶体管的第一导电层。第一电介质层在第一导电层之上。第二导电层在第一介电层内，与第一导电层的顶表面的一部分接触。第二导电层包括在第一介电层的顶表面上方延伸的盖部分。第一介电隔离物在第一介电层和第二导电层之间。相变材料层在第二导电层的顶表面之上。第三导电层在相变材料层之上。第二电介质层在第一介电层上。第二电介质间隔物位于帽部分的侧壁上，其中第二电介质间隔物的热导率小于第一电介质层或第二电介质层的热导率。

60. 发明授权

US07682963B2 Air gap for interconnect application 有权
标题翻译：互连应用的气隙
公开(公告)号：US07682963B2
公开(公告)日：2010-03-23
申请号：US11867308
申请日：2007-10-04
申请人： Hai-Ching Chen , Sunil Kumar Singh , Tien-I Bao , Shau-Lin Shue , Chen-Hua Yu
发明人： Hai-Ching Chen , Sunil Kumar Singh , Tien-I Bao , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method for fabricating an integrated circuit. The method includes forming an energy removable film (ERF) on a substrate; forming a first dielectric layer on the ERF; patterning the ERF and first dielectric layer to form a trench in the ERF and the first dielectric layer; filling a conductive material in the trench; forming a ceiling layer on the first dielectric layer and conductive material filled in the trench; and applying energy to the ERF to form air gaps in the ERF after the forming of the ceiling layer.
摘要翻译：本公开提供了一种用于制造集成电路的方法。该方法包括在基板上形成能量可去除膜（ERF）; 在ERF上形成第一介电层; 图案化ERF和第一介电层以在ERF和第一介电层中形成沟槽; 在沟槽中填充导电材料; 在第一介电层上形成顶层和填充在沟槽中的导电材料; 并且在形成天花板层之后，向ERF施加能量以在ERF中形成气隙。

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