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51. 发明申请

US20110096824A1 MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER HAVING A SINGLE-STATE DECISION FEEDBACK EQUALIZER 有权
标题翻译：具有单一状态决定反馈均衡器的多对智能电网收发器
公开(公告)号：US20110096824A1
公开(公告)日：2011-04-28
申请号：US12876807
申请日：2010-09-07
申请人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H04L27/06
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

52. 发明申请

US20100309963A1 MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER HAVING ADAPTIVE DISABLING OF CIRCUIT ELEMENTS 失效
标题翻译：具有自适应电路元件的多对智能电网收发器
公开(公告)号：US20100309963A1
公开(公告)日：2010-12-09
申请号：US12796431
申请日：2010-06-08
申请人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H04B15/00 , H03H7/30 , H04B1/38
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

53. 发明申请

US20100135371A1 DYNAMIC REGULATION OF POWER CONSUMPTION OF A HIGH-SPEED COMMUNICATION SYSTEM 审中-公开
标题翻译：高速通信系统功耗的动态调节
公开(公告)号：US20100135371A1
公开(公告)日：2010-06-03
申请号：US12610787
申请日：2009-11-02
申请人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , Henry Samueli
发明人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , Henry Samueli
IPC分类号： H04B1/38 , H04L27/01
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： A method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric and a second metric, which are respectively related to a first performance parameter and a second performance parameter of the integrated circuit, are defined. The first metric is set at a pre-defined value. Selected blocks of the multiplicity of processing blocks are disabled in accordance with a set of pre-determined patterns. The second metric is evaluated, while the disabling operation is being performed, to generate a range of values of the second metric. Each of the values corresponds to the pre-defined value of the first metric. A most desirable value of the second metric is determined from the range of values and is matched to a corresponding pre-determined pattern. The integrated circuit is subsequently operated with selected processing blocks disabled in accordance with the matching pre-determined pattern.
摘要翻译：一种用于动态地调节包括多个处理块的高速集成电路的功耗的方法。定义分别与集成电路的第一性能参数和第二性能参数相关的第一度量和第二度量。第一个度量值设置为预定义值。多个处理块的选定块根据一组预先确定的模式被禁用。在执行禁用操作的同时评估第二度量，以生成第二度量值的范围。每个值对应于第一个度量的预定义值。从值的范围确定第二度量的最理想值，并且与对应的预定模式匹配。随后，根据匹配的预定模式禁用选定的处理块来操作集成电路。

54. 发明授权

US07671681B2 Gigabit ethernet transceiver with analog front end 有权
标题翻译：具有模拟前端的千兆以太网收发器
公开(公告)号：US07671681B2
公开(公告)日：2010-03-02
申请号：US10282688
申请日：2002-10-29
申请人： Arya R. Behzad , Klaas Bult , Ramon A. Gomez , Chi-Hung Lin , Tom W. Kwan , Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Arya R. Behzad , Klaas Bult , Ramon A. Gomez , Chi-Hung Lin , Tom W. Kwan , Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03G3/10
CPC分类号： H03F1/32 , H03F3/347 , H03F3/505 , H03F2200/211 , H03F2200/252 , H03F2200/421 , H03F2200/513 , H03G1/0088 , H03G3/001 , H03G3/3036 , H03G3/3052 , H03G5/10 , H03H11/245
摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.
摘要翻译：电路从集成电路可编程增益衰减器中的信号路径中去除开关。可编程增益衰减器和可编程增益放大器通常使用半导体开关在信号电平之间切换。这种开关可能在信号中引入非线性。通过将开关与信号路径隔离，可以提高PGA的线性度。

55. 发明授权

US07559204B2 Peltier system with water purification means 失效
标题翻译：珀尔帖系统采用水净化手段
公开(公告)号：US07559204B2
公开(公告)日：2009-07-14
申请号：US11799622
申请日：2007-05-02
申请人： Mehdi Hatamian , Mehrtosh A. Ghalebi
发明人： Mehdi Hatamian , Mehrtosh A. Ghalebi
IPC分类号： F25B21/02
CPC分类号： F24F5/0042 , E03B3/28 , F24F2003/1446 , Y02A20/109
摘要： An improved water generating device is provided for extracting water vapor from ambient air circulated therethrough. The device comprises an air pathway, a fan, a peltier module, a collection reservoir, and a heat sink. The air pathway defines first and second sections. A cold side of the peltier module is disposed in the first section and a hot side of the peltier module, whereto the heat sink is attached, is disposed in the second section of the peltier module. The fan draws the ambient air into the air pathway, and the cold side of the peltier module extracts water vapor out of the ambient air, which collects as water in the collection reservoir. The heat sink is partially disposable in the water and also includes a capillary tube which draws the water thereinto. Additional water vapor is extracted from the air, creating substantially dry air.
摘要翻译：提供了一种改进的产水装置，用于从循环的环境空气中提取水蒸气。该装置包括空气通道，风扇，珀耳帖模块，收集容器和散热器。空气通道限定第一和第二部分。珀尔帖模块的冷侧设置在第一部分中，并且佩戴者模块的热侧安装散热片，设置在珀耳帖模块的第二部分中。风扇将环境空气吸入空气通道，珀尔帖模块的冷侧将水蒸气从室外空气中抽出，这些空气以收集容器中的水的形式收集。散热器在水中是部分一次性的，并且还包括将水吸入其中的毛细管。从空气中提取额外的水蒸气，产生基本上干燥的空气。

56. 发明授权

US07466751B2 System and method for high-speed decoding and ISI compensation in a multi-pair transceiver system 失效
标题翻译：多对收发器系统中的高速解码和ISI补偿的系统和方法
公开(公告)号：US07466751B2
公开(公告)日：2008-12-16
申请号：US11204534
申请日：2005-08-16
申请人： Oscar E. Azazzi , David Kruse , Arthur Abnous , Mehdi Hatamian
发明人： Oscar E. Azazzi , David Kruse , Arthur Abnous , Mehdi Hatamian
IPC分类号： H03H7/30
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H03M13/256 , H03M13/41 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/0059 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03203 , H04L25/03267 , H04L25/03324 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03458 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03643 , H04L2025/03745
摘要： A method and a system for providing ISI compensation to an input signal in a bifurcated manner. ISI compensation is provided in two stages, a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel. First stage ISI compensation is performed in an inverse response filter having a characteristic feedback gain factor K, during system start-up. Second stage ISI compensation is performed by a single DFE in combination with a MDFE operating on tentative decisions output from a Viterbi decoder. As the DFE of the second stage reaches convergence, the feedback gain factor K of the first stage is ramped to zero.
摘要翻译：一种用于以分叉方式向输入信号提供ISI补偿的方法和系统。 ISI补偿分两阶段提供，第一级补偿由发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由多对传输信道的特性引起的ISI分量。在系统启动期间，在具有特性反馈增益因子K的逆响应滤波器中执行第一级ISI补偿。第二级ISI补偿由单个DFE与由维特比解码器输出的暂定决定操作的MDFE组合执行。当第二级的DFE达到收敛时，第一级的反馈增益因子K变为零。

57. 发明授权

US07453935B2 Multi-pair gigabit ethernet transceiver having decision feedback equalizer 有权
标题翻译：具有判决反馈均衡器的多对千兆以太网收发器
公开(公告)号：US07453935B2
公开(公告)日：2008-11-18
申请号：US11688669
申请日：2007-03-20
申请人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

58. 发明申请

US20080197645A1 Multi-component container system and method for manufacturing the same 失效
标题翻译：多部件容器系统及其制造方法
公开(公告)号：US20080197645A1
公开(公告)日：2008-08-21
申请号：US11708404
申请日：2007-02-20
申请人： Mehdi Hatamian , Mehrtosh Ghalebi
发明人： Mehdi Hatamian , Mehrtosh Ghalebi
IPC分类号： B65F1/12
CPC分类号： B65F1/02 , B65F1/122 , B65F1/1468 , B65F2220/12 , Y10S220/908
摘要： An improved multi-modular waste container formed at least in part from molded structural-foam. Per conventional waste containers, the improved waste container includes a housing for receiving trash, which will preferably be disposed upon one or more casters. One or more lids are hingeingly engaged to the top perimeter of the housing to provided selective access to the trash receptacle. Detachably fastenable slots may be affixed to opposed sides of the housing to facilitate engagement with and emptying by front-loading garbage trucks. The improved waste containers are substantially lighter, easier to maintain, stronger, chemical and corrosion resistant and possess substantially greater sound deadening characteristics than prior art waste containers fabricated from metal. The container housings are further preferably configured to be stacked within one another to facilitate shipping and handling thereof.
摘要翻译：改进的多模块废物容器至少部分地由模制结构泡沫形成。根据常规废物容器，改进的废物容器包括用于接收垃圾的壳体，其优选地设置在一个或多个脚轮上。一个或多个盖铰接地接合到壳体的顶部周边以提供对垃圾容器的选择性接近。可拆卸的紧固槽可以固定在壳体的相对侧上，以便于与前装垃圾车接合和排空。改进的废物容器比现有技术的由金属制成的废物容器显着更轻，更易于维护，更强，化学和耐腐蚀，并具有显着更大的隔音特性。容器壳体进一步优选地构造成彼此堆叠以便于运输和处理。

59. 发明申请

US20080164204A1 Valve for facilitating and maintaining separation of fluids and materials 审中-公开
标题翻译：用于促进和维持流体和材料分离的阀
公开(公告)号：US20080164204A1
公开(公告)日：2008-07-10
申请号：US11650734
申请日：2007-01-08
申请人： Mehdi Hatamian , Mehrtosh Ghalebi , Matin Ebneshahrashoob
发明人： Mehdi Hatamian , Mehrtosh Ghalebi , Matin Ebneshahrashoob
IPC分类号： B01D43/00 , B01L11/00
CPC分类号： B01L3/5021 , B01L2400/0605 , B01L2400/0633
摘要： Some embodiments include a valve positioned within a test tube to maintain a separation between components of liquid with different densities after centrifugation. The valve preferably includes a cylindrically shaped housing with a conical plug configured to nest within the housing. The plug is not in contact with the housing during centrifugation, but comes into position post-centrifugation.
摘要翻译：一些实施方案包括位于试管内的阀，以在离心后保持不同密度的液体组分之间的分离。阀优选地包括圆柱形壳体，其具有构造成嵌套在壳体内的锥形塞子。在离心过程中，塞子不与壳体接触，但在离心后进入位置。

60. 发明申请

US20080032798A1 Live card playing station 审中-公开
标题翻译：现场卡播放台
公开(公告)号：US20080032798A1
公开(公告)日：2008-02-07
申请号：US11491311
申请日：2006-07-21
申请人： Mehdi Hatamian , Hassan Moshrefazad Tehrani
发明人： Mehdi Hatamian , Hassan Moshrefazad Tehrani
IPC分类号： A63F9/24
CPC分类号： G07F17/3293 , G07F17/32
摘要： A system and method for enabling an individual to remotely participate in an actual casino card game, such as Poker, Blackjack and the like. A card playing station is provided that is integrated or interconnected with a conventional card table that is capable of being operatively interconnected to a remote computer via a secure, preferably web-based communications link. The card playing station is provided with means such as web cams to view the casino environment and enable the participant to remotely interact with the dealer and other players. The card playing station is further provided with means for receiving, reading and discharging playing cards, as well as waging bets and tallying gains and/or losses. The systems and methods thus enable the participant to actually play in a conventional casino-style environment and further afford the participant the opportunity to participate in gaming in virtually any casino throughout the world.
摘要翻译：一种用于使个人远程参与诸如扑克，二十一点等实际赌场牌游戏的系统和方法。提供了一种卡片播放台，其与能够经由安全的，优选基于网络的通信链路可操作地互连到远程计算机的常规卡片表集成或互连。卡片播放台被提供有诸如网络摄像头的手段来观看娱乐场环境，并使参与者能够与经销商和其他玩家远程交互。卡片播放台还设有用于接收，读取和放出扑克牌的手段，以及下注和统计收益和/或损失。因此，系统和方法使参与者能够在传统的赌场式环境中实际玩耍，并进一步为参与者提供在世界各地几乎任何赌场参与游戏的机会。

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