专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20140019655A1 SINGLE CYCLE ARBITRATION 有权
标题翻译：单循环仲裁
公开(公告)号：US20140019655A1
公开(公告)日：2014-01-16
申请号：US13940915
申请日：2013-07-12
申请人： Supreet Jeloka , Sandunmalee Nilmini Abeyratne , Ronald George Dreslinski , Reetuparna Das , Trevor Nigel Mudge , David Theodore Blaauw
发明人： Supreet Jeloka , Sandunmalee Nilmini Abeyratne , Ronald George Dreslinski , Reetuparna Das , Trevor Nigel Mudge , David Theodore Blaauw
IPC分类号： G06F13/374
CPC分类号： G06F13/4022 , G06F13/1642 , G06F13/374 , G06F2213/0038 , G11C7/10 , G11C7/1012 , H03K17/693
摘要： An interconnect 6 within an integrated circuit 2 provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).
摘要翻译：集成电路2内的互连6提供仲裁以选择用于连接到信号输出的多个信号输入中的一个。应用的仲裁使用时间戳值形式的第一仲裁参数值，并且如果两个或更多个信号输入共享这样的时间戳值，则使用第二仲裁参数，其形式为最近最近授予的值。选择应用于与授予对信号输出的访问时的每个信号输入相关联的时间戳值的时间增量以反映与该信号输入相关联的服务质量。当在时间戳值之间进行比较时，优先考虑最低时间戳值。大的时间增量值对应于低优先级（服务质量）。

52. 发明授权

US08346832B2 Random number generator 失效
标题翻译：随机数发生器
公开(公告)号：US08346832B2
公开(公告)日：2013-01-01
申请号：US11826996
申请日：2007-07-19
申请人： Trevor Nigel Mudge , David Theodore Blaauw , Carlos Alfonso Tokunaga
发明人： Trevor Nigel Mudge , David Theodore Blaauw , Carlos Alfonso Tokunaga
IPC分类号： G06F1/02 , G06F7/58
CPC分类号： G06F7/588 , H04L9/0866
摘要： A circuit for generating a random output value is disclosed that comprises: a bistable circuit having two stable states in which a 0 or a 1 is output and having a balanced metastable state in which a floating value between 0 and 1 is output, said bistable circuit resolving from said metastable state to one of said stable states on being switched on, said state depending on a voltage level at a port on said bistable circuit; a voltage level control circuit for controlling a voltage level at said port on said bistable circuit; a time measuring circuit for measuring a switching time taken for said bistable circuit to switch from said metastable state to one of said stable states following switch on; and control logic for controlling said time measuring circuit, said voltage level control circuit and a switching off and on of said bistable circuit, said control logic being adapted to perform a following sequence: control said voltage level control circuit to set a predetermined voltage level at said port on said bistable circuit, switch said bistable circuit on, detect a measured switching time, and turn said bistable circuit off and if said measured switching time is longer than a predetermined value, output said resolved stable state of said bistable circuit as said random output value.
摘要翻译：公开了一种用于产生随机输出值的电路，包括：双稳态电路，具有两个稳定状态，其中输出0或1，并且具有输出浮点值在0和1之间的平衡亚稳态，所述双稳态电路在所述稳定状态下从所述稳定状态分解成所述稳定状态之一被接通，所述状态取决于所述双稳态电路上的端口处的电压电平; 电压电平控制电路，用于控制所述双稳态电路上的所述端口处的电压电平; 时间测量电路，用于测量所述双稳态电路在接通之后从所述亚稳态转换到所述稳定状态之一所需的切换时间; 以及用于控制所述时间测量电路，所述电压电平控制电路和所述双稳态电路的断开和接通的控制逻辑，所述控制逻辑适于执行以下顺序：控制所述电压电平控制电路以将预定电压电平设置在所述双稳态电路上的所述端口，打开所述双稳态电路，检测测量的开关时间，并关闭所述双稳态电路，如果所述测量的开关时间长于预定值，则将所述双稳态电路的所述分辨稳定状态输出为所述随机产值。

53. 发明授权

US08103922B2 Error detection in precharged logic 有权
标题翻译：预充电逻辑中的误差检测
公开(公告)号：US08103922B2
公开(公告)日：2012-01-24
申请号：US13162308
申请日：2011-06-16
申请人： David Michael Bull , Shidhartha Das , David Theodore Blaauw
发明人： David Michael Bull , Shidhartha Das , David Theodore Blaauw
IPC分类号： G11C29/00
CPC分类号： G01R31/3177
摘要： An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry have appropriate values. Error detection circuitry detects an error when the speculative node and the checker node are not one of both discharged or both undischarged.
摘要翻译：集成电路提供有多米诺逻辑，包括推测节点和检查器节点。预充电电路对推测节点和检查器节点进行预充电。逻辑电路根据输入信号值为推测节点和校验器节点提供放电路径。评估控制电路首先将推测节点耦合到逻辑电路，然后随后将校验器节点耦合到逻辑电路，使得如果逻辑电路的输入信号具有适当的值，则它们可以被放电。当推测节点和检查器节点都不是放电或未放电的两者之一时，错误检测电路检测到错误。

54. 发明授权

US08060814B2 Error recovery within processing stages of an integrated circuit 有权
标题翻译：集成电路处理阶段内的错误恢复
公开(公告)号：US08060814B2
公开(公告)日：2011-11-15
申请号：US12461740
申请日：2009-08-21
申请人： David Theodore Blaauw , Shidhartha Das , Todd Michael Austin
发明人： David Theodore Blaauw , Shidhartha Das , Todd Michael Austin
IPC分类号： G06F11/00
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024.非延迟信号捕获元件1016捕获来自处理逻辑1014处于非延迟捕获时间。在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。错误检测电路1026和纠错电路1028检测并校正延迟值中的随机误差并提供错误检查的延迟比较器1024比较错误检查的延迟值和非延迟值，并且如果它们不相等，则这表示非延迟值被太早捕获，并且应该被错误检查的延迟值替换值。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

55. 发明申请

US20110246843A1 ERROR DETECTION IN PRECHARGED LOGIC 有权
标题翻译：预置逻辑中的错误检测
公开(公告)号：US20110246843A1
公开(公告)日：2011-10-06
申请号：US13162308
申请日：2011-06-16
申请人： David Michael BULL , Shidhartha Das , David Theodore Blaauw
发明人： David Michael BULL , Shidhartha Das , David Theodore Blaauw
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177
摘要： An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry have appropriate values. Error detection circuitry detects an error when the speculative node and the checker node are not one of both discharged or both undischarged.
摘要翻译：集成电路提供有多米诺逻辑，包括推测节点和检查器节点。预充电电路对推测节点和检查器节点进行预充电。逻辑电路根据输入信号值为推测节点和校验器节点提供放电路径。评估控制电路首先将推测节点耦合到逻辑电路，然后随后将校验器节点耦合到逻辑电路，使得如果逻辑电路的输入信号具有适当的值，则它们可以被放电。当推测节点和检查器节点都不是放电或未放电的两者之一时，错误检测电路检测到错误。

56. 发明申请

US20090244971A1 Memory cell structure, a memory device employing such a memory cell structure, and an integrated circuit having such a memory device 有权
标题翻译：存储单元结构，采用这种存储单元结构的存储器件，以及具有这种存储器件的集成电路
公开(公告)号：US20090244971A1
公开(公告)日：2009-10-01
申请号：US12078547
申请日：2008-04-01
申请人： Yoonmyung Lee , Michael John Wieckowski , David Theodore Blaauw , Dennis Michael Chen Sylvester
发明人： Yoonmyung Lee , Michael John Wieckowski , David Theodore Blaauw , Dennis Michael Chen Sylvester
IPC分类号： G11C16/06 , G11C11/24
CPC分类号： G11C16/0416 , G11C16/0441 , G11C2216/10 , H01L27/0629 , H01L27/0805 , H01L27/11521 , H01L27/11526 , H01L27/11558 , H01L28/40
摘要： A memory cell structure for a memory device is provided, the memory cell structure comprising a read transistor having a floating gate node, a tunnelling capacitor, and a coupling capacitor stack. The tunnelling capacitor is connected to the floating gate node and has a first programming terminal, whilst the coupling capacitor stack is connected to the floating gate node and has a second programming terminal. The coupling capacitor stack comprises at least two coupling capacitors arranged in series between the floating gate node and the second programming terminal, with the coupling capacitor stack having a larger capacitance than the tunnelling capacitor. During a programming operation, a voltage difference is established between the first programming terminal and the second programming terminal to cause charge tunnelling to occur through the tunnelling capacitor, such that after the programming operation a charge is stored in the floating gate node. During a read operation, the read transistor is activated to produce an output signal indicative of the charge stored in the floating gate node. Such a memory cell structure is efficient in terms of area, and can be manufactured using standard CMOS logic manufacturing processes, thereby avoiding some of the complexities involved in the production of more conventional EEPROM and Flash memory devices.
摘要翻译：提供了一种用于存储器件的存储单元结构，所述存储单元结构包括具有浮置栅极节点的读取晶体管，隧穿电容器和耦合电容器堆叠。隧道电容器连接到浮动栅极节点并且具有第一编程端子，而耦合电容器堆叠件连接到浮动栅极节点并且具有第二编程端子。耦合电容器堆叠包括串联布置在浮动栅极节点和第二编程端子之间的至少两个耦合电容器，耦合电容器堆叠具有比隧道电容器更大的电容。在编程操作期间，在第一编程终端和第二编程终端之间建立电压差以通过隧穿电容器进行电荷隧穿，使得在编程操作之后，电荷被存储在浮动栅节点中。在读取操作期间，读取晶体管被激活以产生指示存储在浮动栅极节点中的电荷的输出信号。这样的存储单元结构在面积方面是有效的，并且可以使用标准CMOS逻辑制造工艺来制造，从而避免了生产更常规的EEPROM和闪存器件的一些复杂性。

57. 发明申请

US20090138658A1 Cache memory system for a data processing apparatus 有权
标题翻译：用于数据处理装置的高速缓冲存储器系统
公开(公告)号：US20090138658A1
公开(公告)日：2009-05-28
申请号：US12292148
申请日：2008-11-12
申请人： Ronald George Dreslinski, JR. , Gregory Kengho Chen , Trevor Nigel Mudge , David Theodore Blaauw , Dennis Sylvester
发明人： Ronald George Dreslinski, JR. , Gregory Kengho Chen , Trevor Nigel Mudge , David Theodore Blaauw , Dennis Sylvester
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0864 , G06F2212/1028 , Y02D10/13
摘要： A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided.
摘要翻译：提供一种数据处理装置，其具有包括数据存储阵列和标签阵列的高速缓存存储器，以及响应于来自处理电路执行高速缓存查找的高速缓存访问请求而耦合到高速缓冲存储器的高速缓存控制器。高速缓冲存储器被布置成使得其具有被配置为在第一电压域中操作的第一存储单元组和被配置为在不同于第一电压域的第二电压域中操作的第二存储单元组。还提供了相应的数据处理方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式