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    • 52. 发明授权
    • Booster circuit
    • 增压电路
    • US4704706A
    • 1987-11-03
    • US850330
    • 1986-04-11
    • Masao NakanoYoshihiro TakemaeKimiaki SatoNobumi Kodama
    • Masao NakanoYoshihiro TakemaeKimiaki SatoNobumi Kodama
    • H03K19/096G11C5/14G11C8/08H03K17/06G11C7/00
    • G11C8/08
    • A booster circuit including a precharge capacitor (C.sub.2), a precharge driver circuit (20) having a first bootstrap circuit (C.sub.59, Q.sub.58, Q.sub.61) and precharging a voltage to the precharge capacitor in a reset mode, and an output driver circuit (19) having a switching circuit (Q.sub.21) for cutting off the output of the precharged voltage of the precharged capacitor in the reset mode and a second bootstrap circuit driving the switching circuit in an operation mode. The booster circuit further includes an additional switching circuit (Q.sub.1) for outputting a voltage to be superimposed onto the precharge voltage in the operation mode.The booster circuit may be applicable to a dynamic semiconductor memory device, for boosting a voltage of a word line at a high speed and for improving integration.
    • 一种升压电路,包括预充电电容器(C2),具有第一自举电路(C59,Q58,Q61)的预充电驱动电路(20),并且在复位模式下向预充电电容器预充电,以及输出驱动器电路 )具有用于在复位模式下切断预充电电容器的预充电电压的输出的开关电路(Q21)和在操作模式下驱动开关电路的第二自举电路。 升压电路还包括用于在操作模式中输出要叠加到预充电电压上的电压的附加开关电路(Q1)。 升压电路可以适用于动态半导体存储器件,用于高速提升字线的电压并改善集成度。
    • 56. 发明授权
    • Decoder circuit
    • 解码电路
    • US4185320A
    • 1980-01-22
    • US964186
    • 1978-11-28
    • Yoshihiro TakemaeMasao Nakano
    • Yoshihiro TakemaeMasao Nakano
    • G11C11/413G11C11/408H03K19/096H03M5/02H03M7/00G11C11/40
    • G11C11/4087H03M7/005
    • Disclosed herein is a decoder circuit including: a charge up transistor for maintaining the content of input address signals; a power supply switching transistor for controlling a charge up current which is supplied to the charge up transistor; a predetermined number of selection transistors which are connected at a connection node between the charge up transistor and the power supply switching transistor for selecting an output word line, and; a bootstrap transistor which is connected at an opposide side of the connection node with respect to the charge up transistor. The characteristic feature of the present invention is the provision of a charge compensation transistor which is connected at a connection node between the charge up transistor and the power supply switching transistor so as to compensate for the charges of the charge up transistor.
    • 这里公开了一种解码器电路,包括:用于维持输入地址信号的内容的充电晶体管; 用于控制提供给充电晶体管的充电电流的电源开关晶体管; 预定数量的选择晶体管,其连接在充电晶体管和用于选择输出字线的电源开关晶体管之间的连接节点处; 一个自举晶体管,其连接在连接节点的相对于充电晶体管的相对侧。 本发明的特征在于提供一种电荷补偿晶体管,其连接在充电晶体管和电源开关晶体管之间的连接节点处,以补偿充电晶体管的电荷。