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1. 发明授权

US4291394A Semiconductor memory device having flip-flop circuits 失效
标题翻译：具有触发电路的半导体存储器件
公开(公告)号：US4291394A
公开(公告)日：1981-09-22
申请号：US87389
申请日：1979-10-22
申请人： Masao Nakano , Tomio Nakano , Yoshihiro Takemae , Katsuhiko Kabashima
发明人： Masao Nakano , Tomio Nakano , Yoshihiro Takemae , Katsuhiko Kabashima
IPC分类号： G11C11/419 , G11C5/06 , G11C11/409 , G11C11/4096 , G11C11/4099 , H03K3/356 , G11C11/40
CPC分类号： G11C5/063 , G11C11/4096 , G11C11/4099
摘要： A semiconductor memory device having flip-flop circuits, in which first and second bit lines are connected to each of the flip-flop circuits as a sense amplifier, the potential of the second bit line being opposite to the potential of the first bit line, and the first and second data bus lines cross perpendicularly to the first and second bit lines, respectively, the first and second dummy lines are arranged in parallel with the first and second data bus lines respectively, in order to prevent erroneous operation of an I/O amplifier connected to the first and second data bus lines.
摘要翻译：一种具有触发电路的半导体存储器件，其中第一和第二位线连接到作为读出放大器的每个触发器电路，第二位线的电位与第一位线的电位相反，并且第一和第二数据总线分别与第一和第二位线垂直交叉，第一和第二虚拟线分别与第一和第二数据总线线并排布置，以防止I / O放大器连接到第一和第二数据总线。

2. 发明授权

US4336465A Reset circuit 失效
标题翻译：复位电路
公开(公告)号：US4336465A
公开(公告)日：1982-06-22
申请号：US61252
申请日：1979-07-27
申请人： Masao Nakano , Yoshihiro Takemae , Katsuhiko Kabashima
发明人： Masao Nakano , Yoshihiro Takemae , Katsuhiko Kabashima
IPC分类号： G11C11/41 , G11C7/10 , G11C7/20 , G11C11/409 , G11C11/4093 , G11C11/417 , G11C11/419 , H03K3/356 , H03K5/00
CPC分类号： G11C11/4093 , G11C7/1048 , G11C7/20 , H03K3/356095
摘要： A reset circuit used for resetting, for example a memory device after a reading-out from a memory is effected, comprises fist and second reset transistors, for connecting first and second circuits to a common voltage source, and a short-circuit transistor, having a lower threshold voltage than the threshold voltage of said first and second reset transistors, for connecting said first and second circuits when said short circuit transistor receives the same input signal as supplied to said first and second reset transistors.
摘要翻译：用于复位的复位电路，例如在从存储器读出数据之后，存储器件包括用于将第一和第二电路连接到公共电压源的第一和第二复位晶体管，以及短路晶体管，具有比所述第一和第二复位晶体管的阈值电压低的阈值电压，用于当所述短路晶体管接收与提供给所述第一和第二复位晶体管相同的输入信号时连接所述第一和第二电路。

3. 发明授权

US4551822A Dynamic semiconductor memory device 失效
标题翻译：动态半导体存储器件
公开(公告)号：US4551822A
公开(公告)日：1985-11-05
申请号：US447677
申请日：1982-12-07
申请人： Yoshihiro Takemae , Katsuhiko Kabashima
发明人： Yoshihiro Takemae , Katsuhiko Kabashima
IPC分类号： G11C29/00 , G11C11/401 , G11C11/403 , G11C11/406 , G11C29/02 , G11C29/08 , G11C29/56 , G11C11/40
CPC分类号： G11C11/406 , G11C29/02
摘要： A dynamic semiconductor memory device having a refresh-address generator, includes an initial resetting circuit for resetting the output signals of a refresh-address counter when the power supply is turned on, thereby eliminating the need for counter checking procedures prior to the examination of the refresh-address generator.
摘要翻译：一种具有刷新地址发生器的动态半导体存储器件，包括一个初始复位电路，用于在电源接通时复位刷新地址计数器的输出信号，从而在检查之前消除了对检查程序的需要刷新地址生成器。

4. 发明授权

US4550289A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4550289A
公开(公告)日：1985-10-29
申请号：US453115
申请日：1982-12-27
申请人： Katsuhiko Kabashima , Yoshihiro Takemae , Shigeki Nozaki , Tsuyoshi Ohira , Hatsuo Miyahara , Masakazu Kanai , Seiji Enomoto
发明人： Katsuhiko Kabashima , Yoshihiro Takemae , Shigeki Nozaki , Tsuyoshi Ohira , Hatsuo Miyahara , Masakazu Kanai , Seiji Enomoto
IPC分类号： G01R31/26 , G06F11/00 , H01L21/66 , H01L21/822 , H01L27/00 , H01L27/04 , G01R31/28
CPC分类号： G01R31/26 , G06F11/006
摘要： A semiconductor integrated circuit (IC) device includes therein a test circuit. The test circuit operates to distinguish the power source level during the testing or ground level occurring at an internal node located inside the semiconductor chip. The test circuit includes a series-connected MIS transistor and an MIS diode. The gate of the MIS transistor is connected to the internal node. The MIS diode is connected to an external input/output (I/O) pin. The level at the internal node, i.e., the power source level or the ground level, can be distinguished by a first voltage level or a second voltage level applied to the external I/O pin, whichever enables a current to be drawn from the external I/O pin.
摘要翻译：半导体集成电路（IC）装置包括测试电路。测试电路用于在测试期间区分电源电平或在位于半导体芯片内部的内部节点处发生地电平。测试电路包括串联连接的MIS晶体管和MIS二极管。 MIS晶体管的栅极连接到内部节点。 MIS二极管连接到外部输入/输出（I / O）引脚。可以通过施加到外部I / O引脚的第一电压电平或第二电压电平来区分内部节点的电平，即电源电平或接地电平，无论哪一个使外部电流从外部 I / O引脚。

5. 发明授权

US4496850A Semiconductor circuit for enabling a quick rise of the potential _on the word line for driving a clock signal line 失效
标题翻译：半导体电路，用于使字线上的电位快速上升以驱动时钟信号线
公开(公告)号：US4496850A
公开(公告)日：1985-01-29
申请号：US347465
申请日：1982-02-10
申请人： Yoshihiro Takemae , Shigeki Nozaki , Katsuhiko Kabashima , Seiji Enomoto
发明人： Yoshihiro Takemae , Shigeki Nozaki , Katsuhiko Kabashima , Seiji Enomoto
IPC分类号： G11C11/407 , G11C11/4076 , G11C11/408 , H03K5/02 , H03K17/06 , H03K19/094 , H03K17/04 , H03K17/693 , H03K19/017
CPC分类号： G11C11/4085 , G11C11/4076 , H03K5/023
摘要： A semiconductor circuit for driving a clock signal line comprising a first circuit for pulling up the potential of the clock signal line to the source voltage and a second circuit for pulling down the potential of the clock signal line to a lower voltage. A capacitor is connected to the clock signal line for receiving a potential push signal and pushing the potential of the clock signal line higher than the source voltage. The capacitor performs the function of capacitance only after the potential of the clock signal line is raised to the source voltage. The operational speed of a dynamic memory device associated with the semiconductor device is then enhanced.
摘要翻译：一种用于驱动时钟信号线的半导体电路，包括用于将时钟信号线的电位提升到源极电压的第一电路和用于将时钟信号线的电位下拉到较低电压的第二电路。电容器连接到时钟信号线，用于接收潜在的推送信号，并推动时钟信号线的电位高于源极电压。只有在时钟信号线的电位升高到电源电压之后，电容才能执行电容。然后增强与半导体器件相关联的动态存储器件的操作速度。

6. 发明授权

US4458337A Buffer circuit 失效
标题翻译：缓冲电路
公开(公告)号：US4458337A
公开(公告)日：1984-07-03
申请号：US354498
申请日：1982-03-03
申请人： Yoshihiro Takemae , Shigeki Nozaki , Tsutomu Mezawa , Katsuhiko Kabashima , Seiji Enomoto
发明人： Yoshihiro Takemae , Shigeki Nozaki , Tsutomu Mezawa , Katsuhiko Kabashima , Seiji Enomoto
IPC分类号： G11C11/413 , G11C11/408 , H03K3/356 , G11C13/00
CPC分类号： H03K3/356017 , H03K3/35606
摘要： A buffer circuit comprises a flip-flop which is receives an external input via a first input circuit and a reference voltage via a second input circuit. Internal complementary outputs are then produced via an output circuit. The flip-flop cooperates with at least one level setting device by way of a second input circuit. The level setting device functions to produce a voltage level to deactivate the second input circuit during activation of the flip-flop.
摘要翻译：缓冲电路包括经由第一输入电路接收外部输入的触发器和经由第二输入电路的参考电压。然后通过输出电路产生内部互补输出。触发器通过第二输入电路与至少一个电平设置装置协作。电平设置装置用于产生电压电平，以在触发器激活期间停用第二输入电路。

7. 发明授权

US4451908A Address Buffer 失效
标题翻译：地址缓冲区
公开(公告)号：US4451908A
公开(公告)日：1984-05-29
申请号：US354499
申请日：1982-03-03
申请人： Yoshihiro Takemae , Shigeki Nozaki , Katsuhiko Kabashima , Seiji Enomoto , Tsutomu Mezawa
发明人： Yoshihiro Takemae , Shigeki Nozaki , Katsuhiko Kabashima , Seiji Enomoto , Tsutomu Mezawa
IPC分类号： G11C11/403 , G11C11/406 , G11C11/408 , G11C11/40
CPC分类号： G11C11/4082 , G11C11/406
摘要： An address buffer for a dynamic memory includes a flip-flop. The flip-flop is coupled at its one input/output terminal with both a first input circuit and a third input circuit connected in parallel with each other and at its other input/output terminal with a second input circuit. The second input circuit receives a reference voltage and is activated by an external address timing clock during a normal operation mode. The first input circuit is also activated by the external address timing clock, but receives an external address. The third input circuit receives an internal refresh address and is activated by an internal refresh address. The address buffer cooperates with a switcher which produces the internal refresh address timing clock and the external address timing clock, alternatively, by switching a basic timing clock generated by an address drive clock generator.
摘要翻译：用于动态存储器的地址缓冲器包括触发器。触发器在其一个输入/输出端子处与第一输入电路和第三输入电路耦合，第一输入电路和第三输入电路彼此并联并且在其另一输入/输出端与第二输入电路连接。第二输入电路接收参考电压，并在正常操作模式期间由外部地址定时时钟激活。第一个输入电路也由外部地址定时时钟激活，但接收一个外部地址。第三输入电路接收内部刷新地址，并由内部刷新地址激活。地址缓冲器与产生内部刷新地址定时时钟和外部地址定时时钟的切换器配合，或者通过切换由地址驱动时钟发生器产生的基本定时时钟。

8. 发明授权

US4447745A Buffer circuit including a current leak circuit for maintaining the charged voltages 失效
标题翻译：缓冲电路包括用于维持充电电压的电流泄漏电路
公开(公告)号：US4447745A
公开(公告)日：1984-05-08
申请号：US322719
申请日：1981-11-18
申请人： Yoshihiro Takemae , Seiji Enomoto , Shigeki Nozaki , Tsutomu Mezawa , Katsuhiko Kabashima
发明人： Yoshihiro Takemae , Seiji Enomoto , Shigeki Nozaki , Tsutomu Mezawa , Katsuhiko Kabashima
IPC分类号： G11C11/417 , G06F1/04 , G11C11/407 , G11C11/4076 , G11C11/418 , H03K19/017 , H03K19/0185 , H03K19/096 , H03K5/135
CPC分类号： G11C11/4076 , G11C11/418 , H03K19/01735 , H03K19/01855
摘要： A semiconductor circuit used as a buffer circuit having an input stage circuit for receiving an input clock signal and an inverted input clock signal, a bootstrap circuit including a transistor for receiving the output of the input stage circuit and for maintaining the gate voltage of the transistor at a high level during the standby period, and an output circuit, including a transistor which is switched on and off by the output of the bootstrap circuit, for generating an output clock signal; the semiconductor circuit further comprising a current leak circuit for maintaining, during the standby period, the voltage of a point in the semiconductor circuit which is charged during the standby period at the value corresponding to the voltage of the power source, whereby the delay of the output clock signal, caused of the fluctuation by the voltage of the power supply during the standby period, is improved and then the high speed access time in the dynamic memory is carried out.
摘要翻译：一种用作缓冲电路的半导体电路，具有用于接收输入时钟信号和反相输入时钟信号的输入级电路，自举电路包括用于接收输入级电路的输出并保持晶体管的栅极电压的晶体管在待机期间处于高电平;以及输出电路，包括由所述自举电路的输出接通和断开的晶体管，用于产生输出时钟信号; 所述半导体电路还包括电流泄漏电路，用于在所述待机期间保持所述半导体电路中在所述待机期间中以与所述电源的电压对应的值被充电的点的电压，由此所述延迟在待机期间由电源的电压引起的输出时钟信号被提高，然后执行动态存储器中的高速访问时间。

9. 发明授权

US4156939A Integrated semiconductor memory device 失效
标题翻译：集成半导体存储器件
公开(公告)号：US4156939A
公开(公告)日：1979-05-29
申请号：US908836
申请日：1978-05-23
申请人： Yoshihiro Takemae , Takeo Tatematsu , Katsuhiko Kabashima , Tomio Nakano , Kiyoshi Miyasaka
发明人： Yoshihiro Takemae , Takeo Tatematsu , Katsuhiko Kabashima , Tomio Nakano , Kiyoshi Miyasaka
IPC分类号： G11C5/02 , G11C7/02 , G11C11/404 , G11C11/407 , H01L21/8242 , H01L27/088 , H01L27/10 , H01L27/105 , H01L27/108 , G11C11/40
CPC分类号： G11C11/404 , G11C11/407 , G11C5/025 , H01L27/088 , H01L27/10805 , H01L27/105
摘要： An integrated semiconductor memory device is formed on a semiconductor substrate of one conductivity type on which there are provided peripheral circuits consisting of a pluality of memory cells each containing a storage capacitor and an IG FET. The IG FET in each memory cell acts as a transfer gate which is disposed on a surface region having the same conductivity type as that of the substrate and higher impurity concentrations than that of the substrate. The transfer gate has a gate threshold value which is higher than that of the IG FET in the peripheral circuits and which is insensitive to a noise pulse supplied thereto, whereby the destruction of data by noise pulse can be effectively prevented.
摘要翻译：集成半导体存储器件形成在一种导电类型的半导体衬底上，其中提供由包含存储电容器和IG FET的存储单元的pluality组成的外围电路。每个存储单元中的IG FET用作传输门，其布置在具有与衬底相同的导电类型的表面区域上，并且具有比衬底更高的杂质浓度。传输门具有比周边电路中的IG FET高的栅极阈值，并且对提供给其的噪声脉冲不敏感，从而可以有效地防止数据噪声脉冲的破坏。

10. 发明授权

US4482825A Semiconductor device having a circuit for generating a voltage higher than a supply voltage and responsive to variations in the supply voltage 失效
标题翻译：具有用于产生高于电源电压的电压并且响应于电源电压的变化的电路的半导体器件
公开(公告)号：US4482825A
公开(公告)日：1984-11-13
申请号：US326899
申请日：1981-12-02
申请人： Shigeki Nozaki , Yoshihiro Takemae , Katsuhiko Kabashima , Seiji Enomoto
发明人： Shigeki Nozaki , Yoshihiro Takemae , Katsuhiko Kabashima , Seiji Enomoto
IPC分类号： H01L21/822 , G11C11/4074 , G11C11/4076 , G11C11/4094 , H01L21/82 , H01L23/52 , H01L23/58 , H01L27/04 , H03K17/06 , H01L27/02 , H03K17/14 , H03K17/16
CPC分类号： H01L23/58 , G11C11/4074 , G11C11/4076 , G11C11/4094 , H01L21/82 , H01L23/52 , H01L2924/0002
摘要： In a semiconductor device having a signal line on which a voltage higher than the voltage supply is generated, a conductive layer following the potential variance of the voltage supply is positioned under an insulating film directly below the signal line in order to make the level of the signal line follow the potential variance of the voltage supply.
摘要翻译：在具有高于电压源的电压的信号线的半导体器件中，与电压源的电位变化相反的导电层位于信号线正下方的绝缘膜的下方，信号线跟随电压的潜在变化。

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