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51. 发明申请

US20080229266A1 Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees 审中-公开
标题翻译：用于在集成电路时钟树中提供均衡负载的时钟分配网络，结构和方法的设计结构
公开(公告)号：US20080229266A1
公开(公告)日：2008-09-18
申请号：US12129773
申请日：2008-05-30
申请人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/62
摘要： Design structure for a clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.
摘要翻译：公开了用于提供平衡负载的时钟分配网络，结构和方法的设计结构。特别地，时钟分配网络可以由一个或多个时钟扇出分配级别形成。每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。

52. 发明申请

US20080186054A1 DESIGN STRUCTURE FOR A FLEXIBLE MULTIMODE LOGIC ELEMENT FOR USE IN A CONFIGURABLE MIXED-LOGIC SIGNAL DISTRIBUTION PATH 有权
标题翻译：用于可配置混合逻辑信号分配路径的灵活多模态逻辑单元的设计结构
公开(公告)号：US20080186054A1
公开(公告)日：2008-08-07
申请号：US11848470
申请日：2007-08-31
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H03K19/173
CPC分类号： H03K19/018585 , H03K3/35613 , H03K5/133 , H03K2005/00058 , H03K2005/00208 , H03K2005/00228
摘要： A design structure for a multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, a design structure for a exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译：公开了一种被配置为以多种操作模式之一操作的多模电路的设计结构。特别地，用于示例性多模电路的设计结构可以被配置为以全摆动模式，限定摆动模式，全摆幅至限定摆动转换器模式和限定摆动转换模式中的一种运行，摆动转换器模式。多模电路的工作模式可以动态地选择。一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。

53. 发明授权

US07403039B1 Flexible multimode logic element for use in a configurable mixed-logic signal distribution path 有权
公开(公告)号：US07403039B1
公开(公告)日：2008-07-22
申请号：US11670537
申请日：2007-02-02
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H03K19/0175
CPC分类号： H03K19/018585 , H03K3/35613 , H03K5/133 , H03K2005/00058 , H03K2005/00208 , H03K2005/00228
摘要： A multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.

54. 发明申请

US20080143416A1 Clock Distribution Network, Structure, And Method For Providing Balanced Loading In Integrated Circuit Clock Trees 失效
标题翻译：用于在集成电路时钟树中提供均衡负载的时钟分配网络，结构和方法
公开(公告)号：US20080143416A1
公开(公告)日：2008-06-19
申请号：US11610848
申请日：2006-12-14
申请人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Serafino Bueti , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F1/04 , G06F1/10
CPC分类号： G06F1/10
摘要： A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.
摘要翻译：公开了一种用于提供平衡负载的时钟分配网络，结构和方法。特别地，时钟分配网络可以由一个或多个时钟扇出分配级别形成。每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。

55. 发明授权

US07342429B2 Programmable low-power high-frequency divider 有权
标题翻译：可编程低功耗高分频器
公开(公告)号：US07342429B2
公开(公告)日：2008-03-11
申请号：US11325786
申请日：2006-01-05
申请人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
发明人： John S. Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号： H03K3/289
CPC分类号： H03K23/52 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/667
摘要： Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.
摘要翻译：描述了包括NAND门级和时钟反相器级和反相器级的组合的多个锁存电路。还描述了包括使用锁存电路的同步分频器电路的可编程分频器。还描述了同源分频器中包括的电路和用于校正由同系分频器产生的时钟信号的占空比为50％的方法。

56. 发明申请

US20060158237A1 Programmable low-power high-frequency divider 失效
标题翻译：可编程低功耗高分频器
公开(公告)号：US20060158237A1
公开(公告)日：2006-07-20
申请号：US11374766
申请日：2006-03-14
申请人： John Austin , Ram Kelkar , Pradeep Thiagarajan
发明人： John Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号： H03K3/356
CPC分类号： H03K23/667 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/52
摘要： A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.
摘要翻译：一种快速锁存器，包括：适于接收时钟信号和数据输入信号的NAND级; 时钟反相器级，被连接到NAND级的输出的时钟反相级的第一输入和与时钟信号耦合的时钟反相级的第二输入; 第一反相器级，耦合到所述时钟反相器的输出的第一反相器级的第一输入和耦合到复位信号的第一反相器级的第二输入; 以及第二反相器级，具有输出，所述第二反相器级的输入耦合到所述第一反相器级的输出。快速锁存器适用于还描述的分频器电路。还公开了使用快速锁存器的分频器的同系物，独特的3/4分频器和不使用快速锁存器的2分频器。

57. 发明申请

US20060109947A1 Programmable low-power high-frequency divider 有权
标题翻译：可编程低功耗高分频器
公开(公告)号：US20060109947A1
公开(公告)日：2006-05-25
申请号：US11325786
申请日：2006-01-05
申请人： John Austin , Ram Kelkar , Pradeep Thiagarajan
发明人： John Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号： H03K21/00
CPC分类号： H03K23/52 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/667
摘要： Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.
摘要翻译：描述了包括NAND门级和时钟反相器级和反相器级的组合的多个锁存电路。还描述了包括使用锁存电路的同步分频器电路的可编程分频器。还描述了同源分频器中包括的电路和用于校正由同系分频器产生的时钟信号的占空比为50％的方法。

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