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51. 发明授权

US07409503B2 Register file systems and methods for employing speculative fills 失效
标题翻译：注册文件系统和采用投机填充的方法
公开(公告)号：US07409503B2
公开(公告)日：2008-08-05
申请号：US10756644
申请日：2004-01-13
申请人： Simon C. Steely, Jr. , Gregory Edward Tierney
发明人： Simon C. Steely, Jr. , Gregory Edward Tierney
IPC分类号： G06F9/00 , G06F9/38 , G06F13/00
CPC分类号： G06F12/0862
摘要： Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a multi-processor system with a processor having a processor pipeline that executes program instructions with data from speculative fills that are provided in response to source requests. The multi-processor system may comprise a first register file that retains register values associated with program instruction employing data from speculative fills, and a second register file that retains register values associated with data from speculative fills that have been determined to be coherent.
摘要翻译：提供多处理器系统和方法。一个实施例涉及一种多处理器系统，其可以包括具有处理器的多处理器系统，处理器具有处理器流水线，该处理器流水线通过响应于源请求而提供的来自投机填充的数据执行程序指令。多处理器系统可以包括第一寄存器文件，其保留与从推测填充中采用数据的程序指令相关联的寄存器值，以及第二寄存器文件，其保留与已被确定为相干的来自投机填充的数据相关联的寄存器值。

52. 发明授权

US07383409B2 Cache systems and methods for employing speculative fills 失效
标题翻译：缓存系统和采用投机填充的方法
公开(公告)号：US07383409B2
公开(公告)日：2008-06-03
申请号：US10756638
申请日：2004-01-13
申请人： Simon C. Steely, Jr. , Gregory Edward Tierney
发明人： Simon C. Steely, Jr. , Gregory Edward Tierney
IPC分类号： G06F9/00 , G06F9/38 , G06F13/00
CPC分类号： G06F12/0831 , G06F2212/507
摘要： One disclosed embodiment is a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in response to a source request. The multi-processor system can further comprise a non-retired store cache that retains non-retired store data based on program instructions to store data into a data cache associated with the processor. The non-retired store data can be written to the data cache if data of a speculative fill associated with the non-retired store data is determined to be coherent. Other apparatus and methodologies are disclosed.
摘要翻译：一个公开的实施例是一种多处理器系统，其包括具有处理器流水线的处理器，处理器流水线通过来自响应于源请求而提供的推测填充的数据来执行程序指令。多处理器系统还可以包括非退休存储高速缓存，其基于程序指令保留非退休存储数据，以将数据存储到与处理器相关联的数据高速缓存中。如果与非退休存储数据相关联的推测填充的数据被确定为相干，则可以将非退休存储数据写入数据高速缓存。公开了其他装置和方法。

53. 发明授权

US07237067B2 Managing a multi-way associative cache 有权
标题翻译：管理多路关联缓存
公开(公告)号：US07237067B2
公开(公告)日：2007-06-26
申请号：US10829186
申请日：2004-04-22
申请人： Simon C. Steely, Jr.
发明人： Simon C. Steely, Jr.
IPC分类号： G06F12/00
CPC分类号： G06F12/128
摘要： Methods for storing replacement data in a multi-way associative cache are disclosed. One method comprises logically dividing the cache's cache sets into segments of at least one cache way; searching a cache set in accordance with a segment search sequence for a segment currently comprising a way which has not yet been accessed during a current cycle of the segment search sequence; searching the current segment in accordance with a way search sequence for a way which has not yet been accessed during a current way search cycle; and storing the replacement data in a first way which has not yet been accessed during a current cycle of the way search sequence. A cache controller that performs such methods is also disclosed.
摘要翻译：公开了在多路关联高速缓存中存储替换数据的方法。一种方法包括将高速缓存的高速缓存集合逻辑划分成至少一个缓存方式的段; 根据段搜索序列搜索当前包括在片段搜索序列的当前周期中尚未被访问的方式的段的高速缓存集; 根据当前方式搜索周期中尚未被访问的方式的搜索顺序搜索当前段; 并且以当前循环的搜索顺序的第一种方式存储替换数据，该方式尚未被访问。还公开了执行这种方法的高速缓存控制器。

54. 发明授权

US06105108A Method and apparatus for releasing victim data buffers of computer systems by comparing a probe counter with a service counter 失效
标题翻译：通过将探测计数器与服务计数器进行比较来释放计算机系统的受害者数据缓冲器的方法和装置
公开(公告)号：US06105108A
公开(公告)日：2000-08-15
申请号：US957509
申请日：1997-10-24
申请人： Simon C. Steely, Jr. , Stephen Van Doren
发明人： Simon C. Steely, Jr. , Stephen Van Doren
IPC分类号： G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0811
摘要： A multiprocessor computer system releases a victim data buffer storing victim data, when system control logic determines that a count of the number of probe messages pending at a specified time equals the number of such probe messages that have had an address comparison performed after the specified time. The specified time occurs when a command to write the victim data element to main memory passes a serialization point of the computer system.The address comparison compares a target address of a probe message with addresses of data stored in the victim data buffer and the associated cache of a CPU of the computer system.
摘要翻译：多系统计算机系统释放存储受害者数据的受害者数据缓冲器，当系统控制逻辑确定在指定时间内等待的探测消息数量的计数等于在指定时间之后进行了地址比较的探测消息的数量。当将受害者数据元素写入主存储器的命令通过计算机系统的序列化点时，会发生指定的时间。地址比较将探测消息的目标地址与存储在受害者数据缓冲器中的数据的地址以及计算机系统的CPU的相关联的缓存进行比较。

55. 发明授权

US6101581A Separate victim buffer read and release control 失效
标题翻译：单独的受害者缓冲区读取和释放控制
公开(公告)号：US6101581A
公开(公告)日：2000-08-08
申请号：US957217
申请日：1997-10-24
申请人： Stephen Van Doren , Simon C. Steely, Jr. , Robert Eugene Stewart , James Bernard Keller
发明人： Stephen Van Doren , Simon C. Steely, Jr. , Robert Eugene Stewart , James Bernard Keller
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0804 , G06F12/0831
摘要： In accordance with the present invention, a method and apparatus is provided for maintaining the coherency of victim data from a time when the data is stored in a victim data buffer until a time when the data is written into a main memory. Alternatively, the coherency of the victim data is preserved until a determination is made that pending probe messages do not target the victim data. At that time the victim data buffer can be deallocated.With both arrangements, a central processing unit can release a victim data buffer at a point in time other than when the data that is stored therein is read from the buffer. Thus, the central processor unit can perform the release or deallocation of the buffer when it is most efficient and when no further access to the data is required.
摘要翻译：根据本发明，提供一种方法和装置，用于在将数据存储在受害者数据缓冲器中直到数据被写入主存储器的时间内时保持受害者数据的一致性。或者，保留受害者数据的一致性，直到确定未决探测消息不针对受害者数据为止。当时可以释放受害者的数据缓冲区。通过这两种布置，中央处理单元可以在从缓冲器读取存储在其中的数据以外的时间点释放受害者数据缓冲器。因此，当中央处理器单元最有效并且不需要对数据的进一步访问时，中央处理器单元可以执行缓冲器的释放或释放。

56. 发明授权

US5966737A Apparatus and method for serialized set prediction 失效
标题翻译：串联集预测的装置和方法
公开(公告)号：US5966737A
公开(公告)日：1999-10-12
申请号：US971630
申请日：1997-11-17
申请人： Simon C. Steely, Jr. , Joseph Dominic Macri
发明人： Simon C. Steely, Jr. , Joseph Dominic Macri
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： A prediction mechanism for improving direct-mapped cache performance is shown to include a direct-mapped cache, partitioned into a plurality of pseudo-banks. Prediction means are employed to provide a prediction index which is appended to the cache index to provide the entire address for addressing the direct mapped cache. One embodiment of the prediction means includes a prediction cache which is advantageously larger than the pseudo-banks of the direct-mapped cache and is used to store the prediction index for each cache location. A second embodiment includes a plurality of partial tag stores, each including a predetermined number of tag bits for the data in each bank. A comparison of the tags generates a match in one of the plurality of tag stores, and is used in turn to generate a prediction index. A third embodiment for use with a direct mapped cache divided into two partitions includes a distinguishing bit ram, which is used to provide the bit number of any bit which differs between the tags at the same location in the different banks. The bit number is used in conjunction with a complement signal to provide the prediction index for addressing the direct-mapped cache.
摘要翻译：示出了用于改善直接映射高速缓存性能的预测机制，其包括被划分成多个伪库的直接映射高速缓存。预测装置被用于提供附加到高速缓存索引的预测索引，以提供用于寻址直接映射高速缓存的整个地址。预测装置的一个实施例包括有利地大于直接映射高速缓存的伪库的预测高速缓存，并且用于存储每个高速缓存位置的预测索引。第二实施例包括多个部分标签存储，每个部分标签存储器包括用于每个存储体中的数据的预定数量的标签位。标签的比较在多个标签存储之一中产生匹配，并且依次用于生成预测索引。用于分割成两个分区的直接映射高速缓存的第三实施例包括区分位RAM，其用于提供不同存储体中相同位置处的标签之间不同的任何位的位数。位数与补码信号结合使用，以提供用于寻址直接映射高速缓存的预测索引。

57. 发明授权

US5829051A Apparatus and method for intelligent multiple-probe cache allocation 失效
标题翻译：智能多探头缓存分配的装置和方法
公开(公告)号：US5829051A
公开(公告)日：1998-10-27
申请号：US223069
申请日：1994-04-04
申请人： Simon C. Steely, Jr. , Richard B. Gillett, Jr. , Tryggve Fossum
发明人： Simon C. Steely, Jr. , Richard B. Gillett, Jr. , Tryggve Fossum
IPC分类号： G06F12/08 , G06F9/26
CPC分类号： G06F12/0864
摘要： An apparatus for allocating data to and retrieving data from a cache includes a memory subsystem coupled between a processor and a memory to provide quick access of memory data to the processor. The memory subsystem includes a cache memory. The address provided to the memory subsystem is divided into a cache index and a tag, and the cache index is hashed to provide a plurality of alternative addresses for accessing the cache. During a cache read, each of the alternative addresses are selected to search for the data responsive to an indicator of the validity of the data at the locations. The selection of the alternative address may be done through a mask having a number of bits corresponding to the number of alternative addresses. Each bit indicates whether the alternative address at that location should be used during the access of the cache in search of the data. Alternatively, a memory device which has more entries than the cache has blocks may be used to store the select value of the best alternative address to use to locate the data. Data is allocated to each alternative address based upon a modified least recently used technique wherein a quantum number and modula counter are used to time stamp the data.
摘要翻译：一种用于向高速缓存提供数据并从其中检索数据的装置包括耦合在处理器和存储器之间的存储器子系统，以便将存储器数据快速地存取到处理器。存储器子系统包括高速缓冲存储器。提供给存储器子系统的地址被划分为高速缓存索引和标签，并且高速缓存索引被散列以提供用于访问高速缓存的多个替代地址。在缓存读取期间，选择每个备选地址以响应于在该位置处的数据的有效性的指示符来搜索数据。替代地址的选择可以通过具有对应于替代地址的数量的位数的掩码来完成。每个位指示在缓存访问期间是否应该使用该位置处的替代地址来搜索数据。或者，具有比高速缓存具有更多条目的存储器装置可以用于存储用于定位数据的最佳替代地址的选择值。基于修改的最近最少使用的技术将数据分配给每个备选地址，其中使用量子数和模数计数器来对数据进行时间戳。

58. 发明授权

US5619662A Memory reference tagging 失效
标题翻译：内存引用标记
公开(公告)号：US5619662A
公开(公告)日：1997-04-08
申请号：US289613
申请日：1994-08-12
申请人： Simon C. Steely, Jr. , David J. Sager , David B. Fite, Jr.
发明人： Simon C. Steely, Jr. , David J. Sager , David B. Fite, Jr.
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3863 , G06F9/3012 , G06F9/30141 , G06F9/322 , G06F9/3802 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857
摘要： A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the instruction processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.
摘要翻译：流水线处理器包括指令盒，其包括寄存器映射器，映射一组指令的寄存器操作数字段和由该组指令馈送的指令调度器，以从指令处理器重新排序指令集的发布。映射的寄存器操作数字段在指令发布之前与重新排序的指令集的相应指令相关联。处理器还包括分支预测表，其将与分支指令相关联的过去历史的存储模式映射到分支指令的更可能的预测方向。处理器还包括与指令调度器相关联的存储器参考标记存储器，使得调度器可以在不知道由存储器参考指令寻址的实际存储器位置的情况下重新排序存储器参考指令。

59. 发明授权

US5564118A Past-history filtered branch prediction 失效
标题翻译：过去历史过滤分支预测
公开(公告)号：US5564118A
公开(公告)日：1996-10-08
申请号：US352291
申请日：1994-12-08
申请人： Simon C. Steely, Jr. , David J. Sager , William B. Noyce
发明人： Simon C. Steely, Jr. , David J. Sager , William B. Noyce
IPC分类号： G06F9/30 , G06F9/312 , G06F9/38 , G06F9/40
CPC分类号： G06F9/3806 , G06F9/30043 , G06F9/3012 , G06F9/30134 , G06F9/30141 , G06F9/3836 , G06F9/384 , G06F9/3848 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by said set of instructions, to reorder the issuance of said set of instructions from said instruction processor. The mapped register operand fields are associated with the corresponding instructions of said reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.
摘要翻译：流水线处理器包括指令盒，其包括寄存器映射器，映射一组指令的寄存器操作数字段和由所述指令组馈送的指令调度器，以从所述指令处理器重新排序所述指令集的发布。映射的寄存器操作数字段在指令发布之前与所述重新排序的指令集的相应指令相关联。处理器还包括分支预测表，其将与分支指令相关联的过去历史的存储模式映射到分支指令的更可能的预测方向。处理器还包括与指令调度器相关联的存储器参考标记存储器，使得调度器可以在不知道由存储器参考指令寻址的实际存储器位置的情况下重新排序存储器参考指令。

60. 发明授权

US5551048A Ring based distributed communication bus for a multiprocessor network 失效
标题翻译：用于多处理器网络的基于环的分布式通信总线
公开(公告)号：US5551048A
公开(公告)日：1996-08-27
申请号：US253474
申请日：1994-06-03
申请人： Simon C. Steely, Jr.
发明人： Simon C. Steely, Jr.
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0813 , G06F12/0815 , Y10S707/99952
摘要： A method for providing communication between a plurality of nodes coupled in a ring arrangement, wherein a plurality of the nodes comprise processors each having a cache memory for storing a subset of shared data. Each of the nodes on the ring deposits data into a data slot during a given time period. The data deposited by each node may comprise an address field and a node field. To ensure data coherency between the caches, each processor on the ring includes a queue for saving a plurality of received data representative of the latest bus data transmitted on the bus. As each processor receives new data, the new data is compared against the plurality of saved data in the queue to determine if the address field of the new data matches the address field of any of the saved data of the queue. In the event that the new data matches one of the plurality of saved data, it is determined whether the new data represents updated data from the memory device. If the new data represents updated data it is shifted into the queue. If it does not represent updated data, it is discarded.
摘要翻译：一种用于在以环形布置耦合的多个节点之间提供通信的方法，其中多个节点包括具有用于存储共享数据子集的高速缓存存储器的处理器。环中的每个节点在给定时间段内将数据存入数据时隙。由每个节点存储的数据可以包括地址字段和节点字段。为了确保高速缓存之间的数据一致性，环上的每个处理器包括用于保存表示在总线上发送的最新总线数据的多个接收数据的队列。当每个处理器接收新数据时，将新数据与队列中的多个保存的数据进行比较，以确定新数据的地址字段是否与队列中保存的任何数据的地址字段匹配。在新数据与多个保存数据中的一个匹配的情况下，确定新数据是否表示来自存储装置的更新数据。如果新的数据表示更新的数据，则它被转移到队列中。如果不表示已更新的数据，则会被丢弃。

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