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1. 发明授权

US5953747A Apparatus and method for serialized set prediction 失效
公开(公告)号：US5953747A
公开(公告)日：1999-09-14
申请号：US668316
申请日：1996-06-26
申请人： Simon C. Steely, Jr. , Joseph Dominic Macri
发明人： Simon C. Steely, Jr. , Joseph Dominic Macri
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： A prediction mechanism for improving direct-mapped cache performance is shown to include a direct-mapped cache, partitioned into a plurality of pseudo-banks. Prediction means are employed to provide a prediction index which is appended to the cache index to provide the entire address for addressing the direct mapped cache. One embodiment of the prediction means includes a prediction cache which is advantageously larger than the pseudo-banks of the direct-mapped cache and is used to store the prediction index for each cache location. A second embodiment includes a plurality of partial tag stores, each including a predetermined number of tag bits for the data in each bank. A comparison of the tags generates a match in one of the plurality of tag stores, and is used in turn to generate a prediction index. A third embodiment for use with a direct mapped cache divided into two partitions includes a distinguishing bit ram, which is used to provide the bit number of any bit which differs between the tags at the same location in the different banks. The bit number is used in conjunction with a complement signal to provide the prediction index for addressing the direct-mapped cache.

2. 发明授权

US6154828A Method and apparatus for employing a cycle bit parallel executing instructions 失效
标题翻译：用于使用循环位指示并行执行指令的执行完成的方法和装置
公开(公告)号：US6154828A
公开(公告)日：2000-11-28
申请号：US072632
申请日：1993-06-03
申请人： Joseph Dominic Macri , Francis X. McKeen , Joel S. Emer , William Robert Grundmann , Robert P. Nix , David Arthur James Webb, Jr.
发明人： Joseph Dominic Macri , Francis X. McKeen , Joel S. Emer , William Robert Grundmann , Robert P. Nix , David Arthur James Webb, Jr.
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/3836 , G06F9/3838
摘要： A method and apparatus including means for storing an executable file which includes a group of bits which define functional operations and cycle bits associated with each functional operation and means for completing a variable number of the functional operations in parallel during a single execution cycle in accordance with a state of the associated cycle bit. The method and apparatus eliminates the need for complex data dependency checking hardware and allows a minimum amount of control logic to complete execution of executable files. The method and apparatus further minimizes the necessity of adding null operations (NOPs) to executable files which reduces the amount of storage space necessary to store the executable files and allows executable files to be used on multiple hardware implementations and for register values to be used for multiple purposes during single execution cycles.
摘要翻译：一种方法和装置，包括用于存储可执行文件的装置，该可执行文件包括定义与每个功能操作相关联的功能操作和周期位的一组比特，以及用于在单个执行周期期间根据单个执行周期并行地完成可变数量的功能操作的装置相关联的周期位的状态。该方法和装置消除了对复杂数据依赖性检查硬件的需要，并允许最小量的控制逻辑来完成可执行文件的执行。该方法和装置进一步最小化了对可执行文件添加空操作（NOP）的必要性，这减少了存储可执行文件所需的存储空间量，并允许在多个硬件实现上使用可执行文件，并且使用用于在单个执行周期中有多个目的。

3. 发明授权

US06678204B2 Semiconductor memory device with high-speed operation and methods of using and designing thereof 有权
标题翻译：具有高速操作的半导体存储器件及其使用和设计方法
公开(公告)号：US06678204B2
公开(公告)日：2004-01-13
申请号：US10026755
申请日：2001-12-27
申请人： Osamu Nagashima , Joseph Dominic Macri
发明人： Osamu Nagashima , Joseph Dominic Macri
IPC分类号： G11C812
CPC分类号： G11C11/4076 , G11C7/1042 , G11C7/1072 , G11C7/22 , G11C11/4097
摘要： Two types of command interval specifications are defined as first and second command interval specifications. The first command interval specifications is defined as the relationship between a preceding command and a following command that are issued for the same bank, while the second command interval specifications is defined as the relationship between a preceding command and a following command that are issued for different banks, respectively. As for the second command interval specification, since target banks are different between a preceding command and a following command, the following command is executed during the column circuits precharge after the preceding command. Therefore, in the case of the second command interval specification, a command interval is substantially shortened. In addition, pairs of banks are defined as bank pairs, and are applied the first and second command interval specifications, so that the DRAM device is small-sized.
摘要翻译：两种类型的命令间隔规范被定义为第一和第二命令间隔规范。第一个命令间隔规范被定义为为同一个组发出的上一个命令和后续命令之间的关系，而第二个命令间隔规范被定义为前面的命令和下一个命令之间的关系，银行。对于第二命令间隔指定，由于在前一命令和后续命令之间的目标组不同，所以在前一命令之后的列电路预充电期间执行以下命令。因此，在第二命令间隔指定的情况下，命令间隔大大缩短。另外，银行对被定义为银行对，并且应用第一和第二指令间隔规范，使得DRAM设备是小型的。

4. 发明授权

US5966737A Apparatus and method for serialized set prediction 失效
标题翻译：串联集预测的装置和方法
公开(公告)号：US5966737A
公开(公告)日：1999-10-12
申请号：US971630
申请日：1997-11-17
申请人： Simon C. Steely, Jr. , Joseph Dominic Macri
发明人： Simon C. Steely, Jr. , Joseph Dominic Macri
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： A prediction mechanism for improving direct-mapped cache performance is shown to include a direct-mapped cache, partitioned into a plurality of pseudo-banks. Prediction means are employed to provide a prediction index which is appended to the cache index to provide the entire address for addressing the direct mapped cache. One embodiment of the prediction means includes a prediction cache which is advantageously larger than the pseudo-banks of the direct-mapped cache and is used to store the prediction index for each cache location. A second embodiment includes a plurality of partial tag stores, each including a predetermined number of tag bits for the data in each bank. A comparison of the tags generates a match in one of the plurality of tag stores, and is used in turn to generate a prediction index. A third embodiment for use with a direct mapped cache divided into two partitions includes a distinguishing bit ram, which is used to provide the bit number of any bit which differs between the tags at the same location in the different banks. The bit number is used in conjunction with a complement signal to provide the prediction index for addressing the direct-mapped cache.
摘要翻译：示出了用于改善直接映射高速缓存性能的预测机制，其包括被划分成多个伪库的直接映射高速缓存。预测装置被用于提供附加到高速缓存索引的预测索引，以提供用于寻址直接映射高速缓存的整个地址。预测装置的一个实施例包括有利地大于直接映射高速缓存的伪库的预测高速缓存，并且用于存储每个高速缓存位置的预测索引。第二实施例包括多个部分标签存储，每个部分标签存储器包括用于每个存储体中的数据的预定数量的标签位。标签的比较在多个标签存储之一中产生匹配，并且依次用于生成预测索引。用于分割成两个分区的直接映射高速缓存的第三实施例包括区分位RAM，其用于提供不同存储体中相同位置处的标签之间不同的任何位的位数。位数与补码信号结合使用，以提供用于寻址直接映射高速缓存的预测索引。

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