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1. 发明授权

US09588889B2 Domain state 有权
标题翻译：域状态
公开(公告)号：US09588889B2
公开(公告)日：2017-03-07
申请号：US13995991
申请日：2011-12-29
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0802 , G06F12/0811 , G06F12/0817 , G06F13/00
摘要： Method and apparatus to efficiently maintain cache coherency by reading/writing a domain state field associated with a tag entry within a cache tag directory. A value may be assigned to a domain state field of a tag entry in a cache tag directory. The cache tag directory may belong to a hierarchy of cache tag directories. Each tag entry may be associated with a cache line from a cache belonging to a first domain. The first domain may contain multiple caches. The value of the domain state field may indicate whether its associated cache line can be read or changed.
摘要翻译：通过读/写与缓存标签目录中的标签条目相关联的域状态字段来有效地维持高速缓存一致性的方法和装置。可以将值分配给缓存标签目录中的标签条目的域状态字段。缓存标签目录可能属于高速缓存标签目录的层次结构。每个标签条目可以与来自属于第一域的高速缓存行相关联。第一个域可能包含多个缓存。域状态字段的值可以指示其相关联的高速缓存行是否可以被读取或改变。

2. 发明授权

US09201792B2 Short circuit of probes in a chain 有权
标题翻译：探针在链中短路
公开(公告)号：US09201792B2
公开(公告)日：2015-12-01
申请号：US13996012
申请日：2011-12-29
申请人： Simon C. Steely, Jr. , Samantika Subramaniam , William C. Hasenplaugh , Joel S. Emer
发明人： Simon C. Steely, Jr. , Samantika Subramaniam , William C. Hasenplaugh , Joel S. Emer
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/082
摘要： A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining that a local last accessor of the memory address may have a copy of the requested data up to date with the memory. The local last accessor may be within a local domain that the requester belongs to. The method may further comprise sending a cache probe to the local last accessor and retrieving a latest value of the requested data from the local last accessor to the requester.
摘要翻译：多核处理装置可以提供高速缓存探针和数据检索方法。该方法可以包括将请求者的存储器请求发送到记录保存结构。存储器请求可以具有存储请求的数据的存储器的存储器地址。该方法还可以包括确定存储器地址的本地最后访问器可以具有与存储器一起的所请求数据的副本。本地最后一个访问者可能在请求者所属的本地域内。该方法还可以包括向本地最后一个访问器发送高速缓存探测器，并且从本地最后一个访问器检索所请求的数据的最新值到请求者。

3. 发明授权

US08438335B2 Probe speculative address file 失效
标题翻译：探测推测地址文件
公开(公告)号：US08438335B2
公开(公告)日：2013-05-07
申请号：US12892476
申请日：2010-09-28
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F2212/507
摘要： An apparatus to resolve cache coherency is presented. In one embodiment, the apparatus includes a microprocessor comprising one or more processing cores. The apparatus also includes a probe speculative address file unit, coupled to a cache memory, comprising a plurality of entries. Each entry includes a timer and a tag associated with a memory line. The apparatus further includes control logic to determine whether to service an incoming probe based at least in part on a timer value.
摘要翻译：提出了一种解决高速缓存一致性的设备。在一个实施例中，该装置包括具有一个或多个处理核心的微处理器。该装置还包括耦合到高速缓冲存储器的探测推测地址文件单元，包括多个条目。每个条目包括定时器和与存储器线相关联的标签。该装置还包括至少部分地基于定时器值来确定是否对入站探测器进行服务的控制逻辑。

4. 发明授权

US08407421B2 Cache spill management techniques using cache spill prediction 失效
标题翻译：缓存溢出管理技术使用缓存溢出预测
公开(公告)号：US08407421B2
公开(公告)日：2013-03-26
申请号：US12639214
申请日：2009-12-16
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Aamer Jaleel , George Z. Chrysos
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Aamer Jaleel , George Z. Chrysos
IPC分类号： G06F12/00
CPC分类号： G06F12/0806 , G06F12/12
摘要： An apparatus and method is described herein for intelligently spilling cache lines. Usefulness of cache lines previously spilled from a source cache is learned, such that later evictions of useful cache lines from a source cache are intelligently selected for spill. Furthermore, another learning mechanism—cache spill prediction—may be implemented separately or in conjunction with usefulness prediction. The cache spill prediction is capable of learning the effectiveness of remote caches at holding spilled cache lines for the source cache. As a result, cache lines are capable of being intelligently selected for spill and intelligently distributed among remote caches based on the effectiveness of each remote cache in holding spilled cache lines for the source cache.
摘要翻译：这里描述了用于智能地溢出高速缓存行的装置和方法。了解先前从源缓存溢出的高速缓存行的有用性，从而智能地选择来自源缓存的随后驱逐的溢出。此外，另一种学习机制 - 缓存溢出预测 - 可以单独实施或结合有用性预测来实现。高速缓存溢出预测能够学习在为源缓存保留溢出的高速缓存行时远程高速缓存的有效性。因此，基于每个远程高速缓存在保存用于源高速缓存的溢出高速缓存行的有效性的情况下，高速缓存行能够被智能地选择为溢出并且智能地分布在远程高速缓存中。

5. 发明授权

US07360069B2 Systems and methods for executing across at least one memory barrier employing speculative fills 有权
标题翻译：通过使用投机填充的至少一个记忆障碍执行的系统和方法
公开(公告)号：US07360069B2
公开(公告)日：2008-04-15
申请号：US10756639
申请日：2004-01-13
申请人： Simon C. Steely, Jr. , Gregory Edward Tierney
发明人： Simon C. Steely, Jr. , Gregory Edward Tierney
IPC分类号： G06F9/00
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3863 , G06F12/0815 , G06F12/0859
摘要： Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a processor having a processor pipeline that executes program instructions across at least one memory barrier with data from speculative data fills that are provided in response to source requests, and a log that retains executed load instruction entries associated with executed program instruction. The executed load instruction entries may be retired if a cache line associated with data of the speculative data fill has not been invalidated in an epoch that is different from the epoch in which the executed load instruction is executed.
摘要翻译：提供多处理器系统和方法。一个实施例涉及一种多处理器系统，其可以包括具有处理器流水线的处理器，处理器流水线通过至少一个存储器障碍执行程序指令，其中数据来自响应于源请求而提供的推测数据填充，以及保留执行负载的日志与执行的程序指令相关联的指令条目。如果在与执行的执行加载指令的历元不同的时期中，与推测数据填充的数据相关联的高速缓存行没有被无效，那么执行的加载指令条目可能会被停止。

6. 发明授权

US06286090B1 Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches 失效
标题翻译：选择性地强制页表提取之间的干扰顺序和相应数据提取的机制
公开(公告)号：US06286090B1
公开(公告)日：2001-09-04
申请号：US09084621
申请日：1998-05-26
申请人： Simon C. Steely, Jr. , Madhumitra Sharma , Stephen R. Van Doren , Kourosh Gharachorloo
发明人： Simon C. Steely, Jr. , Madhumitra Sharma , Stephen R. Van Doren , Kourosh Gharachorloo
IPC分类号： G06F1200
CPC分类号： G06F12/1054 , G06F12/0813
摘要： A technique selectively imposes inter-reference ordering between memory reference operations issued by a processor of a multiprocessor system to addresses within a page pertaining to a page table entry (PTE) that is affected by a translation buffer (TB) miss flow routine. The TB miss flow is used to retrieve information contained in the PTE for mapping a virtual address to a physical address and, subsequently, to allow retrieval of data at the mapped physical address. The PTE that is retrieved in response to a memory reference (read) operation is not loaded into the TB until a commit-signal associated with that read operation is returned to the processor. Once the PTE and associated commit-signal are returned, the processor loads the PTE into the TB so that it can be used for a subsequent read operation directed to the data at the physical address.
摘要翻译：一种技术选择性地将由多处理器系统的处理器发出的存储器参考操作之间的参考间排序施加于与由翻译缓冲器（TB）错过流程程影响的页表项（PTE）相关的页面内的地址。 TB错误流被用于检索包含在PTE中的信息，用于将虚拟地址映射到物理地址，并且随后允许在映射的物理地址处检索数据。响应于存储器引用（读取）操作检索的PTE不会被加载到TB中，直到与该读取操作相关联的提交信号返回到处理器。一旦返回了PTE和相关联的提交信号，处理器将PTE加载到TB中，以便它可以用于针对物理地址的数据的后续读取操作。

7. 发明授权

US6049889A High performance recoverable communication method and apparatus for write-only networks 失效
标题翻译：用于只写网络的高性能可恢复通信方法和装置
公开(公告)号：US6049889A
公开(公告)日：2000-04-11
申请号：US6115
申请日：1998-01-13
申请人： Simon C. Steely, Jr. , Glenn P. Garvey , Richard B. Gillett, Jr.
发明人： Simon C. Steely, Jr. , Glenn P. Garvey , Richard B. Gillett, Jr.
IPC分类号： H04L29/06 , H04L29/14 , G06F3/00
CPC分类号： H04L29/06 , H04L69/40
摘要： A multi-node computer network includes a plurality of nodes coupled together via a data link. Each of the nodes includes a local memory, which further comprises a shared memory. Certain items of data that are to be shared by the nodes are stored in the shared portion of memory. Associated with each of the shared data items is a data structure. When a node sharing data with other nodes in the system seeks to modify the data, it transmits the modifications over the data link to the other nodes in the network. Each update is received in order by each node in the cluster. As part of the last transmission by the modifying node, an acknowledgement request is sent to the receiving nodes in the cluster. Each node that receives the acknowledgment request returns an acknowledgement to the sending node. The returned acknowledgement is written to the data structure associated with the shared data item. If there is an error during the transmission of the message, the receiving node does not transmit an acknowledgement, and the sending node is thereby notified that an error has occurred.
摘要翻译：多节点计算机网络包括通过数据链路耦合在一起的多个节点。每个节点包括本地存储器，其还包括共享存储器。要由节点共享的某些数据项存储在存储器的共享部分中。与每个共享数据项相关联的是数据结构。当与系统中的其他节点共享数据的节点寻求修改数据时，它将数据链路上的修改发送到网络中的其他节点。群集中的每个节点按顺序接收每个更新。作为修改节点的最后一次传输的一部分，向群集中的接收节点发送确认请求。接收确认请求的每个节点向发送节点返回确认。返回的确认被写入与共享数据项相关联的数据结构。如果在消息的发送期间存在错误，则接收节点不发送确认，并且由此通知发送节点发生了错误。

8. 发明授权

US5509135A Multi-index multi-way set-associative cache 失效
标题翻译：多索引多路组合关联缓存
公开(公告)号：US5509135A
公开(公告)日：1996-04-16
申请号：US951623
申请日：1992-09-25
申请人： Simon C. Steely, Jr.
发明人： Simon C. Steely, Jr.
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0864
摘要： A plurality of indexes are provided for a multi-way set-associate cache of a computer system. The cache is organized as a plurality of blocks for storing data which are a copies of main memory data. Each block has an associated tag for uniquely identifying the block. The blocks and the tags are addressed by indexes. The indexes are generated by a Boolean hashing function which converts a memory address to cache indexes by combining the bits of the memory address using an exclusive OR function. Different combination of bits are used to generate a plurality of different indexes to address the tags and the associated blocks to transfer data between the cache and the central processing unit of the computer system.
摘要翻译：为计算机系统的多路集合相关缓存提供多个索引。高速缓存被组织为用于存储作为主存储器数据的副本的数据的多个块。每个块都具有用于唯一标识块的关联标签。块和标签由索引寻址。索引由布尔散列函数生成，该函数通过使用异或函数组合存储器地址的位来将存储器地址转换为缓存索引。使用不同的比特组合来生成多个不同的索引以寻址标签和相关联的块以在计算机系统的高速缓存和中央处理单元之间传送数据。

9. 发明授权

US5235697A Set prediction cache memory system using bits of the main memory address 失效
标题翻译：使用主存储器地址的位设置预测高速缓存存储器系统
公开(公告)号：US5235697A
公开(公告)日：1993-08-10
申请号：US956827
申请日：1992-10-05
申请人： Simon C. Steely, Jr. , John H. Zurawski
发明人： Simon C. Steely, Jr. , John H. Zurawski
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： The set-prediction cache memory system comprises an extension of a set-associative cache memory system which operates in parallel to the set-associative structure to increase the overall speed of the cache memory while maintaining its performance. The set prediction cache memory system includes a plurality of data RAMs and a plurality of tag RAMs to store data and data tags, respectively. Also included in the system are tag store comparators to compare the tag data contained in a specific tag RAM location with a second index comprising a predetermined second portion of a main memory address. The elements of the set prediction cache memory system which operate in parallel to the set-associative cache memory include: a set-prediction RAM which receives at least one third index comprising a predetermined third portion of the main memory address, and stores such third index to essentially predict the data cache RAM holding the data indexed by the third index; a data-select multiplexer which receives the prediction index and selects a data output from the data cache RAM indexed by the prediction index; and a mispredict logic device to determine if the set prediction RAM predicted the correct data cache RAM and if not, issue a mispredict signal which may comprise a write data signal, the write data signal containing information intended to correct the prediction index contained in the set prediction RAM.
摘要翻译：设置预测高速缓冲存储器系统包括与集合关联结构并行操作的集合关联高速缓冲存储器系统的扩展，以在保持其性能的同时增加高速缓冲存储器的总体速度。集合预测高速缓冲存储器系统包括分别存储数据和数据标签的多个数据RAM和多个标签RAM。还包括在系统中的标签存储比较器，用于将包含在特定标签RAM位置中的标签数据与包含主存储器地址的预定第二部分的第二索引进行比较。与设置关联高速缓存存储器并行操作的集合预测高速缓冲存储器系统的元件包括：设置预测RAM，其接收包含主存储器地址的预定第三部分的至少一个第三索引，并存储这样的第三索引以基本预测由第三指标索引的数据的数据缓存RAM; 数据选择多路复用器，其接收预测索引并选择从由预测索引索引的数据高速缓存RAM输出的数据; 以及用于确定所设置的预测RAM是否预测正确的数据高速缓存RAM的错误预测逻辑设备，如果不是，则发出可能包括写入数据信号的错误预测信号，所述写入数据信号包含旨在校正包含在该组中的预测索引的信息预测RAM。

10. 发明授权

US09262327B2 Signature based hit-predicting cache 有权
标题翻译：基于签名的命中预测缓存
公开(公告)号：US09262327B2
公开(公告)日：2016-02-16
申请号：US13538390
申请日：2012-06-29
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Aamer Jaleel , Joel S. Emer , Carole-Jean Wu
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Aamer Jaleel , Joel S. Emer , Carole-Jean Wu
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： An apparatus may comprise a cache file having a plurality of cache lines and a hit predictor. The hit predictor may contain a table of counter values indexed with signatures that are associated with the plurality of cache lines. The apparatus may fill cache lines into the cache file with either low or high priority. Low priority lines may be chosen to be replaced by a replacement algorithm before high priority lines. In this way, the cache naturally may contain more high priority lines than low priority ones. This priority filling process may improve the performance of most replacement schemes including the best known schemes which are already doing better than LRU.
摘要翻译：装置可以包括具有多个高速缓存行和命中预测器的高速缓存文件。命中预测器可以包含用与多个高速缓存行相关联的签名索引的计数器值的表。该装置可以以低优先级或高优先级将高速缓存行填充到高速缓存文件中。低优先级行可以被选择为在高优先级行之前由替换算法代替。以这种方式，高速缓存当然可以包含比优先级更高的优先级更高的行。该优先填充过程可以改善大多数替换方案的性能，包括已经比LRU更好的已知方案。

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