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51. 发明申请

US20130058164A1 MEMORY APPARATUS, SYSTEMS, AND METHODS 有权
公开(公告)号：US20130058164A1
公开(公告)日：2013-03-07
申请号：US13563314
申请日：2012-07-31
申请人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
发明人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C2211/5641
摘要： Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided.

52. 发明授权

US10102903B1 Write process for a non volatile memory device 有权
公开(公告)号：US10102903B1
公开(公告)日：2018-10-16
申请号：US15476654
申请日：2017-03-31
申请人： Tommaso Vali , Violante Moschiano , Andrea D'Alessandro , Pranav Kalavade
发明人： Tommaso Vali , Violante Moschiano , Andrea D'Alessandro , Pranav Kalavade
IPC分类号： G11C11/34 , G11C11/56 , G11C16/10 , G11C16/34
摘要： An apparatus is described. The apparatus includes a non volatile memory device that includes a controller to implement a coarse write process for the non volatile memory device. The non volatile memory device includes storage cells to store more than two logic states, wherein, the coarse write process is to perform a verify operation early in the coarse write process to identify less responsive storage cells and provide additional charge to the less responsive storage cells as compared to non less responsive storage cells that are to be programmed to a same logical state as the less responsive storage cells without performing a following verify operation after each pulse of charge applied during the coarse write process.

53. 发明授权

US08737139B2 Determining soft data for combinations of memory cells 有权
标题翻译：确定存储单元组合的软数据
公开(公告)号：US08737139B2
公开(公告)日：2014-05-27
申请号：US13444443
申请日：2012-04-11
申请人： Violante Moschiano , Tommaso Vali , Mark A. Hawes
发明人： Violante Moschiano , Tommaso Vali , Mark A. Hawes
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/26
摘要： The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and a second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells.
摘要翻译：本公开包括用于确定存储器单元的组合的软数据的装置和方法。多个实施例包括存储单元的阵列，其包括第一和第二存储单元，每个第一和第二存储器单元可编程为多个程序状态之一，其中第一和第二存储器单元的编程状态的组合对应于多个数据状态，以及耦合到阵列并被配置为确定与第一和第二存储器单元的程序状态相关联的软数据的缓冲器和/或控制器以及与对应于程序状态的组合的数据状态相关联的软数据至少部分地基于与第一和第二存储器单元的程序状态相关联的软数据。

54. 发明申请

US20130051141A1 THRESHOLD VOLTAGE COMPENSATION IN A MULTILEVEL MEMORY 有权
标题翻译：多电平存储器中的阈值电压补偿
公开(公告)号：US20130051141A1
公开(公告)日：2013-02-28
申请号：US13219439
申请日：2011-08-26
申请人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
发明人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
IPC分类号： G11C16/04
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C2211/5641
摘要： Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.
摘要翻译：电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。对于相邻编程的侵略存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。

55. 发明申请

US20120176843A1 MEMORIES AND METHODS OF PROGRAMMING MEMORIES 有权
标题翻译：记忆和编程记忆的方法
公开(公告)号：US20120176843A1
公开(公告)日：2012-07-12
申请号：US13051599
申请日：2011-03-18
申请人： Pranav Kalavade , Akira Goda , Tommaso Vali , Violante Moschiano
发明人： Pranav Kalavade , Akira Goda , Tommaso Vali , Violante Moschiano
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454 , G11C16/3459
摘要： Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper limit is determined after a single programming pulse for lower page programming, and upper page programming start voltages are adjusted based on the determined upper limit of the threshold voltage distribution.
摘要翻译：公开了用于调整存储器上部页面编程的装置和方法。在至少一个实施例中，在用于较低页编程的单个编程脉冲之后确定阈值电压分布上限，并且基于所确定的阈值电压分布的上限来调整上页编程开始电压。

56. 发明授权

US08902653B2 Memory devices and configuration methods for a memory device 有权
标题翻译：存储器件的存储器件和配置方法
公开(公告)号：US08902653B2
公开(公告)日：2014-12-02
申请号：US13208802
申请日：2011-08-12
申请人： William H. Radke , Tommaso Vali , Michele Incarnati
发明人： William H. Radke , Tommaso Vali , Michele Incarnati
IPC分类号： G11C11/34 , G11C16/06 , G06F11/10 , G11C16/10 , G11C16/04 , G11C11/56
CPC分类号： G06F11/1048 , G06F3/0604 , G06F3/0608 , G06F3/0629 , G06F3/0631 , G06F3/064 , G06F3/0679 , G06F11/1068 , G06F11/1072 , G06F12/0207 , G06F12/0646 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C29/52
摘要： Memory devices and methods of operating memory devices are disclosed. In one such method, different blocks of memory cells have different configurations of user data space and overhead data space. In at least one method, overhead data is distributed within more than one block of memory cells. In another method, blocks are reconfigurable responsive to particular operating modes and/or desired levels of reliability of user data stored in a memory device.
摘要翻译：公开了存储器件和操作存储器件的方法。在一种这样的方法中，不同的存储器单元块具有用户数据空间和开销数据空间的不同配置。在至少一种方法中，开销数据分布在多于一个存储单元块内。在另一种方法中，可以响应于存储在存储器设备中的特定操作模式和/或用户数据的可靠性的期望级别重新配置块。

57. 发明申请

US20130039129A1 MEMORY DEVICES AND CONFIGURATION METHODS FOR A MEMORY DEVICE 有权
标题翻译：用于存储器件的存储器件和配置方法
公开(公告)号：US20130039129A1
公开(公告)日：2013-02-14
申请号：US13208802
申请日：2011-08-12
申请人： William H. RADKE , Tommaso Vali , Michele Incarnati
发明人： William H. RADKE , Tommaso Vali , Michele Incarnati
IPC分类号： G11C29/42 , G11C16/04
CPC分类号： G06F11/1048 , G06F3/0604 , G06F3/0608 , G06F3/0629 , G06F3/0631 , G06F3/064 , G06F3/0679 , G06F11/1068 , G06F11/1072 , G06F12/0207 , G06F12/0646 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C29/52
摘要： Memory devices and methods of operating memory devices are disclosed. In one such method, different blocks of memory cells have different configurations of user data space and overhead data space. In at least one method, overhead data is distributed within more than one block of memory cells. In another method, blocks are reconfigurable responsive to particular operating modes and/or desired levels of reliability of user data stored in a memory device.
摘要翻译：公开了存储器件和操作存储器件的方法。在一种这样的方法中，不同的存储器单元块具有用户数据空间和开销数据空间的不同配置。在至少一种方法中，开销数据分布在多于一个存储单元块内。在另一种方法中，可以响应于存储在存储器设备中的特定操作模式和/或用户数据的可靠性的期望级别重新配置块。

58. 发明授权

US06584035B2 Supply noise reduction in memory device column selection 有权
公开(公告)号：US06584035B2
公开(公告)日：2003-06-24
申请号：US10032375
申请日：2001-12-21
申请人： Ercole Di lorio , Giulio G. Marotta , Giovanni Santin , Tommaso Vali
发明人： Ercole Di lorio , Giulio G. Marotta , Giovanni Santin , Tommaso Vali
IPC分类号： G11C800
CPC分类号： G11C16/08 , G11C7/1048 , G11C8/10 , G11C2207/002
摘要： Column select circuits having improved immunity to supply potential noise during sensing of the programmed state of a target memory cell are suited for use in low-voltage memory devices. Such column select circuits contain driver circuits having a filtered path and an unfiltered path for applying a supply potential to a gate of a pass transistor. The unfiltered path is utilized during a first sensing phase, such as during decoding or precharging of the bit lines, when transition speed of the pass transistors is desired. The filtered path is utilized at least during a second sensing phase while the sensing device is detecting the programmed state of the target memory cell. By reducing the noise of the supply potential using the filtered path, margins are improved on the sensing device and the sensing device is thus capable of operating at lower supply potentials.

59. 发明申请

US20100122016A1 DYNAMIC SLC/MLC BLOCKS ALLOCATIONS FOR NON-VOLATILE MEMORY 有权
标题翻译：动态SLC / MLC块分配非易失性存储器
公开(公告)号：US20100122016A1
公开(公告)日：2010-05-13
申请号：US12269766
申请日：2008-11-12
申请人： Giulio Marotta , Luca De Santis , Tommaso Vali
发明人： Giulio Marotta , Luca De Santis , Tommaso Vali
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G11C16/16 , G06F12/0246 , G06F2212/7202 , G11C2211/5641
摘要： Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode.
摘要翻译：公开了装置和方法，例如基于特性在单级单元（SLC）和多级单元（MLC）之间的NAND闪速存储器中提供动态块分配的装置和方法。在一个实施例中，存储器控制器基于可用于使用的存储器的量，在SLC模式和MLC模式之间的编程和/或重新编程块之间动态切换。当内存使用量低时，使用SLC模式。当内存使用率高时，使用MLC模式。动态块分配允许内存控制器获得SLC模式的性能和可靠性优势，同时保持MLC模式的节省空间的优势。

60. 发明授权

US07206240B2 Fast sensing scheme for floating-gate memory cells 有权
标题翻译：浮栅存储器单元的快速感测方案
公开(公告)号：US07206240B2
公开(公告)日：2007-04-17
申请号：US10787911
申请日：2004-02-25
申请人： Girolamo Gallo , Tommaso Vali , Giulio Giuseppe Marotta
发明人： Girolamo Gallo , Tommaso Vali , Giulio Giuseppe Marotta
IPC分类号： G11C7/02
CPC分类号： G11C7/04 , G11C7/14 , G11C16/24 , G11C16/26
摘要： Sensing circuits are adapted for faster sensing of a programmed state of a floating-gate memory cell. The sensing circuits include a first precharging path for applying a first precharge potential to the input node of a sensing device for precharging bit lines prior to sensing the programmed state of the floating-gate memory cell. The sensing circuits further include a second precharging path for applying a second precharge potential to a target global bit line for precharging bit lines prior to sensing the programmed state of the floating-gate memory cell. The second precharging path is activated during only a portion of the precharging phase of a sensing operation to bring the bit lines rapidly up toward an asymptotic potential level. The second precharging path is thus deactivated prior to deactivating the first precharging path.
摘要翻译：感测电路适于更快地感测浮栅存储器单元的编程状态。感测电路包括用于将第一预充电电位施加到感测装置的输入节点的第一预充电路径，用于在感测浮栅存储器单元的编程状态之前对位线进行预充电。感测电路还包括第二预充电路径，用于在感测浮栅存储器单元的编程状态之前，将第二预充电电位施加到目标全局位线用于预充电位线。第二预充电路径仅在感测操作的预充电阶段的一部分期间被激活，以使位线快速向上渐近的电位电平。因此在停用第一预充电路径之前停用第二预充电路径。

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