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51. 发明授权

US07831774B2 Pipelining D states for MRU steerage during MRU-LRU member allocation 有权
标题翻译：在MRU-LRU成员分配过程中管理D状态用于MRU操纵
公开(公告)号：US07831774B2
公开(公告)日：2010-11-09
申请号：US12118238
申请日：2008-05-09
申请人： Robert H. Bell, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
发明人： Robert H. Bell, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/0888 , G06F12/123 , G06F12/126 , G06F2212/1032
摘要： A method and apparatus for preventing selection of Deleted (D) members as an LRU victim during LRU victim selection. During each cache access targeting the particular congruence class, the deleted cache line is identified from information in the cache directory. A location of a deleted cache line is pipelined through the cache architecture during LRU victim selection. The information is latched and then passed to MRU vector generation logic. An MRU vector is generated and passed to the MRU update logic, which is selects/tags the deleted member as a MRU member. The make MRU operation affects only the lower level LRU state bits arranged in a tree-based structure state bits so that the make MRU operation only negates selection of the specific member in the D state, without affecting LRU victim selection of the other members.
摘要翻译：用于在LRU受害者选择期间防止选择被删除（D）成员作为LRU受害者的方法和装置。在针对特定同余类的每个缓存访问期间，从高速缓存目录中的信息识别已删除的高速缓存行。删除的高速缓存行的位置在LRU受害者选择期间通过高速缓存架构流水线化。信息被锁存，然后传递给MRU向量生成逻辑。生成MRU向量并将其传递给MRU更新逻辑，MRU更新逻辑是将删除的成员作为MRU成员进行选择/标记。使MRU操作仅影响以基于树的结构状态位布置的较低级LRU状态位，使得MRU操作仅在D状态下否定特定成员的选择，而不影响其他成员的LRU受害者选择。

52. 发明申请

US20100153650A1 Victim Cache Line Selection 有权
标题翻译：受害者缓存行选择
公开(公告)号：US20100153650A1
公开(公告)日：2010-06-17
申请号：US12335809
申请日：2008-12-16
申请人： Guy L. Guthrie , Thomas L. Jeremiah , William L. McNeil , Piyush C. Patel , William J. Starke , Jeffrey A. Stuecheli
发明人： Guy L. Guthrie , Thomas L. Jeremiah , William L. McNeil , Piyush C. Patel , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/126 , G06F12/0817 , G06F12/0862 , G06F12/0897 , Y02D10/13
摘要： A cache memory includes a cache array including a plurality of congruence classes each containing a plurality of cache lines, where each cache line belongs to one of multiple classes which include at least a first class and a second class. The cache memory also includes a cache directory of the cache array that indicates class membership. The cache memory further includes a cache controller that selects a victim cache line for eviction from a congruence class. If the congruence class contains a cache line belonging to the second class, the cache controller preferentially selects as the victim cache line a cache line of the congruence class belonging to the second class based upon access order. If the congruence class contains no cache line belonging to the second class, the cache controller selects as the victim cache line a cache line belonging to the first class based upon access order.
摘要翻译：高速缓存存储器包括包含多个等同类的高速缓存阵列，每个级别包含多条高速缓存行，其中每条高速缓存行属于至少包括第一类和第二类的多个类中的一个。缓存存储器还包括指示类成员资格的高速缓存阵列的高速缓存目录。高速缓冲存储器还包括高速缓存控制器，其选择用于从同余类驱逐的受害缓存行。如果同余类包含属于第二类的高速缓存行，则高速缓存控制器基于访问顺序优先选择属于第二类的同余类的高速缓存行作为受害缓存行。如果同余类不包含属于第二类的高速缓存行，则高速缓存控制器基于访问顺序选择属于第一类的高速缓存行作为受害缓存行。

53. 发明申请

US20080071994A1 Processor, Data Processing System and Method Supporting Improved Coherency Management of Castouts 有权
标题翻译：处理器，数据处理系统和方法支持改进的Castouts的一致性管理
公开(公告)号：US20080071994A1
公开(公告)日：2008-03-20
申请号：US11532981
申请日：2006-09-19
申请人： James S. Fields , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： James S. Fields , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/0804 , G06F12/0815
摘要： According to one embodiment, a method of coherency management in a data processing system includes holding a cache line in an upper level cache memory in an exclusive ownership coherency state and thereafter removing the cache line from the upper level cache memory and transmitting a castout request for the cache line from the upper level cache memory to a lower level cache memory. The castout request includes an indication of a shared ownership coherency state. In response to the castout request, the cache line is placed in the lower level cache memory in a coherency state determined in accordance with the castout request.
摘要翻译：根据一个实施例，一种数据处理系统中的一致性管理方法包括：将高速缓存行以独占所有权一致性状态保存在上级高速缓冲存储器中，之后从高级缓存存储器中移除高速缓存行，从高级缓存存储器到高级缓存的高速缓存行。丢弃请求包括共享所有权一致性状态的指示。响应于抛出请求，高速缓存行以根据转储请求确定的一致性状态被放置在较低级高速缓冲存储器中。

54. 发明申请

US20080120473A1 Data Processing System, Method and Interconnect Fabric that Protect Ownership Transfer with Non-Uniform Protection Windows 失效
标题翻译：数据处理系统，方法和互连结构，保护所有权转移与非均匀保护Windows
公开(公告)号：US20080120473A1
公开(公告)日：2008-05-22
申请号：US11560603
申请日：2006-11-16
申请人： James S. Fields , Benjiman L. Goodman , Guy L. Guthie , William J. Starke , Jeffrey A. Stuecheli
发明人： James S. Fields , Benjiman L. Goodman , Guy L. Guthie , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0833
摘要： In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Within data storage in the data processing system, a data structure indicates a duration of a protection window extension for each of the plurality of agents. Each protection window extension is a period following receipt of a combined response during which an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. Each of the plurality of agents is configured with a duration of a protection window extension by reference to the data structure, and at least two of the agents have protection window extensions of differing durations. The plurality of agents thereafter employ the configured protection window extensions.
摘要翻译：在数据处理系统中，多个代理之间进行通信。每个操作包括一个请求和组合的响应，代表对该请求的全系统响应。在数据处理系统中的数据存储中，数据结构指示多个代理中的每一个的保护窗口扩展的持续时间。每个保护窗口扩展是接收到组合响应之后的周期，在该周期期间，所述多个代理中的相关联的一个代理保护代理之间的数据粒子的一致性所有权的传送。通过参考数据结构，多个代理中的每一个配置有保护窗口扩展的持续时间，并且至少两个代理具有不同持续时间的保护窗口扩展。此后，多个代理程序采用配置的保护窗口扩展。

55. 发明授权

US07689771B2 Coherency management of castouts 有权
标题翻译： castouts的一致性管理
公开(公告)号：US07689771B2
公开(公告)日：2010-03-30
申请号：US11532981
申请日：2006-09-19
申请人： James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0804 , G06F12/0815
摘要： According to one embodiment, a method of coherency management in a data processing system includes holding a cache line in an upper level cache memory in an exclusive ownership coherency state and thereafter removing the cache line from the upper level cache memory and transmitting a castout request for the cache line from the upper level cache memory to a lower level cache memory. The castout request includes an indication of a shared ownership coherency state. In response to the castout request, the cache line is placed in the lower level cache memory in a coherency state determined in accordance with the castout request.
摘要翻译：根据一个实施例，一种数据处理系统中的一致性管理方法包括：将高速缓存行以独占所有权一致性状态保存在上级高速缓冲存储器中，之后从高级缓存存储器中移除高速缓存行，从高级缓存存储器到高级缓存的高速缓存行。丢弃请求包括共享所有权一致性状态的指示。响应于抛出请求，高速缓存行以根据转储请求确定的一致性状态被放置在较低级高速缓冲存储器中。

56. 发明授权

US07447844B2 Data processing system, processor and method of data processing in which local memory access requests are serviced on a fixed schedule 失效
标题翻译：数据处理系统，处理器和数据处理方法，其中本地存储器访问请求以固定的时间表被服务
公开(公告)号：US07447844B2
公开(公告)日：2008-11-04
申请号：US11457322
申请日：2006-07-13
申请人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/1425 , G06F12/0817 , G06F12/0897
摘要： A processing unit includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array. The cache memory further includes one or more state machines that service a first set of memory access requests, an arbiter that directs servicing of a second set of memory access requests by reference to the data array and the directory on a fixed schedule, address collision logic that protects memory access requests in the second set by detecting and signaling address conflicts between active memory access requests in the second set and subsequent memory access requests, and dispatch logic coupled to the address collision logic. The dispatch logic dispatches memory access requests in the first set to the one or more state machines for servicing and signals the arbiter to direct servicing of memory access requests in the second set according to the fixed schedule.
摘要翻译：处理单元包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。高速缓冲存储器包括数据阵列，数据阵列的内容目录。缓存存储器还包括服务于第一组存储器访问请求的一个或多个状态机，通过参考数据阵列和固定时间表上的目录来指导第二组存储器访问请求的服务的仲裁器，地址冲突逻辑其通过检测和发出第二组中的活动存储器访问请求与后续存储器访问请求之间的地址冲突以及耦合到地址冲突逻辑的调度逻辑来保护第二组中的存储器访问请求。调度逻辑将第一组中的存储器访问请求分派到一个或多个状态机用于服务，并且向仲裁器发出信号，以根据固定的时间表对第二组中的存储器访问请求进行直接服务。

57. 发明申请

US20080016279A1 Data Processing System, Processor and Method of Data Processing in which Local Memory Access Requests are Serviced by State Machines with Differing Functionality 失效
标题翻译：数据处理系统，处理器和数据处理方法，其中本地存储器访问请求由具有不同功能的状态机服务
公开(公告)号：US20080016279A1
公开(公告)日：2008-01-17
申请号：US11457333
申请日：2006-07-13
申请人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0817 , G06F12/1416
摘要： A data processing system includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array, at least one snoop machine that services memory access requests of a remote processor core, and multiple state machines that service memory access requests of the local processor core. The multiple state machines include a first state machine that has a first set of memory access requests of the local processor core that it is capable of servicing and a second state machine that has a different second set of memory access requests of the local processor core that it is capable of servicing.
摘要翻译：数据处理系统包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。高速缓冲存储器包括数据阵列，数据阵列的内容目录，至少一个服务于远程处理器核的存储器访问请求的窥探机器，以及服务于本地处理器核心的存储器访问请求的多个状态机。多状态机包括第一状态机，其具有能够服务的本地处理器核心的第一组存储器访问请求;以及第二状态机，其具有本地处理器核心的不同的第二组存储器访问请求，它能够维修。

58. 发明授权

US07447845B2 Data processing system, processor and method of data processing in which local memory access requests are serviced by state machines with differing functionality 失效
标题翻译：数据处理系统，处理器和数据处理方法，其中本地存储器访问请求由具有不同功能的状态机服务
公开(公告)号：US07447845B2
公开(公告)日：2008-11-04
申请号：US11457333
申请日：2006-07-13
申请人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0817 , G06F12/1416
摘要： A data processing system includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array, at least one snoop machine that services memory access requests of a remote processor core, and multiple state machines that service memory access requests of the local processor core. The multiple state machines include a first state machine that has a first set of memory access requests of the local processor core that it is capable of servicing and a second state machine that has a different second set of memory access requests of the local processor core that it is capable of servicing.
摘要翻译：数据处理系统包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。高速缓冲存储器包括数据阵列，数据阵列的内容目录，至少一个服务于远程处理器核的存储器访问请求的窥探机器，以及服务于本地处理器核心的存储器访问请求的多个状态机。多状态机包括第一状态机，其具有能够服务的本地处理器核心的第一组存储器访问请求;以及第二状态机，其具有本地处理器核心的不同的第二组存储器访问请求，它能够维修。

59. 发明申请

US20080016278A1 Data Processing System, Processor and Method of Data Processing in which Local Memory Access Requests are Serviced on a Fixed Schedule 失效
标题翻译：数据处理系统，处理器和数据处理方法，其中本地存储器访问请求在固定时间表上服务
公开(公告)号：US20080016278A1
公开(公告)日：2008-01-17
申请号：US11457322
申请日：2006-07-13
申请人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/1425 , G06F12/0817 , G06F12/0897
摘要： A processing unit includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array. The cache memory further includes one or more state machines that service a first set of memory access requests, an arbiter that directs servicing of a second set of memory access requests by reference to the data array and the directory on a fixed schedule, address collision logic that protects memory access requests in the second set by detecting and signaling address conflicts between active memory access requests in the second set and subsequent memory access requests, and dispatch logic coupled to the address collision logic. The dispatch logic dispatches memory access requests in the first set to the one or more state machines for servicing and signals the arbiter to direct servicing of memory access requests in the second set according to the fixed schedule.
摘要翻译：处理单元包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。高速缓冲存储器包括数据阵列，数据阵列的内容目录。缓存存储器还包括服务于第一组存储器访问请求的一个或多个状态机，通过参考数据阵列和固定时间表上的目录来指导第二组存储器访问请求的服务的仲裁器，地址冲突逻辑其通过检测和发出第二组中的活动存储器访问请求与后续存储器访问请求之间的地址冲突以及耦合到地址冲突逻辑的调度逻辑来保护第二组中的存储器访问请求。调度逻辑将第一组中的存储器访问请求分派到一个或多个状态机用于服务，并且向仲裁器发出信号，以根据固定的时间表对第二组中的存储器访问请求进行直接服务。

60. 发明授权

US08254411B2 Data processing system, method and interconnect fabric having a flow governor 有权
标题翻译：具有流量调节器的数据处理系统，方法和互连结构
公开(公告)号：US08254411B2
公开(公告)日：2012-08-28
申请号：US11055399
申请日：2005-02-10
申请人： Leo J. Clark , Guy L. Guthrie , William J. Starke
发明人： Leo J. Clark , Guy L. Guthrie , William J. Starke
IPC分类号： H04J3/16 , H04J3/22 , G06F13/00 , G06F15/173
CPC分类号： H04L47/722 , H04L47/70 , H04L49/109
摘要： A data processing system includes a plurality of local hubs each coupled to a remote hub by a respective one a plurality of point-to-point communication links. Each of the plurality of local hubs queues requests for access to memory blocks for transmission on a respective one of the point-to-point communication links to a shared resource in the remote hub. Each of the plurality of local hubs transmits requests to the remote hub utilizing only a fractional portion of a bandwidth of its respective point-to-point communication link. The fractional portion that is utilized is determined by an allocation policy based at least in part upon a number of the plurality of local hubs and a number of processing units represented by each of the plurality of local hubs. The allocation policy prevents overruns of the shared resource.
摘要翻译：数据处理系统包括多个本地集线器，每个集线器通过相应的一个多个点对点通信链路耦合到远程集线器。多个本地集线器中的每一个排队对存储器块进行访问的请求，用于在到远程集线器中的共享资源的点对点通信链路中的相应一个上传输。多个本地集线器中的每一个仅利用其相应点对点通信链路的带宽的小数部分向远程集线器发送请求。所使用的分数部分由至少部分地基于多个本地集线器的数量和由多个本地集线器中的每一个表示的多个处理单元的分配策略确定。分配策略可以防止超出共享资源。

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