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1. 发明授权

US07761631B2 Data processing system, method and interconnect fabric supporting destination data tagging 失效
标题翻译：数据处理系统，方法和互连结构支持目标数据标记
公开(公告)号：US07761631B2
公开(公告)日：2010-07-20
申请号：US12117539
申请日：2008-05-08
申请人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
发明人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F13/42 , G06F13/00
CPC分类号： G06F15/16
摘要： A data processing system includes a plurality of communication links and a plurality of processing units including a local master processing unit. The local master processing unit includes interconnect logic that couples the processing unit to one or more of the plurality of communication links and an originating master coupled to the interconnect logic. The originating master originates an operation by issuing a write-type request on at least one of the one or more communication links, receives from a snooper in the data processing system a destination tag identifying a route to the snooper, and, responsive to receipt of the combined response and the destination tag, initiates a data transfer including a data payload and a data tag identifying the route provided within the destination tag.
摘要翻译：数据处理系统包括多个通信链路和包括本地主处理单元的多个处理单元。本地主处理单元包括将处理单元耦合到多个通信链路中的一个或多个以及耦合到互连逻辑的始发主机的互连逻辑。始发主机通过在一个或多个通信链路中的至少一个发出写入请求来发起操作，从数据处理系统中的窥探者接收标识到窥探者的路由的目的地标签，并且响应于接收到组合响应和目的地标签，发起包括数据有效载荷和标识目的地标签内提供的路由的数据标签的数据传输。

2. 发明授权

US07512742B2 Data processing system, cache system and method for precisely forming an invalid coherency state indicating a broadcast scope 失效
标题翻译：数据处理系统，缓存系统和精确形成指示广播范围的无效一致性状态的方法
公开(公告)号：US07512742B2
公开(公告)日：2009-03-31
申请号：US11333615
申请日：2006-01-17
申请人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
发明人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a memory block is held in a storage location associated with an address tag and a coherency state field. A determination is made if a home system memory assigned an address associated with the memory block is within the first coherency domain. If not, the coherency state field is set to a coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, the first coherency domain does not contain the home system memory, and that, following formation of the coherency state, the memory block is cached outside of the first coherency domain.
摘要翻译：缓存相干数据处理系统至少包括第一和第二相干域。在数据处理系统的第一相关域内的第一高速缓存存储器中，存储块被保存在与地址标签和一致性状态字段相关联的存储位置中。如果分配了与存储器块相关联的地址的归属系统存储器在第一相关域内，则确定。如果不是，则将一致性状态字段设置为指示地址标签有效的一致性状态，即存储位置不包含有效数据，第一相干域不包含家庭系统存储器，并且在形成一致性状态下，内存块被缓存在第一个相干域之外。

3. 发明授权

US07409481B2 Data processing system, method and interconnect fabric supporting destination data tagging 有权
标题翻译：数据处理系统，方法和互连结构支持目标数据标记
公开(公告)号：US07409481B2
公开(公告)日：2008-08-05
申请号：US11055405
申请日：2005-02-10
申请人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
发明人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F13/42 , G06F13/00
CPC分类号： G06F15/16
摘要： A data processing system includes a plurality of communication links and a plurality of processing units including a local master processing unit. The local master processing unit includes interconnect logic that couples the processing unit to one or more of the plurality of communication links and an originating master coupled to the interconnect logic. The originating master originates an operation by issuing a write-type request on at least one of the one or more communication links, receives from a snooper in the data processing system a destination tag identifying a route to the snooper, and, responsive to receipt of the combined response and the destination tag, initiates a data transfer including a data payload and a data tag identifying the route provided within the destination tag.
摘要翻译：数据处理系统包括多个通信链路和包括本地主处理单元的多个处理单元。本地主处理单元包括将处理单元耦合到多个通信链路中的一个或多个以及耦合到互连逻辑的始发主机的互连逻辑。始发主机通过在一个或多个通信链路中的至少一个发出写入请求来发起操作，从数据处理系统中的窥探者接收标识到窥探者的路由的目的地标签，并且响应于接收到组合响应和目的地标签，发起包括数据有效载荷和标识目的地标签内提供的路由的数据标签的数据传输。

4. 发明申请

US20080120625A1 Data Processing System, Method and Interconnect Fabric that Protect Ownership Transfer with Non-Uniform Protection Windows 有权
标题翻译：数据处理系统，方法和互连结构，保护所有权转移与非均匀保护Windows
公开(公告)号：US20080120625A1
公开(公告)日：2008-05-22
申请号：US11560619
申请日：2006-11-16
申请人： Leo J. Clark , James S. Fields , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , James S. Fields , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F9/44
CPC分类号： G06F15/173
摘要： In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Latencies of requests and combined responses between the plurality of agents are observed. Each of the plurality of agents is configured with a respective duration of a protection window extension by reference to the observed latencies. Each protection window extension is a period following receipt of a combined response during winch an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. The plurality of agents employing protection window extensions in accordance with the configuration, and at least two of the agents have protection window extensions of differing durations.
摘要翻译：在数据处理系统中，多个代理之间进行通信。每个操作包括一个请求和组合的响应，代表对该请求的全系统响应。观察到请求的延迟和多个代理之间的组合响应。通过参考所观察到的延迟，多个代理中的每个被配置有保护窗口扩展的相应持续时间。每个保护窗口扩展是在绞盘期间接收到组合响应之后的周期，多个代理之一相关联的一个代理保护代理之间的数据粒子的一致性所有权的传送。多个代理根据配置使用保护窗口扩展，并且至少两个代理具有不同持续时间的保护窗口扩展。

5. 发明授权

US08140770B2 Data processing system and method for predictively selecting a scope of broadcast of an operation 有权
标题翻译：用于预测性地选择操作的广播范围的数据处理系统和方法
公开(公告)号：US08140770B2
公开(公告)日：2012-03-20
申请号：US11054886
申请日：2005-02-10
申请人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke
发明人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/0844 , G06F12/0817 , G06F12/0831
摘要： A cache coherent data processing system includes at least first and second coherency domains coupled for communication. The first and second coherency domains each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains based, at least in part, upon a type of the operation. The master then performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.
摘要翻译：高速缓存一致数据处理系统至少包括耦合用于通信的第一和第二相干域。第一和第二相关域各自包括第一和第二高速缓存存储器中的相应一个。第一相关域中的主机至少部分地基于类型，从包括第一相关域的第一范围和包括第一和第二相干域两者的第二范围中选择操作的初始广播的范围的操作。然后，主机使用所选择的范围在高速缓存相干数据处理系统内执行操作的初始广播。

6. 发明授权

US07447844B2 Data processing system, processor and method of data processing in which local memory access requests are serviced on a fixed schedule 失效
标题翻译：数据处理系统，处理器和数据处理方法，其中本地存储器访问请求以固定的时间表被服务
公开(公告)号：US07447844B2
公开(公告)日：2008-11-04
申请号：US11457322
申请日：2006-07-13
申请人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/1425 , G06F12/0817 , G06F12/0897
摘要： A processing unit includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array. The cache memory further includes one or more state machines that service a first set of memory access requests, an arbiter that directs servicing of a second set of memory access requests by reference to the data array and the directory on a fixed schedule, address collision logic that protects memory access requests in the second set by detecting and signaling address conflicts between active memory access requests in the second set and subsequent memory access requests, and dispatch logic coupled to the address collision logic. The dispatch logic dispatches memory access requests in the first set to the one or more state machines for servicing and signals the arbiter to direct servicing of memory access requests in the second set according to the fixed schedule.
摘要翻译：处理单元包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。高速缓冲存储器包括数据阵列，数据阵列的内容目录。缓存存储器还包括服务于第一组存储器访问请求的一个或多个状态机，通过参考数据阵列和固定时间表上的目录来指导第二组存储器访问请求的服务的仲裁器，地址冲突逻辑其通过检测和发出第二组中的活动存储器访问请求与后续存储器访问请求之间的地址冲突以及耦合到地址冲突逻辑的调度逻辑来保护第二组中的存储器访问请求。调度逻辑将第一组中的存储器访问请求分派到一个或多个状态机用于服务，并且向仲裁器发出信号，以根据固定的时间表对第二组中的存储器访问请求进行直接服务。

7. 发明申请

US20080016279A1 Data Processing System, Processor and Method of Data Processing in which Local Memory Access Requests are Serviced by State Machines with Differing Functionality 失效
标题翻译：数据处理系统，处理器和数据处理方法，其中本地存储器访问请求由具有不同功能的状态机服务
公开(公告)号：US20080016279A1
公开(公告)日：2008-01-17
申请号：US11457333
申请日：2006-07-13
申请人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0817 , G06F12/1416
摘要： A data processing system includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array, at least one snoop machine that services memory access requests of a remote processor core, and multiple state machines that service memory access requests of the local processor core. The multiple state machines include a first state machine that has a first set of memory access requests of the local processor core that it is capable of servicing and a second state machine that has a different second set of memory access requests of the local processor core that it is capable of servicing.
摘要翻译：数据处理系统包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。高速缓冲存储器包括数据阵列，数据阵列的内容目录，至少一个服务于远程处理器核的存储器访问请求的窥探机器，以及服务于本地处理器核心的存储器访问请求的多个状态机。多状态机包括第一状态机，其具有能够服务的本地处理器核心的第一组存储器访问请求;以及第二状态机，其具有本地处理器核心的不同的第二组存储器访问请求，它能够维修。

8. 发明授权

US07475195B2 Data processing system, cache system and method for actively scrubbing a domain indication 失效
标题翻译：数据处理系统，缓存系统和方法，用于主动清理域指示
公开(公告)号：US07475195B2
公开(公告)日：2009-01-06
申请号：US11136651
申请日：2005-05-24
申请人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F12/0822
摘要： Scrubbing logic in a local coherency domain issues to at least one cache hierarchy in a remote coherency domain a domain reset request that forces invalidation of any cached copy of a target memory block then held in said remote coherency domain. A coherency response to said domain reset request is received. In response to said coherency response indicating that said target memory block is not cached in said remote coherency domain, a domain indication of said local coherency domain is updated to indicate that said target memory block is cached, if at all, only within said local coherency domain.
摘要翻译：本地一致性域中的擦除逻辑向远程一致性域中的至少一个高速缓存层次结构发出一个域重置请求，该请求强制所保存在所述远程一致性域中的目标存储器块的任何高速缓存副本的无效。接收到对所述域重置请求的一致性响应。响应于所述相关性响应指示所述目标存储器块未被高速缓存在所述远程一致性域中，所述本地一致性域的域指示被更新以指示所述目标存储器块被缓存，如果完全只在所述局部一致性内域。

9. 发明授权

US07254694B2 Processors interconnect fabric with relay broadcasting and accumulation of partial responses 失效
标题翻译：处理器将结构与中继广播和部分响应的积累互连
公开(公告)号：US07254694B2
公开(公告)日：2007-08-07
申请号：US11055297
申请日：2005-02-10
申请人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
发明人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F15/16
CPC分类号： G06F13/385 , G06F9/546
摘要： A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts requests received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units. The interconnect logic includes a partial response data structure including a plurality of entries each associating a partial response field with a plurality of flags respectively associated with each processing unit containing a snooper from which that processing unit will receive a partial response. The interconnect logic accumulates partial responses of processing units by reference to the partial response field to obtain an accumulated partial response, and when the plurality of flags indicate that all processing units from which partial responses are expected have returned a partial response, outputs the accumulated partial response.
摘要翻译：数据处理系统包括多个处理单元，每个处理单元各自具有与多个处理单元中的多个其他处理单元中的每一个相对的点对点通信链路，但是比所有多个处理单元少。多个处理单元中的每一个包括互连逻辑，其耦合到该处理单元的每个点对点通信链路，其将从多个处理单元中的多个其中一个的接收的请求广播到多个处理单元中的一个或多个处理单位。互连逻辑包括部分响应数据结构，其包括多个条目，每个条目将部分响应字段与分别与包含窥探者的每个处理单元相关联的多个标志相关联，该处理单元将从该处理单元接收部分响应。互连逻辑通过参考部分响应字段积累处理单元的部分响应以获得累积的部分响应，并且当多个标志指示预期部分响应的所有处理单元已经返回部分响应时，输出累积的部分响应响应。

10. 发明授权

US08205024B2 Protecting ownership transfer with non-uniform protection windows 有权
标题翻译：用不均匀的保护窗保护所有权转让
公开(公告)号：US08205024B2
公开(公告)日：2012-06-19
申请号：US11560619
申请日：2006-11-16
申请人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F15/173
摘要： In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Latencies of requests and combined responses between the plurality of agents are observed. Each of the plurality of agents is configured with a respective duration of a protection window extension by reference to the observed latencies. Each protection window extension is a period following receipt of a combined response during winch an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. The plurality of agents employing protection window extensions in accordance with the configuration, and at least two of the agents have protection window extensions of differing durations.
摘要翻译：在数据处理系统中，多个代理之间进行通信。每个操作包括一个请求和组合的响应，代表对该请求的全系统响应。观察到请求的延迟和多个代理之间的组合响应。通过参考所观察到的延迟，多个代理中的每个被配置有保护窗口扩展的相应持续时间。每个保护窗口扩展是在绞盘期间接收到组合响应之后的周期，多个代理之一相关联的一个代理保护代理之间的数据粒子的一致性所有权的传送。多个代理根据配置使用保护窗口扩展，并且至少两个代理具有不同持续时间的保护窗口扩展。

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