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51. 发明申请

US20100246814A1 APPARATUS AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR THE DATA ENCRYPTION STANDARD (DES) ALGORITHM 有权
标题翻译：用于实施数据加密标准（DES）算法的指令支持的装置和方法
公开(公告)号：US20100246814A1
公开(公告)日：2010-09-30
申请号：US12414755
申请日：2009-03-31
申请人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
发明人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
IPC分类号： H04L9/06
CPC分类号： G06F21/72 , G06F9/30007 , H04L9/0625 , H04L2209/122 , H04L2209/125 , H04L2209/24
摘要： A processor including instruction support for implementing the Data Encryption Standard (DES) block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more DES instructions defined within the ISA. In addition, the DES instructions may be executable by the cryptographic unit to implement portions of an DES cipher that is compliant with Federal Information Processing Standards Publication 46-3 (FIPS 46-3). In response to receiving a DES key expansion instruction defined within the ISA, the cryptographic unit may generate one or more expanded cipher keys of the DES cipher key schedule from an input key.
摘要翻译：包括用于实现数据加密标准（DES）块密码算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发出执行编程器可选择的指令。处理器可以包括可以接收执行指令的密码单元。指令包括在ISA内定义的一个或多个DES指令。此外，DES指令可以由加密单元执行，以实现符合联邦信息处理标准出版物46-3（FIPS 46-3）的DES密码的部分。响应于接收到在ISA内定义的DES密钥扩展指令，密码单元可以从输入密钥生成DES密码密钥调度的一个或多个扩展密码密钥。

52. 发明授权

US07437538B1 Apparatus and method for reducing execution latency of floating point operations having special case operands 有权
标题翻译：具有特殊情况操作数的浮点运算减少执行延迟的装置和方法
公开(公告)号：US07437538B1
公开(公告)日：2008-10-14
申请号：US10881763
申请日：2004-06-30
申请人： Jeffrey S. Brooks , Christopher H. Olson
发明人： Jeffrey S. Brooks , Christopher H. Olson
IPC分类号： G06F9/40
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30123 , G06F9/3013 , G06F9/3828 , G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3877 , G06F9/3891
摘要： An apparatus and method for floating-point special case handling. In one embodiment, a processor may include a first execution unit configured to execute a longer-latency floating-point instruction, and a second execution unit configured to execute a shorter-latency floating-point instruction. In response to the longer-latency floating-point instruction being issued to the first execution unit, the second execution unit may be further configured to detect whether a result of the longer-latency floating-point instruction is determinable from one or more operands of the longer-latency floating-point instruction independently of the first execution unit executing the longer-latency floating-point instruction. In response to detecting that the result is determinable, the second execution unit may be further configured to flush the longer-latency floating-point instruction from the first execution unit and to determine the result.
摘要翻译：一种用于浮点特殊情况处理的装置和方法。在一个实施例中，处理器可以包括被配置为执行较长延迟浮点指令的第一执行单元，以及被配置为执行较短延迟浮点指令的第二执行单元。响应于向第一执行单元发出的较长延迟的浮点指令，第二执行单元还可以被配置为检测长延迟浮点指令的结果是否可以从所述第一执行单元的一个或多个操作数确定更长延迟的浮点指令独立于执行较长延迟浮点指令的第一执行单元。响应于检测到结果是可确定的，第二执行单元可以被进一步配置为从第一执行单元刷新长延迟浮点指令并确定结果。

53. 发明授权

US07099910B2 Partitioned shifter for single instruction stream multiple data stream (SIMD) operations 有权
标题翻译：用于单指令流分多个数据流（SIMD）操作的分区移位器
公开(公告)号：US07099910B2
公开(公告)日：2006-08-29
申请号：US10408132
申请日：2003-04-07
申请人： Jeffrey S. Brooks , Christopher H. Olson , Paul J. Jagodik
发明人： Jeffrey S. Brooks , Christopher H. Olson , Paul J. Jagodik
IPC分类号： G06F7/485
CPC分类号： G06F7/485 , G06F5/012 , G06F2207/382 , G06F2207/3828
摘要： A method of enabling a single instruction stream multiple data stream operation and a double precision floating point operation within a single floating point execution unit which includes providing a floating point unit with a two way aligner and a two way normalizer, selectively aligning a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed, and selectively normalizing a value based upon whether a single instruction stream multiple data stream operation is to be performed or a double precision operation is to be performed.
摘要翻译：一种在单个浮点执行单元内实现单指令流多数据流操作和双精度浮点运算的方法，该方法包括：提供具有双向对准器和双向归一化器的浮点单元，要执行单个指令流多数据流操作还是执行双精度操作，并且基于是要执行单个指令流多数据流操作还是双精度操作来选择性地归一化值被执行。

54. 发明授权

US06361645B1 Method and device for compensating wafer bias in a plasma processing chamber 有权
标题翻译：用于补偿等离子体处理室中的晶片偏置的方法和装置
公开(公告)号：US06361645B1
公开(公告)日：2002-03-26
申请号：US09169017
申请日：1998-10-08
申请人： Alan M. Schoepp , Robert E. Knop , Christopher H. Olson , Michael S. Barnes , Tuan M. Ngo
发明人： Alan M. Schoepp , Robert E. Knop , Christopher H. Olson , Michael S. Barnes , Tuan M. Ngo
IPC分类号： H02N1300
CPC分类号： H01J37/32706 , H01J37/3299 , H01L21/6833
摘要： Disclosed is a method and device for compensating a bias voltage on a wafer disposed over an electrostatic chuck in a processing chamber of a plasma processing system. The plasma processing system includes an electrostatic and RF power supplies that are coupled to the electrostatic chuck. The bias compensation device includes a voltage converter, a storage unit, and a voltage adjusting circuitry. The voltage converter is coupled to the electrostatic chuck for detecting a voltage Vpp of the electrostatic chuck. The voltage converter converts the detected voltage to a lower voltage Vref. The storage unit stores a predetermined slope and a predetermined offset of a calibration curve, which is derived by fitting a plurality of wafer bias voltages as a function of electrostatic chuck voltages.
摘要翻译：公开了一种用于补偿在等离子体处理系统的处理室中设置在静电卡盘上的晶片上的偏置电压的方法和装置。等离子体处理系统包括耦合到静电卡盘的静电和RF电源。偏置补偿装置包括电压转换器，存储单元和电压调节电路。电压转换器耦合到静电卡盘，用于检测静电卡盘的电压Vpp。电压转换器将检测到的电压转换成较低的电压Vref。存储单元存储通过拟合作为静电卡盘电压的函数的多个晶片偏置电压导出的校准曲线的预定斜率和预定偏移。

55. 发明授权

US5803107A Method and apparatus for pressure control in vacuum processors 失效
标题翻译：真空处理器中压力控制的方法和装置
公开(公告)号：US5803107A
公开(公告)日：1998-09-08
申请号：US627711
申请日：1996-03-29
申请人： Farro Frank Kaveh , Michael S. Barnes , Brett C. Richardson , Christopher H. Olson
发明人： Farro Frank Kaveh , Michael S. Barnes , Brett C. Richardson , Christopher H. Olson
IPC分类号： H01L21/302 , B01J3/02 , F16K31/12 , F16K31/36 , G05D16/20 , H01L21/3065 , F17D1/16 , F16K17/34 , F17D1/18
CPC分类号： G05D16/202 , Y10S438/909 , Y10T137/0396 , Y10T137/2572 , Y10T137/7761
摘要： A method and apparatus is disclosed for controlling the pressure of reaction chamber in wafer processing equipment. The disclosed apparatus and method uses a ballast port for inserting gas into the evacuation system, thereby controlling the pressure in the reaction chamber. The disclosed apparatus and method further uses estimation curves to estimate the desired position of a controlled gate valve which is located between the reaction chamber and turbo pump. The disclosed apparatus and method further introduces process gases at higher rate than set point levels to reduce the transition time or stabilization time required when raising the pressure in the reaction chamber.
摘要翻译：公开了一种用于控制晶片加工设备中的反应室的压力的方法和装置。所公开的装置和方法使用用于将气体插入抽空系统中的压载端口，从而控制反应室中的压力。所公开的装置和方法还使用估计曲线来估计位于反应室和涡轮泵之间的受控闸阀的期望位置。所公开的装置和方法进一步介绍了比设定点水平更高的处理气体，以减少在提高反应室中的压力时所需的过渡时间或稳定时间。

56. 发明授权

US09086890B2 Division unit with normalization circuit and plural divide engines for receiving instructions when divide engine availability is indicated 有权
标题翻译：分配单元具有归一化电路和多个除法引擎，用于在分配发动机可用性时指示
公开(公告)号：US09086890B2
公开(公告)日：2015-07-21
申请号：US13345391
申请日：2012-01-06
申请人： Christopher H. Olson , Jeffrey S. Brooks , Matthew B. Smittle
发明人： Christopher H. Olson , Jeffrey S. Brooks , Matthew B. Smittle
IPC分类号： G06F9/38 , G06F7/535 , G06F7/537 , G06F9/30 , G06F7/499
CPC分类号： G06F9/3895 , G06F7/49936 , G06F7/535 , G06F7/5375 , G06F9/3001 , G06F9/3875 , G06F9/3885
摘要： Techniques are disclosed relating to integrated circuits that include hardware support for divide and/or square root operations. In one embodiment, an integrated circuit is disclosed that includes a division unit that, in turn, includes a normalization circuit and a plurality of divide engines. The normalization circuit is configured to normalize a set of operands. Each divide engine is configured to operate on a respective normalized set of operands received from the normalization circuit. In some embodiments, the integrated circuit includes a scheduler unit configured to select instructions for issuance to a plurality of execution units including the division unit. The scheduler unit is further configured to maintain a counter indicative of a number of instructions currently being operated on by the division unit, and to determine, based on the counter whether to schedule subsequent instructions for issuance to the division unit.
摘要翻译：公开了涉及包括用于划分和/或平方根操作的硬件支持的集成电路的技术。在一个实施例中，公开了一种集成电路，其包括分割单元，该分割单元又包括归一化电路和多个除法引擎。归一化电路被配置为归一化一组操作数。每个分频引擎被配置为对从归一化电路接收的相应的归一化操作数集进行操作。在一些实施例中，集成电路包括调度器单元，其被配置为选择用于向包括该分割单元的多个执行单元发布的指令。调度器单元还被配置为保持指示当前正在由分割单元操作的指令的数量的计数器，并且基于计数器确定是否计划用于发布到分割单元的后续指令。

57. 发明授权

US08654970B2 Apparatus and method for implementing instruction support for the data encryption standard (DES) algorithm 有权
标题翻译：用于实现数据加密标准（DES）算法的指令支持的装置和方法
公开(公告)号：US08654970B2
公开(公告)日：2014-02-18
申请号：US12414755
申请日：2009-03-31
申请人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
发明人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
IPC分类号： H04K1/00 , H04L9/00
CPC分类号： G06F21/72 , G06F9/30007 , H04L9/0625 , H04L2209/122 , H04L2209/125 , H04L2209/24
摘要： A processor including instruction support for implementing the Data Encryption Standard (DES) block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more DES instructions defined within the ISA. In addition, the DES instructions may be executable by the cryptographic unit to implement portions of an DES cipher that is compliant with Federal Information Processing Standards Publication 46-3 (FIPS 46-3). In response to receiving a DES key expansion instruction defined within the ISA, the cryptographic unit may generate one or more expanded cipher keys of the DES cipher key schedule from an input key.
摘要翻译：包括用于实现数据加密标准（DES）块密码算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发出执行编程器可选择的指令。处理器可以包括可以接收执行指令的密码单元。指令包括在ISA内定义的一个或多个DES指令。此外，DES指令可以由加密单元执行，以实现符合联邦信息处理标准出版物46-3（FIPS 46-3）的DES密码的部分。响应于接收到在ISA内定义的DES密钥扩展指令，密码单元可以从输入密钥生成DES密码密钥调度的一个或多个扩展密码密钥。

58. 发明授权

US08555038B2 Processor and method providing instruction support for instructions that utilize multiple register windows 有权
标题翻译：处理器和方法为使用多个寄存器窗口的指令提供指令支持
公开(公告)号：US08555038B2
公开(公告)日：2013-10-08
申请号：US12790074
申请日：2010-05-28
申请人： Christopher H. Olson , Paul J. Jordan , Jama I. Barreh
发明人： Christopher H. Olson , Paul J. Jordan , Jama I. Barreh
IPC分类号： G06F9/00
CPC分类号： G06F9/30127 , G06F7/5324 , G06F9/30032 , G06F9/30043 , G06F9/30145 , G06F9/3824 , G06F9/384 , G06F9/3844 , G06F9/3851 , G06F9/3867 , G06F21/556
摘要： A processor including instruction support for large-operand instructions that use multiple register windows may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may also include an instruction execution unit that, during operation, receives instructions for execution from the instruction fetch unit and executes a large-operand instruction defined within the ISA, where execution of the large-operand instruction is dependent upon a plurality of registers arranged within a plurality of register windows. The processor may further include control circuitry (which may be included within the fetch unit, the execution unit, or elsewhere within the processor) that determines whether one or more of the register windows depended upon by the large-operand instruction are not present. In response to determining that one or more of these register windows are not present, the control circuitry causes them to be restored.
摘要翻译：包括对使用多个寄存器窗口的大操作数指令的指令支持的处理器可以从定义的指令集架构（ISA）发出用于执行编程器可选择指令的指令。处理器还可以包括指令执行单元，其在操作期间从指令获取单元接收执行指令，并执行在ISA内定义的大操作数指令，其中大操作数指令的执行取决于多个寄存器布置在多个寄存器窗口内。处理器还可以包括控制电路（其可以包括在提取单元，执行单元或处理器内的其他地方），其确定不存在大操作数指令所依赖的寄存器窗口中的一个或多个。响应于确定这些寄存器窗口中的一个或多个不存在，控制电路使它们被恢复。

59. 发明授权

US08468425B2 Register error correction of speculative data in an out-of-order processor 有权
标题翻译：在乱序处理器中注册误差校正数据
公开(公告)号：US08468425B2
公开(公告)日：2013-06-18
申请号：US13295554
申请日：2011-11-14
申请人： Paul J. Jordan , Christopher H. Olson
发明人： Paul J. Jordan , Christopher H. Olson
IPC分类号： G11C29/00 , H03M13/03
CPC分类号： G06F11/10
摘要： In one embodiment, a processor comprises a first register file configured to store speculative register state, a second register file configured to store committed register state, a check circuit and a control unit. The first register file is protected by a first error protection scheme and the second register file is protected by a second error protection scheme. A check circuit is coupled to receive a value and corresponding one or more check bits read from the first register file to be committed to the second register file in response to the processor selecting a first instruction to be committed. The check circuit is configured to detect an error in the value responsive to the value and the check bits. Coupled to the check circuit, the control unit is configured to cause reexecution of the first instruction responsive to the error detected by the check circuit.
摘要翻译：在一个实施例中，处理器包括被配置为存储推测寄存器状态的第一寄存器文件，被配置为存储提交寄存器状态的第二寄存器文件，检查电路和控制单元。第一个寄存器文件由第一个错误保护方案保护，第二个寄存器文件由第二个错误保护方案保护。耦合检查电路以响应于处理器选择要提交的第一指令，接收从第一寄存器文件读取的值和对应的一个或多个校验位以提交给第二寄存器堆。检查电路被配置为响应于该值和校验位来检测该值中的错误。耦合到检查电路，控制单元被配置为响应于由检查电路检测到的错误而引起第一指令的再次执行。

60. 发明授权

US08452831B2 Apparatus and method for implementing hardware support for denormalized operands for floating-point divide operations 有权
标题翻译：用于实现用于浮点除法运算的非归一化操作数的硬件支持的装置和方法
公开(公告)号：US08452831B2
公开(公告)日：2013-05-28
申请号：US12415370
申请日：2009-03-31
申请人： Christopher H. Olson , Jeffrey S. Brooks
发明人： Christopher H. Olson , Jeffrey S. Brooks
IPC分类号： G06F7/44 , G06F7/487
CPC分类号： G06F7/4873 , G06F7/49915 , G06F7/49936
摘要： A floating-point circuit may include a floating-point operand normalization circuit configured to receive input floating-point operands of a given floating-point divide operation, the operands comprising a dividend and a divisor, as well as a divide engine coupled to the normalization circuit. In response to determining that one or more of the input floating-point operands is a denormal number, the operand normalization circuit may be further configured to normalize the one or more of the input floating-point operands and output a normalized dividend and normalized divisor to the divide engine, and dependent upon respective numbers of leading zeros of the dividend and divisor prior to normalization, generate a value indicative of a maximum possible number of digits of a quotient (NDQ). The divide engine may be configured to iteratively generate NDQ digits of a floating-point quotient from the normalized dividend and the normalized divisor provided by the floating-point operand normalization circuit.
摘要翻译：浮点电路可以包括浮点操作数归一化电路，其被配置为接收给定浮点除法运算的输入浮点操作数，所述操作数包括除数和除数，以及耦合到归一化的除法引擎电路。响应于确定一个或多个输入浮点操作数是反正态数，操作数归一化电路还可以被配置为对输入浮点操作数中的一个或多个进行归一化，并将归一化的除数和归一化除数输出到除法引擎，并且依赖于归一化之前的除数和除数的前导零的相应数量，生成指示商（NDQ）的最大可能数位数的值。划分引擎可以被配置为从浮动点操作数归一化电路提供的归一化除数和归一化除数迭代生成浮点商的NDQ数字。

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