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51. 发明授权

US06300172B1 Method of field isolation in silicon-on-insulator technology 失效
标题翻译：硅绝缘体技术中的场隔离方法
公开(公告)号：US06300172B1
公开(公告)日：2001-10-09
申请号：US09409887
申请日：1999-10-01
申请人： Ting Cheong Ang , Shyue Pong Quek , Lap Chan , Sang Yee Loong
发明人： Ting Cheong Ang , Shyue Pong Quek , Lap Chan , Sang Yee Loong
IPC分类号： H01L2100
CPC分类号： H01L21/76264 , H01L21/76281
摘要： A method of fabricating an SOI transistor device comprises the following steps. a silicon semiconductor structure is provided. A silicon oxide layer is formed over the silicon semiconductor structure. A silicon-on-insulator layer is formed over the oxide layer. A well is implanted in the silicon-on-insulator layer. A gate oxide layer is grown over the silicon-on-insulator layer. A polysilicon layer is deposited over the gate oxide layer. The polysilicon layer, gate oxide layer, and silicon oxide layer are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised shallow trench isolation regions (STIs). The polysilicon layer is patterned and the non-gate portions are removed polysilicon adjacent the raised STIs forming a gate conductor between the raised STIs with the gate conductor and said raised STIs having exposed sidewalls. The gate oxide layer is removed between the gate conductor and the raised STIs, and outboard of the raised STIs. The source and drain are formed in the silicon-on-insulator layer adjacent the gate spacers. Silicide regions may then be formed on the source and drain.
摘要翻译：制造SOI晶体管器件的方法包括以下步骤。提供硅半导体结构。在硅半导体结构上形成氧化硅层。在氧化物层上形成绝缘体上硅层。将阱注入绝缘体上硅层中。栅氧化层生长在绝缘体上硅层上。在栅极氧化物层上沉积多晶硅层。对多晶硅层，栅极氧化物层和氧化硅层进行图案化和蚀刻以形成沟槽。沟槽用隔离材料填充至少甚至具有多晶硅层的顶表面的水平以形成凸起的浅沟槽隔离区域（STI）。多晶硅层被图案化，并且非栅极部分去除与凸起的STI相邻的多晶硅，其在栅极导体和所述凸起的STI具有暴露的侧壁之间在凸起的STI之间形成栅极导体。栅极氧化物层在栅极导体和凸起的STI之间以及凸起的STIs的外侧被移除。源极和漏极形成在邻近栅极间隔物的绝缘体上硅层中。然后可以在源极和漏极上形成硅化物区域。

52. 发明授权

US06274485B1 Method to reduce dishing in metal chemical-mechanical polishing 失效
标题翻译：减少金属化学机械抛光中的凹陷的方法
公开(公告)号：US06274485B1
公开(公告)日：2001-08-14
申请号：US09425310
申请日：1999-10-25
申请人： Feng Chen , Rick Teo , Lap Chan
发明人： Feng Chen , Rick Teo , Lap Chan
IPC分类号： H01L2144
CPC分类号： H01L21/7684
摘要： A new method of metal plug metallization utilizing a sacrificial high polishing rate layer to prevent dishing and metal residues after CMP is described. An oxide layer is provided overlying semiconductor device structures in and on a semiconductor substrate. A sacrificial high polishing rate (HPR) layer is deposited overlying the oxide layer. An opening is etched through the HPR layer and the oxide layer to one of the semiconductor device structures. A barrier layer and a metal layer are deposited over the surface of the HPR layer and within the opening. The metal layer, barrier layer, and HPR layer overlying the oxide layer are polished away by CMP. The polishing rate of the HPR layer is higher than that of the metal layer with the result that after the HPR layer is completely removed, the metal layer remaining within the opening has a convex shape. The oxide layer is over-polished until endpoint detection is received. Since the metal polishing rate is higher than the oxide polishing rate, the convex shape is made substantially planar during the over-polishing to complete metal plug metallization in the fabrication of an integrated circuit.
摘要翻译：描述了利用牺牲高抛光速率层以防止CMP之后的凹陷和金属残余物的金属插塞金属化的新方法。半导体衬底上半导体器件结构上覆盖氧化物层。牺牲高抛光速率（HPR）层沉积在氧化物层上。通过HPR层和氧化物层将开口蚀刻到半导体器件结构之一。阻挡层和金属层沉积在HPR层的表面上并且在开口内。覆盖氧化物层的金属层，阻挡层和HPR层通过CMP抛光。 HPR层的抛光速率高于金属层的抛光速率，结果是在HPR层被完全去除之后，残留在开口内的金属层具有凸形状。氧化层被过度抛光，直到接收端点检测。由于金属抛光速率高于氧化物研磨速度，因此在制造集成电路时，在抛光过程中使凸形形状基本上平坦，以完成金属插塞金属化。

53. 发明授权

US06221727B1 Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technology 有权
标题翻译：在硅基板上捕获空气的方法，以改善CMOS技术中RF电感器的品质因素
公开(公告)号：US06221727B1
公开(公告)日：2001-04-24
申请号：US09385524
申请日：1999-08-30
申请人： Lap Chan , Johnny Kok Wai Chew , Cher Liang Cha , Chee Tee Chua
发明人： Lap Chan , Johnny Kok Wai Chew , Cher Liang Cha , Chee Tee Chua
IPC分类号： H01L2120
CPC分类号： H01L28/10 , H01L21/764 , H01L27/08
摘要： A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacturing of integrated circuits is described. A field oxide region is formed in and on a semiconductor substrate and then removed whereby a well is left in the semiconductor substrate. A polish stop layer is deposited over the substrate and within the well. The polish stop layer is covered and the well filled with a spin-on-glass layer. The spin-on-glass layer is polished back to the polish stop layer. The said polish stop layer is removed. A first oxide layer is deposited overlying the spin-on-glass layer and the semiconductor substrate and is patterned using an inductor reticle whereby a plurality of openings are made through the first oxide layer to the spin-on-glass layer. All of the spin-on-glass layer within the well is removed through the plurality of openings. Thereafter, a second oxide layer is deposited overlying the first oxide layer and capping the plurality of openings thereby forming an air barrier within the well. A metal layer is deposited overlying the second oxide layer and patterned using the same inductor reticle to form the inductor in the fabrication of an integrated circuit device.
摘要翻译：描述了在制造集成电路中制造利用空气作为下层屏障的电感器的新方法。在半导体衬底中形成场氧化物区域，然后去除，从而在半导体衬底中留下阱。抛光停止层沉积在基底上并在孔内。抛光停止层被覆盖并充满了旋涂玻璃层。旋涂玻璃层被抛光回抛光停止层。所述抛光停止层被去除。沉积在旋涂玻璃层和半导体衬底上的第一氧化物层，并且使用电感器掩模版进行图案化，由此通过第一氧化物层到旋涂玻璃层制成多个开口。孔内的所有旋涂玻璃层通过多个开口被去除。此后，将第二氧化物层沉积在第一氧化物层上并覆盖多个开口，从而在该阱内形成空气屏障。沉积在第二氧化物层上的金属层，并使用相同的电感器掩模版进行图案化以在集成电路器件的制造中形成电感器。

54. 发明授权

US06207534B1 Method to form narrow and wide shallow trench isolations with different trench depths to eliminate isolation oxide dishing 有权
标题翻译：形成具有不同沟槽深度的窄而宽的浅沟槽隔离以消除隔离氧化物凹陷的方法
公开(公告)号：US06207534B1
公开(公告)日：2001-03-27
申请号：US09389632
申请日：1999-09-03
申请人： Lap Chan , Cher Liang Cha , Teck Koon Lee
发明人： Lap Chan , Cher Liang Cha , Teck Koon Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A method of forming trenches having different depths for use in shallow trench isolations is achieved. Dishing problems due to isolation oxide thinning over wide trenches is eliminated. A silicon substrate is provided. A pad oxide is grown. A polishing stop of silicon nitride is deposited. An oxide layer is grown overlying the silicon substrate. The oxide layer, polishing stop layer, and pad oxide layer are etched through to the silicon substrate to form openings for planned first trenches. A polysilicon layer is deposited overlying the oxide layer and filling the openings for the planned first trenches. The polysilicon layer is polished down to the top surface of the oxide layer such that the polysilicon layer remains only in the openings of the planned first trenches. The oxide layer, polishing stop layer, and pad oxide layer are etched through to the silicon substrate to form openings for planned second trenches. The silicon substrate and the polysilicon layer are simultaneously etched to complete the first trenches and the second trenches, with the second trenches deeper than the first trenches, and with the oxide layer a hard mask, and the integrated circuit device is completed.
摘要翻译：实现了在浅沟槽隔离中使用具有不同深度的沟槽的方法。消除了由于在宽沟槽上的隔离氧化物变薄导致的抛光问题。提供硅衬底。生长垫氧化物。沉积氮化硅的抛光停止。生长在硅衬底上的氧化物层。将氧化物层，抛光停止层和衬垫氧化物层蚀刻到硅衬底上，以形成用于计划的第一沟槽的开口。沉积覆盖氧化物层的多晶硅层并填充用于计划的第一沟槽的开口。多晶硅层被抛光到氧化物层的顶表面，使得多晶硅层仅保留在预定的第一沟槽的开口中。氧化物层，抛光停止层和焊盘氧化物层被蚀刻到硅衬底上以形成用于规划的第二沟槽的开口。同时蚀刻硅衬底和多晶硅层以完成第一沟槽和第二沟槽，其中第二沟槽比第一沟槽更深，并且氧化物层是硬掩模，并且集成电路器件完成。

55. 发明授权

US06177324B1 ESD protection device for STI deep submicron technology 有权
标题翻译：用于STI深亚微米技术的ESD保护器件
公开(公告)号：US06177324B1
公开(公告)日：2001-01-23
申请号：US09428568
申请日：1999-10-28
申请人： Jun Song , Shyue Fong Quek , Ting Cheong Ang , Lap Chan
发明人： Jun Song , Shyue Fong Quek , Ting Cheong Ang , Lap Chan
IPC分类号： H01L21336
CPC分类号： H01L29/66621 , H01L27/0266 , H01L29/0649 , H01L29/7834
摘要： A new method is provided for the creation of an ESD protection device for deep submicron semiconductor technology. An STI trench is created and filled with oxide. The surface of the STI region is polished after which a gate structure is created over the STI region. A high energy ESD implant is performed that is self-aligned with the created gate structure after which the EDS device structure is completed by implanting the source and drain regions of the ESD device.
摘要翻译：提供了一种用于创建深亚微米半导体技术的ESD保护器件的新方法。产生STI沟槽并填充氧化物。抛光STI区域的表面，之后在STI区域上形成栅极结构。执行高能量ESD注入，其与所产生的栅极结构自对准，之后通过注入ESD器件的源极和漏极区域来完成EDS器件结构。

56. 发明授权

US6150232A Formation of low k dielectric 有权
标题翻译：低k电介质的形成
公开(公告)号：US6150232A
公开(公告)日：2000-11-21
申请号：US244877
申请日：1999-02-05
申请人： Lap Chan , Cher Liang Cha , Kok Keng Ong , Kheng Chok Tee
发明人： Lap Chan , Cher Liang Cha , Kok Keng Ong , Kheng Chok Tee
IPC分类号： H01L21/312 , H01L21/316 , H01L21/768 , H01L21/76
CPC分类号： H01L21/7682 , H01L21/3124 , H01L21/31612
摘要： A method for creating low intra-level dielectric interface between conducting lines using conventional deposition and etching processes. A layer of conducting lines is formed interspersed with dielectric material. A dummy, high-density pattern of low k dielectric material is created on top of this layer. The dielectric material between the metal lines is removed. The dummy high-density pattern is interconnected, deposited on top of this interconnected layer is a low k dielectric to form an inter layer dielectric.
摘要翻译：一种使用常规沉积和蚀刻工艺在导线之间产生低内部电介质界面的方法。一层导电线形成为散布有电介质材料。在该层的顶部上形成低k电介质材料的虚拟高密度图案。去除金属线之间的电介质材料。虚拟高密度图案是互连的，沉积在该互连层的顶部上的是低k电介质以形成层间电介质。

57. 发明授权

US6136693A Method for planarized interconnect vias using electroless plating and CMP 失效
标题翻译：使用化学镀和CMP的平面化互连通孔的方法
公开(公告)号：US6136693A
公开(公告)日：2000-10-24
申请号：US958427
申请日：1997-10-27
申请人： Lap Chan , Hou Tee Ng
发明人： Lap Chan , Hou Tee Ng
IPC分类号： C23C14/58 , C23C16/56 , C23C18/30 , C23C18/40 , H01L21/768 , B05D5/12 , C23C14/32 , H01L21/4763
CPC分类号： C23C14/588 , C23C16/56 , C23C18/30 , C23C18/405 , H01L21/7684 , H01L21/76843 , H01L21/76865 , H01L21/76874 , H01L21/76879
摘要： An improved and new method for fabricating conducting vias between successive layers of conductive interconnection patterns in a semiconductor integrated circuit has been developed. The method utilizes a first CMP step to form a barrier lined contact hole, deposition of copper by electroless plating into the barrier lined contact hole, and a second CMP step to remove overgrowth of copper, thus producing coplanarity between the copper surface and the surrounding insulator surface.
摘要翻译：已经开发了用于在半导体集成电路中的导电互连图案的连续层之间制造导电通孔的改进和新的方法。该方法利用第一CMP步骤形成屏障衬里的接触孔，通过化学镀将铜沉积到屏障衬里接触孔中，以及第二CMP步骤以去除铜的过度生长，从而产生铜表面和周围绝缘体之间的共面性表面。

58. 发明授权

US6110787A Method for fabricating a MOS device 有权
标题翻译： MOS器件的制造方法
公开(公告)号：US6110787A
公开(公告)日：2000-08-29
申请号：US391886
申请日：1999-09-07
申请人： Lap Chan , Ting Cheong Ang , Shyue Pong Quek , Sang Yee Loong
发明人： Lap Chan , Ting Cheong Ang , Shyue Pong Quek , Sang Yee Loong
IPC分类号： H01L21/336 , H01L21/762 , H01L29/417 , H01L29/423
CPC分类号： H01L29/41775 , H01L21/76224 , H01L29/41783 , H01L29/6659 , H01L29/66628 , H01L29/78
摘要： A method of fabricating a MOS device having raised source/drain, raised isolation regions having isolation spacers, and a gate conductor having gate spacers is achieved. A layer of gate silicon oxide is grown over the surface of a semiconductor structure. A polysilicon layer is deposited overlying the gate silicon oxide layer. The polysilicon layer, gate silicon oxide layer and semiconductor structure are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised isolation regions. The remaining polysilicon layer is patterned to remove polysilicon adjacent the raised isolation regions forming a gate conductor between the raised isolation regions. The gate conductor and the raised isolation regions having exposed sidewalls. The gate oxide layer between the gate conductor and raised isolation regions is removed. Isolation spacers are formed on the exposed sidewalls of the raised isolation regions and gate spacers are formed on the exposed sidewalls of the gate conductor. A layer of silicon is deposited and patterned to form raised source and drain adjacent the gate spacers with source and drain being doped to form a MOS device.
摘要翻译：实现了具有升高的源极/漏极，具有隔离间隔物的升高的隔离区域以及具有栅极间隔物的栅极导体的MOS器件的制造方法。在半导体结构的表面上生长栅极氧化硅层。沉积覆盖栅氧化硅层的多晶硅层。对多晶硅层，栅极氧化硅层和半导体结构进行图案化和蚀刻以形成沟槽。沟槽用隔离材料填充至少甚至具有多晶硅层的顶表面的水平以形成凸起的隔离区域。将剩余的多晶硅层图案化以去除在凸起的隔离区域之间形成栅极导体的凸起的隔离区域附近的多晶硅。栅极导体和凸起的隔离区域具有暴露的侧壁。去除栅极导体与升高隔离区之间的栅极氧化层。在凸起的隔离区域的暴露的侧壁上形成绝缘间隔物，并且栅极间隔物形成在栅极导体的暴露的侧壁上。沉积一层硅并图案化以形成与栅极间隔物相邻的凸起源极和漏极，源极和漏极被掺杂以形成MOS器件。

59. 发明授权

US6100195A Passivation of copper interconnect surfaces with a passivating metal layer 有权
公开(公告)号：US6100195A
公开(公告)日：2000-08-08
申请号：US222275
申请日：1998-12-28
申请人： Lap Chan , Kuan Pei Yap , Kheng Chok Tee , Flora S. Ip , Wye Boon Loh
发明人： Lap Chan , Kuan Pei Yap , Kheng Chok Tee , Flora S. Ip , Wye Boon Loh
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76849 , H01L21/76858 , H01L21/76867 , H01L21/76886
摘要： An interconnect line on an IMD layer on a semiconductor device is formed in an interconnect hole in the IMD layer. The interconnect hole has walls and a bottom in the IMD layer. A diffusion barrier is formed on the walls and the bottom of the hole. Fill the interconnect hole with a copper metal line. Perform a CMP step to planarize the device and to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole. Alternatively, a blanket deposit of a copper metal line layer covers the diffusion layer and fills the interconnect hole with a copper metal line. Perform a CMP process to planarize the device to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole in a self-aligned deposition process.

60. 发明授权

US5893787A Application of fast etching glass for FED manufacturing 失效
标题翻译：快速蚀刻玻璃在FED制造中的应用
公开(公告)号：US5893787A
公开(公告)日：1999-04-13
申请号：US805877
申请日：1997-03-03
申请人： Lap Chan , Simon Chooi
发明人： Lap Chan , Simon Chooi
IPC分类号： H01J9/02
CPC分类号： H01J9/025
摘要： The microtip housing cavity in a cold cathode display was formed by selecting for the dielectric layer surrounding it a material whose etch rate (for the same etchant) was 3 to 20 times faster than the etch rate of the gate layer. Specifically, a gaseous etchant that included CHF.sub.3, CH.sub.4, CO, or CO and C.sub.4 F.sub.8 was used to form the cavity in a layer consisting of silicon oxide containing between about 3 and 10 weight % boron and between about 3 and 10 weight % phosphorus, deposited by chemical vapor deposition at pressures somewhat less than atmospheric (commonly referred to as SABPSG or sub-atmospheric boro-phosphosilicate glass). The gate layer consisted of phosphorus-doped polysilicon. Using this combination, once the gate opening had been etched, etching of the cavity proceeded very rapidly with little increase in the width of the gate opening. Thus the cavity was formed in a single mask, single etchant process.
摘要翻译：冷阴极显示器中的微尖端壳体腔通过选择围绕其的介电层形成，其蚀刻速率（相同蚀刻剂）的蚀刻速率比栅极层的蚀刻速率快3至20倍。具体地，使用包括CHF 3，CH 4，CO或CO和C 4 F 8的气体蚀刻剂在由含有约3至10重量％硼和约3至10重量％磷之间的氧化硅组成的层中形成空腔，通过化学气相沉积在小于大气压（通常称为SABPSG或次大气硼硅磷酸盐玻璃）的压力下沉积。栅极层由磷掺杂多晶硅组成。使用这种组合，一旦栅极开口被蚀刻，腔的蚀刻就非常迅速地进行，门开口的宽度几乎没有增加。因此，腔形成在单个掩模中，单一蚀刻过程。

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