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51. 发明授权

US06556303B1 Scattered signal collection using strobed technique 有权
标题翻译：使用频闪技术分散信号采集
公开(公告)号：US06556303B1
公开(公告)日：2003-04-29
申请号：US09902366
申请日：2001-07-10
申请人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Khoi A. Phan
发明人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Khoi A. Phan
IPC分类号： G01B1114
CPC分类号： G01B11/0683 , G01B11/0625 , H01L22/12
摘要： The present invention is directed to a system and a method for controlling a thin film formation on a moving substrate as part of a process for manufacturing an integrated circuit. The invention involves the use of scatterometry to control the thin film formation process by analyzing the thin film on the moving substrate in a periodic manner. A registration feature associated with the moving substrate can be utilized in conjunction with a signaling system to determine a position of the moving substrate, whereby a repeatable analysis of a corresponding location on the moving substrate can be performed. Scatterometry permits in-situ measurements of thin film formation progress, whereby thin film formation process conditions can be controlled in a feedback loop to obtain a targeted result. Scatterometry can also be facilitated by providing a grating pattern on a non-production portion of the substrate.
摘要翻译：本发明涉及一种用于控制移动衬底上的薄膜形成的系统和方法，作为用于制造集成电路的工艺的一部分。本发明涉及使用散射法来以周期性方式分析移动基片上的薄膜来控制薄膜形成过程。与移动基板相关联的配准特征可以与信号系统结合使用，以确定移动基板的位置，由此可以执行移动基板上对应位置的可重复分析。散射测量允许原位测量薄膜形成进程，由此可以在反馈回路中控制薄膜形成工艺条件以获得目标结果。也可以通过在基板的非生产部分上提供光栅图案来促进散射测量。

52. 发明授权

US07159205B1 Use of non-lithographic shrink techniques for fabrication/making of imprints masks 失效
标题翻译：使用非光刻收缩技术制造/制作印记掩模
公开(公告)号：US07159205B1
公开(公告)日：2007-01-02
申请号：US10838830
申请日：2004-05-04
申请人： Gilles Amblard , Bhanwar Singh , Khoi A. Phan
发明人： Gilles Amblard , Bhanwar Singh , Khoi A. Phan
IPC分类号： G06F17/50
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , G03F7/40
摘要： The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate improved critical dimension (CD) control and the reduction of line-edge roughness (LER) during pattern line formation in an imprint mask. One aspect of the invention provides for forming features having CDs that are larger than ultimately desired in a mask resist. Upon application of a non-lithographic shrink technique, LER is mitigated and CD is reduced to within a desired target tolerance.
摘要翻译：本发明一般涉及光刻系统和方法，更具体地涉及在压印掩模中在图案线形成期间促进改进的临界尺寸（CD）控制和减少线边缘粗糙度（LER）的系统和方法。本发明的一个方面提供了形成具有大于掩模抗蚀剂中最终期望的CD的特征。在施加非光刻收缩技术时，LER被减轻并且CD被减小到期望的目标公差内。

53. 发明授权

US07148142B1 System and method for imprint lithography to facilitate dual damascene integration in a single imprint act 有权
标题翻译：用于压印光刻的系统和方法，以便于在单一印记法中双重镶嵌一体化
公开(公告)号：US07148142B1
公开(公告)日：2006-12-12
申请号：US10874500
申请日：2004-06-23
申请人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Khoi A. Phan
发明人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Khoi A. Phan
IPC分类号： H01L21/44
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , H01L21/76807 , H01L21/76817 , H01L2221/1021
摘要： A system and method are provided to facilitate dual damascene interconnect integration in a single imprint step. The method provides for creation of a translucent imprint mold with three-dimensional features comprising the dual damascene pattern to be imprinted. The imprint mold is brought into contact with a photopolymerizable organosilicon imaging layer deposited upon a transfer layer which is spin coated or otherwise deposited upon a dielectric layer of a substrate. When the photopolymerizable layer is exposed to a source of illumination, it cures with a structure matching the dual damascene pattern of the imprint mold. A halogen breakthrough etch followed by oxygen transfer etch transfer the vias from the imaging layer into the transfer layer. A second halogen breakthrough etch followed by a second oxygen transfer etch transfer the trenches from the imaging layer into the transfer layer. A dielectric etch transfers the pattern from the transfer layer into the dielectric layer. A metal fill process then fills the dual damascene openings of the dielectric layer with metal.
摘要翻译：提供了一种系统和方法，以便在单个压印步骤中促进双镶嵌互连集成。该方法提供了具有三维特征的半透明压印模具的创建，该三维特征包括要印刷的双镶嵌图案。压印模具与沉积在转移层上的可光聚合的有机硅成像层接触，转移层被旋涂或以其它方式沉积在基底的电介质层上。当可光聚合层暴露于照明源时，它可以用匹配印模的双镶嵌图案的结构固化。卤素穿透蚀刻随后氧传递蚀刻将通孔从成像层转移到转移层中。第二个卤素穿透蚀刻，随后是第二次氧转移蚀刻，将沟槽从成像层转移到转移层中。电介质蚀刻将图案从转印层转移到电介质层中。然后，金属填充过程用金属填充介电层的双镶嵌开口。

54. 发明授权

US06486072B1 System and method to facilitate removal of defects from a substrate 失效
标题翻译：有助于从基底去除缺陷的系统和方法
公开(公告)号：US06486072B1
公开(公告)日：2002-11-26
申请号：US09709974
申请日：2000-11-10
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： H01L21302
CPC分类号： H01L21/02046
摘要： A system and method are disclosed for facilitating removal of a defect from a substrate. A charge is applied at the surface of substrate, such as in the form of an ionized gas, to weaken attractive forces between the defect and the substrate. As a result of weakening the attractive forces, a suitable defect removal system may be employed to remove the defect.
摘要翻译：公开了一种用于便于从基底去除缺陷的系统和方法。在基板的表面，例如以电离气体的形式施加电荷，以减弱缺陷和基板之间的吸引力。作为吸引力减弱的结果，可以采用合适的缺陷去除系统来去除缺陷。

55. 发明授权

US06171737B2 Low cost application of oxide test wafer for defect monitor in photolithography process 失效
标题翻译：用于光刻工艺中缺陷监测器的氧化物测试晶片的低成本应用
公开(公告)号：US06171737B2
公开(公告)日：2001-01-09
申请号：US09017695
申请日：1998-02-03
申请人： Khoi A. Phan , Shobhana R. Punjabi , Robert J. Chiu , Bhanwar Singh
发明人： Khoi A. Phan , Shobhana R. Punjabi , Robert J. Chiu , Bhanwar Singh
IPC分类号： G03F900
CPC分类号： G03F7/7065 , H01L22/20 , H01L22/34
摘要： A low cost technique for detecting defects in photolithography processes in a submicron integrated circuit manufacturing environment combines use of a reusable test wafer with in-line processing to monitor defects using a pattern comparator system. A reusable test wafer having an oxide layer overlying a silicon substrate and having a thickness corresponding to a minimum reflectance for an exposure wavelength used for photolithography is patterned using a prescribed photolithographic fabrication process to form a repetitive pattern according to a prescribed design product rule. The pattern is formed using a reticle having a repetitive pattern array with a similar design rule as the product to be developed by the lithography processes. The patterned test wafer is then inspected using image-based inspection techniques, where the image has high resolution pixels of preferably 0.25 microns per pixel. An optical review station and scanning electron microscope system are used to review defect and classify defect types. The test wafer can then be reused by cleaning the photolithographic pattern by removing the photoresist, and then removing polymer particles adhering to the oxide layer following removal of the photoresist.
摘要翻译：在亚微米集成电路制造环境中用于检测光刻工艺中的缺陷的低成本技术将使用可重复使用的测试晶片与在线处理相结合，以使用模式比较器系统来监测缺陷。使用规定的光刻制造工艺对具有覆盖在硅衬底上并具有与用于光刻的曝光波长的最小反射率相对应的厚度的可重复使用的测试晶片图案化以根据规定的设计产品规则形成重复图案。使用具有与通过光刻工艺开发的产品相似的设计规则的具有重复图案阵列的掩模版形成图案。然后使用基于图像的检查技术来检查图案化的测试晶片，其中图像具有每像素优选0.25微米的高分辨率像素。光学检查站和扫描电子显微镜系统用于检查缺陷并分类缺陷类型。然后可以通过除去光致抗蚀剂来清洁光刻图案，然后在去除光致抗蚀剂之后去除粘附到氧化物层上的聚合物颗粒，来重新使用测试晶片。

56. 发明授权

US07065737B2 Multi-layer overlay measurement and correction technique for IC manufacturing 失效
标题翻译：用于IC制造的多层覆盖测量和校正技术
公开(公告)号：US07065737B2
公开(公告)日：2006-06-20
申请号：US10790296
申请日：2004-03-01
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： G06F17/50 , G03F9/00 , G03C5/00
CPC分类号： G03F7/70633 , G01N21/95607 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system facilitating measurement and correction of overlay between multiple layers of a wafer is disclosed. The system comprises an overlay target that represents overlay between three or more layers of a wafer and a measurement component that determines overlay error existent in the overlay target, thereby determining overlay error between the three or more layers of the wafer. A control component can be provided to correct overlay error between adjacent and non-adjacent layers, wherein the correction is based at least in part on measurements obtained by the measurement component.
摘要翻译：公开了一种便于测量和校正晶片多层之间覆盖层的系统。该系统包括覆盖在三层或多层晶片之间的重叠目标，以及确定覆盖目标中存在的重叠误差的测量部件，从而确定晶片的三层或更多层之间的重叠误差。可以提供控制部件来校正相邻层和非相邻层之间的覆盖误差，其中校正至少部分地基于由测量部件获得的测量。

57. 发明授权

US08028531B2 Mitigating heat in an integrated circuit 有权
标题翻译：减轻集成电路中的热量
公开(公告)号：US08028531B2
公开(公告)日：2011-10-04
申请号：US12537135
申请日：2009-08-06
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： F25B21/02
CPC分类号： H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides for a system and method for regulating and monitoring heat dissipation of an integrated circuit by employing a heat regulating device with a thermal structure net work assembly. Each thermal structure can act as a heat conducting pathway for inducing heat into and/or dissipating heat away from the integrated circuit, thus creating a more uniform temperature gradient across the semiconductor body.
摘要翻译：本发明提供一种通过采用具有热结构网工作组件的热调节装置来调节和监测集成电路的散热的系统和方法。每个热结构可以用作导热通道，用于将热量从集成电路引入和/或散热，从而在半导体主体上产生更均匀的温度梯度。

58. 发明申请

US20090288425A1 HEAT REGULATING DEVICE FOR AN INTEGRATED CIRCUIT 有权
标题翻译：用于集成电路的热调节装置
公开(公告)号：US20090288425A1
公开(公告)日：2009-11-26
申请号：US12537135
申请日：2009-08-06
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： F25B21/02 , G05D23/00
CPC分类号： H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides for a system and method for regulating and monitoring heat dissipation of an integrated circuit by employing a heat regulating device with a thermal structure net work assembly. Each thermal structure can act as a heat conducting pathway for inducing heat into and/or dissipating heat away from the integrated circuit, thus creating a more uniform temperature gradient across the semiconductor body.
摘要翻译：本发明提供一种通过采用具有热结构网工作组件的热调节装置来调节和监测集成电路的散热的系统和方法。每个热结构可以用作导热通道，用于将热量从集成电路引入和/或散热，从而在半导体主体上产生更均匀的温度梯度。

59. 发明授权

US07056646B1 Use of base developers as immersion lithography fluid 有权
标题翻译：使用基底显影剂作为浸没光刻液
公开(公告)号：US07056646B1
公开(公告)日：2006-06-06
申请号：US10676749
申请日：2003-10-01
申请人： Gilles Amblard , Bhanwar Singh , Khoi A. Phan
发明人： Gilles Amblard , Bhanwar Singh , Khoi A. Phan
IPC分类号： G03F7/20
CPC分类号： G03F7/2041 , G03F7/322 , G03F7/70341
摘要： Disclosed are immersion lithography methods involving using a base developer as an immersion lithography fluid. Consequently, it is unnecessary to contact a developer with an irradiated resist after the immersion lithography fluid is removed.
摘要翻译：公开了涉及使用基底显影剂作为浸没光刻流体的浸没式光刻方法。因此，在浸没光刻液被去除之后，不需要将曝光的抗蚀剂接触显影剂。

60. 发明授权

US06924157B1 Real time particle monitor inside of plasma chamber during resist strip processing 失效
标题翻译：抗蚀带处理过程中等离子体室内实时粒子监测
公开(公告)号：US06924157B1
公开(公告)日：2005-08-02
申请号：US10277003
申请日：2002-10-21
申请人： Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan
发明人： Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan
IPC分类号： H01L21/00
CPC分类号： H01L21/67288 , H01J2237/0225 , H01J2237/3342
摘要： One aspect of the present invention relates to a system and method for controlling defect formation during a resist strip process. The system includes a reaction chamber comprising a patterned resist layer overlying a semiconductor structure wherein the resist layer is being exposed to a plasma material flowing into the chamber in order to facilitate removing the resist layer from the structure, a plasma-resist particle monitoring system connected to the reaction chamber and programmed to determine a particle count in the reaction chamber during the resist strip process, and a reaction controller coupled to the chamber and to the monitoring system, the reaction controller being programmed to receive particle data from the monitoring system to facilitate determining whether the counted particles in the chamber are within a tolerable limit. The method involves continuing to expose the structure and the chamber to the plasma until an acceptable particle count is obtained.
摘要翻译：本发明的一个方面涉及一种用于在抗蚀剂剥离过程中控制缺陷形成的系统和方法。该系统包括反应室，其包括覆盖半导体结构的图案化抗蚀剂层，其中抗蚀剂层暴露于流入室中的等离子体材料，以便于从结构去除抗蚀剂层;连接的等离子体抗蚀剂颗粒监测系统并且被编程为在抗蚀剂剥离过程期间确定反应室中的颗粒计数，以及耦合到室和反应控制器的反应控制器，反应控制器被编程为从监测系统接收颗粒数据以促进确定室中的计数颗粒是否在可容忍的极限内。该方法包括继续将结构和室暴露于等离子体，直到获得可接受的颗粒数。

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