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51. 发明申请

US20100001260A1 SELF-ALIGNED NANOTUBE FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING SAME 有权
标题翻译：自对准纳米管场效应晶体管及其制备方法
公开(公告)号：US20100001260A1
公开(公告)日：2010-01-07
申请号：US12544436
申请日：2009-08-20
申请人： Joerg Appenzeller , Phaedon Avouris , Kevin K. Chan , Philip G. Collins , Richard Martel , Hon-Sum Philip Wong
发明人： Joerg Appenzeller , Phaedon Avouris , Kevin K. Chan , Philip G. Collins , Richard Martel , Hon-Sum Philip Wong
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L51/0516 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L51/0048 , H01L51/0052 , H01L51/0545 , Y10S977/842 , Y10S977/938 , Y10S977/94
摘要： A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.
摘要翻译：自对准碳纳米管场效应晶体管半导体器件分别包括沉积在基板上的碳纳米管，分别形成在碳纳米管的第一端和第二端的源极和漏极，以及基本上形成的栅极碳纳米管的一部分，通过电介质膜与碳纳米管分离。

52. 发明授权

US07485518B2 Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) 失效
标题翻译：拉伸应变SiGe绝缘体上的应变Si MOSFET（SGOI）
公开(公告)号：US07485518B2
公开(公告)日：2009-02-03
申请号：US11684855
申请日：2007-03-12
申请人： Kevin K. Chan , Jack Q Chan , Kern Rim , Leathen Shi
发明人： Kevin K. Chan , Jack Q Chan , Kern Rim , Leathen Shi
IPC分类号： H01L21/336
CPC分类号： H01L29/78687 , H01L21/2007 , H01L29/1054 , H01L29/517 , H01L29/66742 , H01L29/7833 , H01L29/7842 , H01L29/78603
摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.
摘要翻译：提供了用作形成高性能金属氧化物半导体场效应晶体管（MOSFET）器件的模板的半导体结构。更具体地，本发明提供一种包括绝缘体上硅衬底的结构，其包括位于绝缘层顶部的拉伸应变SiGe合金层; 以及拉伸应变SiGe合金层顶部的应变Si层。本发明还提供了形成拉伸应变SGOI基板以及上述异质结构的方法。本发明的方法通过在绝缘层上直接提供拉伸应变SiGe合金层来分离应变Si层中的高应变和下层中的Ge含量的偏好。

53. 发明申请

US20080268600A1 MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS 有权
标题翻译：具有多个自对准硅化物接触的MOSFET结构
公开(公告)号：US20080268600A1
公开(公告)日：2008-10-30
申请号：US12131973
申请日：2008-06-03
申请人： Kevin K. Chan , Christian Lavoie , Kern Rim
发明人： Kevin K. Chan , Christian Lavoie , Kern Rim
IPC分类号： H01L21/336
CPC分类号： H01L29/66507 , H01L29/6653 , H01L29/7833
摘要： A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide.
摘要翻译：提供了包括多个不同的自对准硅化物触点的金属氧化物半导体场效应晶体管（MOSFET）结构及其制造方法。 MOSFET结构包括至少一个金属氧化物半导体场效应晶体管，其具有包括位于含Si衬底的表面上的栅极边缘的栅极导体; 第一内部硅化物，其具有基本上与所述至少一个金属氧化物半导体场效应晶体管的栅极边缘对准的边缘; 以及位于第一内部硅化物附近的第二外部硅化物。根据本发明，第二外部硅化物的第二厚度大于第一内部硅化物的第一厚度。此外，第二外部硅化物的电阻率低于第一内部硅化物的电阻率。

54. 发明授权

US07253065B2 Self-aligned nanotube field effect transistor and method of fabricating same 有权
标题翻译：自对准纳米管场效应晶体管及其制造方法
公开(公告)号：US07253065B2
公开(公告)日：2007-08-07
申请号：US10956851
申请日：2004-10-01
申请人： Joerg Appenzeller , Phaedon Avouris , Kevin K. Chan , Philip G. Collins , Richard Martel , Hon-Sum Philip Wong
发明人： Joerg Appenzeller , Phaedon Avouris , Kevin K. Chan , Philip G. Collins , Richard Martel , Hon-Sum Philip Wong
IPC分类号： H01L21/336 , H01L21/76 , H01L21/31 , H01L21/469
CPC分类号： H01L51/0516 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L51/0048 , H01L51/0052 , H01L51/0545 , Y10S977/842 , Y10S977/938 , Y10S977/94
摘要： A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.
摘要翻译：自对准碳纳米管场效应晶体管半导体器件分别包括沉积在基板上的碳纳米管，分别形成在碳纳米管的第一端和第二端的源极和漏极，以及基本上形成的栅极碳纳米管的一部分，通过电介质膜与碳纳米管分离。

55. 发明授权

US07253034B2 Dual SIMOX hybrid orientation technology (HOT) substrates 失效
标题翻译：双SIMOX混合取向技术（HOT）底物
公开(公告)号：US07253034B2
公开(公告)日：2007-08-07
申请号：US10902557
申请日：2004-07-29
申请人： Kevin K. Chan , Joel P. de Souza , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger
发明人： Kevin K. Chan , Joel P. de Souza , Alexander Reznicek , Devendra K. Sadana , Katherine L. Saenger
IPC分类号： H01L21/70 , H01L21/762
CPC分类号： H01L21/84 , H01L21/76243 , H01L21/76267 , H01L27/1203 , H01L27/1207
摘要： This invention provides a separation by implanted oxygen (SIMOX) method for forming planar hybrid orientation semiconductor-on-insulator (SOI) substrates having different crystal orientations, thereby making it possible for devices to be fabricated on crystal orientations providing optimal performance. The method includes the steps of selecting a substrate having a base semiconductor layer having a first crystallographic orientation separated by a thin insulating layer from a top semiconductor layer having a second crystallographic orientation; replacing the top semiconductor layer in selected regions with an epitaxially grown semiconductor having the first crystallographic orientation; then using an ion implantation and annealing method to (i) form a buried insulating region within the epitaxially grown semiconductor material, and (ii) thicken the insulating layer underlying the top semiconductor layer, thereby forming a hybrid orientation substrate in which the two semiconductor materials with different crystallographic orientations have substantially the same thickness and are both disposed on a common buried insulator layer. In a variation of this method, an ion implantation and annealing method is instead used to extend an auxiliary buried insulator layer (initially underlying the base semiconductor layer) upwards (i) into the epitaxially grown semiconductor, and (ii) up to the insulating layer underlying the top semiconductor layer.
摘要翻译：本发明提供了通过注入氧（SIMOX）分离方法，用于形成具有不同晶体取向的平面杂化取向绝缘体上半导体（SOI）衬底，从而使得可以以提供最佳性能的晶体取向来制造器件。该方法包括以下步骤：从具有第二晶体取向的顶部半导体层选择具有由薄绝缘层分离的第一晶体取向的基底半导体层的衬底; 用具有第一晶体取向的外延生长的半导体代替选定区域中的顶部半导体层; 然后使用离子注入和退火方法来（i）在外延生长的半导体材料内形成掩埋绝缘区，并且（ii）加厚顶部半导体层下面的绝缘层，从而形成混合取向衬底，其中两个半导体材料具有不同的晶体取向具有基本上相同的厚度并且均设置在公共掩埋绝缘体层上。在该方法的变型中，替代地使用离子注入和退火方法将辅助掩埋绝缘体层（最初在基底半导体层下面）向上（i）延伸到外延生长的半导体中，以及（ii）直到绝缘层在顶部半导体层下面。

56. 发明授权

US07145212B2 Method for manufacturing device substrate with metal back-gate and structure formed thereby 有权
公开(公告)号：US07145212B2
公开(公告)日：2006-12-05
申请号：US10868791
申请日：2004-06-17
申请人： Kevin K. Chan , Lijuan Huang , Fenton R. McFeely , Paul M. Solomon , Hon-Sum Philip Wong
发明人： Kevin K. Chan , Lijuan Huang , Fenton R. McFeely , Paul M. Solomon , Hon-Sum Philip Wong
IPC分类号： H01L29/76
CPC分类号： H01L29/66772 , H01L21/76251 , H01L29/78648
摘要： A method (and resultant structure) of forming a semiconductor device, includes forming a metal-back-gate over a substrate and a metal back-gate, forming a passivation layer on the metal back-gate to prevent the metal back-gate from reacting with radical species, and providing an intermediate gluing layer between the substrate and the metal back-gate to enhance adhesion.

57. 发明授权

US07078773B2 Nitride-encapsulated FET (NNCFET) 失效
标题翻译：氮化物封装的FET（NNCFET）
公开(公告)号：US07078773B2
公开(公告)日：2006-07-18
申请号：US10328258
申请日：2002-12-23
申请人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
发明人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.
摘要翻译：提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。在本发明中，提供自对准隔离区以减小DGFET结构中的寄生电容。此外，本发明封装了含硅沟道层，使背栅能够被更大程度地氧化，从而进一步降低结构的寄生电容。

58. 发明授权

US06893948B2 Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size 失效
标题翻译：通过沉积不同晶粒尺寸的多晶硅来减少多晶硅栅电极中的多晶硅耗尽的方法
公开(公告)号：US06893948B2
公开(公告)日：2005-05-17
申请号：US10616962
申请日：2003-07-11
申请人： Arne W. Ballantine , Kevin K. Chan , Jeffrey D. Gilbert , Kevin M. Houlihan , Glen L. Miles , James J. Quinlivan , Samuel C. Ramac , Michael B. Rice , Beth A. Ward
发明人： Arne W. Ballantine , Kevin K. Chan , Jeffrey D. Gilbert , Kevin M. Houlihan , Glen L. Miles , James J. Quinlivan , Samuel C. Ramac , Michael B. Rice , Beth A. Ward
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L21/20 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28035 , H01L29/4925 , H01L29/665
摘要： Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.
摘要翻译：通过在受控条件下沉积多晶硅来减少多晶硅栅电极中的多晶硅电耗，从而通过多晶硅的厚度来改变晶粒尺寸。所得到的结构可以具有两个或更多个相应晶粒尺寸的深度连续的区域，并且晶粒尺寸的选择被引导以最大限度地使栅极电介质附近的多晶硅中的掺杂剂活化最大化，并且将多晶硅的电阻定制在第一区域并且远离栅极电介质。该方法和所得结构有利地用于形成FET和掺杂多晶硅电阻器。

59. 发明授权

US06891227B2 Self-aligned nanotube field effect transistor and method of fabricating same 有权
公开(公告)号：US06891227B2
公开(公告)日：2005-05-10
申请号：US10102365
申请日：2002-03-20
申请人： Joerg Appenzeller , Phaedon Avouris , Kevin K. Chan , Richard Martel , Hon-Sum Philip Wong , Philip G. Collins
发明人： Joerg Appenzeller , Phaedon Avouris , Kevin K. Chan , Richard Martel , Hon-Sum Philip Wong , Philip G. Collins
IPC分类号： H01L51/00 , H01L51/05 , H01L51/30 , H01L29/76 , H01L29/06 , H01L29/94
CPC分类号： H01L51/0516 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L51/0048 , H01L51/0052 , H01L51/0545 , Y10S977/842 , Y10S977/938 , Y10S977/94
摘要： A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

60. 发明授权

US06444578B1 Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices 有权
标题翻译：用于减少浅结和薄SOI电子器件中Si消耗的自对准硅化物工艺
公开(公告)号：US06444578B1
公开(公告)日：2002-09-03
申请号：US09791024
申请日：2001-02-21
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin K. Chan , Guy M. Cohen , Kathryn Wilder Guarini , James M. Harper , Christian Lavoie , Paul M. Solomon
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin K. Chan , Guy M. Cohen , Kathryn Wilder Guarini , James M. Harper , Christian Lavoie , Paul M. Solomon
IPC分类号： H01L2144
CPC分类号： H01L21/28518
摘要： The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a M—Si or M—Si—Ge alloy, where M is Co, Ni or CoNi and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.
摘要翻译：本发明涉及在采用M-Si或M-Si-Ge合金的自对准硅化物工艺中降低Si消耗的方法，其中M是Co，Ni或CoNi以及Si的覆盖层。本发明特别可用于最大限度地减少浅结和薄绝缘体上硅（SOI）电子器件中的Si消耗。

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