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51. 发明授权

US07305515B2 Performance optimizing compiler for building a compiled DRAM 失效
标题翻译：用于构建编译的DRAM的性能优化编译器
公开(公告)号：US07305515B2
公开(公告)日：2007-12-04
申请号：US09793037
申请日：2001-02-26
申请人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
发明人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F17/5045
摘要： A compiler is provided for compiling at least one array or bank unit of a DRAM macro such that electrical performance, including cycle time, access time, setup time, among other properties, is optimized. The compiler compiles the DRAM macro according to inputted information. The compiler receives an input capacity and configuration for the DRAM macro. A compiler algorithm determines a number of wordlines and bitlines required to create the DRAM macro of the input capacity. The compiler algorithm optimizes the cycle time and access time of the DRAM macro by properly configuring a support unit of the DRAM macro based upon the number of wordlines and bitlines.
摘要翻译：提供了一种用于编译DRAM宏的至少一个阵列或存储体单元的编译器，使得包括循环时间，访问时间，建立时间在内的电性能以及其他特性被优化。编译器根据输入的信息编译DRAM宏。编译器接收DRAM宏的输入容量和配置。编译器算法确定创建输入容量的DRAM宏所需的字数和位线数。编译器算法通过根据字线和位线的数量正确配置DRAM宏的支持单元来优化DRAM宏的周期时间和访问时间。

52. 发明授权

US07268577B2 Changing chip function based on fuse states 有权
标题翻译：基于保险丝状态改变芯片功能
公开(公告)号：US07268577B2
公开(公告)日：2007-09-11
申请号：US11016220
申请日：2004-12-17
申请人： Karl R. Erickson , John A. Fifield , Chandrasekharan Kothandaraman , Phil C. Paone , William R. Tonti
发明人： Karl R. Erickson , John A. Fifield , Chandrasekharan Kothandaraman , Phil C. Paone , William R. Tonti
IPC分类号： H03K19/00
CPC分类号： G06F21/71
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fuses (eFUSES).
摘要翻译：提供了在设备已经离开制造商的控制之后可以控制电子设备的特定特征的操作和/或访问的技术和系统。操作和/或访问可以基于存储在诸如电可编程熔丝（eFUSES）的非易失性存储元件中的值来提供。

53. 外观设计

USD538448S1 Roof tile 有权
公开(公告)号：USD538448S1
公开(公告)日：2007-03-13
申请号：US29231965
申请日：2005-06-13
申请人： John A. Fifield , William R. Powel
设计人： John A. Fifield , William R. Powel

54. 发明授权

US06917319B1 Digital to analog converter using tunneling current element 失效
标题翻译：使用隧道电流元件的数模转换器
公开(公告)号：US06917319B1
公开(公告)日：2005-07-12
申请号：US10708877
申请日：2004-03-30
申请人： Wagdi W. Abadeer , John A. Fifield
发明人： Wagdi W. Abadeer , John A. Fifield
IPC分类号： H03M1/76 , H03M1/00 , H03M1/66
CPC分类号： H03M1/76
摘要： A method and structure for a digital-to-analog converter comprising a voltage source supply; a voltage division stack connected to the voltage source supply; a multiplexer connected to the voltage division stack; a digital circuit connected to the multiplexer; an analog circuit connected to the multiplexer; and an input binary word source connected to the digital circuit, wherein outputs of the digital circuit are input into the analog circuit and converted as analog output. According to the invention, the multiplexer comprises any of an NFET and/or a PFET. The digital-to-analog converter further comprises a capacitor connected to the analog circuit and a binary-weighted tunneling current device connected to the digital circuit. The multiplexer and the capacitor are made of thick oxide (at least 5 nm thick). The tunneling current device outputs tunneling current, wherein the tunneling current is adjusted in proportion to a binary weight of the input binary word source.
摘要翻译：一种用于数模转换器的方法和结构，包括电压源电源; 连接到电压源电源的分压堆; 连接到电压分组的多路复用器; 连接到多路复用器的数字电路; 连接到多路复用器的模拟电路; 以及连接到数字电路的输入二进制字源，其中数字电路的输出被输入到模拟电路中并转换为模拟输出。根据本发明，多路复用器包括NFET和/或PFET中的任一个。数模转换器还包括连接到模拟电路的电容器和连接到数字电路的二进制加权隧道电流器件。多路复用器和电容器由厚氧化物（至少5nm厚）制成。隧道电流装置输出隧道电流，其中隧道电流与输入二进制字源的二进制权重成比例地调整。

55. 发明授权

US06879638B1 Method and apparatus for providing communication between electronic devices 失效
标题翻译：用于在电子设备之间提供通信的方法和装置
公开(公告)号：US06879638B1
公开(公告)日：2005-04-12
申请号：US09473935
申请日：1999-12-28
申请人： Claude L. Bertin , Anthony R. Bonaccio , John A. Fifield , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , John A. Fifield , Wilbur D. Pricer , William R. Tonti
IPC分类号： H04L25/49 , H04L27/10
CPC分类号： H04L25/4906 , H04L25/4902
摘要： A method and system for providing communication between electronic devices that uses the phase of data transmitted between the devices to indicate logical one and zero values. The method and system has the added benefit of relieving the traditional limitations of voltage communication restraints between devices having differing core voltages (i.e. Differing generations).
摘要翻译：一种用于在电子设备之间提供通信的方法和系统，其使用在设备之间传输的数据的相位来指示逻辑1和零值。该方法和系统具有减轻在具有不同核心电压的器件（即不同代）之间的电压通信约束的传统限制的附加益处。

56. 发明授权

US06577154B2 Constant impedance driver for high speed interface 有权
标题翻译：用于高速接口的恒定阻抗驱动器
公开(公告)号：US06577154B2
公开(公告)日：2003-06-10
申请号：US09848454
申请日：2001-05-03
申请人： John A. Fifield , Russell J. Houghton
发明人： John A. Fifield , Russell J. Houghton
IPC分类号： H03K1716
CPC分类号： H04L25/028 , H03K19/00384 , H04L25/0278
摘要： A compensated driver for maintaining constant impedance during data transfer from an integrated circuit comprises an output portion having an output device to transfer data from the integrated circuit and a mimic circuit portion having a sample output device scaled to a fraction of the output device adapted to accept a reference current and generate a sample voltage. A mimic circuit portion has a sample output device scaled to a fraction of the output device adapted to accept a reference current and generate a sample voltage. A differential amplifier portion is adapted to generate a control voltage in response to a reference voltage and the sample voltage. A predrive portion applies either a ground or the predetermined control voltage from the differential amplifier portion to the output stage portion in response to an input, the control voltage regulating the output device in the output stage portion to achieve a more constant impedance.
摘要翻译：用于在从集成电路进行数据传输期间保持恒定阻抗的补偿驱动器包括具有输出装置以从集成电路传送数据的输出部分和具有缩放到适于接受的输出装置的一部分的样本输出装置的模拟电路部分参考电流并产生采样电压。模拟电路部分具有缩放到适于接受参考电流并且产生采样电压的输出设备的一部分的采样输出设备。差分放大器部分适于响应于参考电压和采样电压而产生控制电压。预驱动部分响应于输入将来自差分放大器部分的接地或预定控制电压施加到输出级部分，控制电压调节输出级部分中的输出器件以实现更恒定的阻抗。

57. 发明授权

US06552944B2 Single bitline direct sensing architecture for high speed memory device 有权
标题翻译：用于高速存储器件的单位线直接感测架构
公开(公告)号：US06552944B2
公开(公告)日：2003-04-22
申请号：US09870755
申请日：2001-05-31
申请人： John A. Fifield , Toshiaki Kirihata , Wing K. Luk , Jeremy K. Stephens , Daniel W. Storaska
发明人： John A. Fifield , Toshiaki Kirihata , Wing K. Luk , Jeremy K. Stephens , Daniel W. Storaska
IPC分类号： G11C702
CPC分类号： G11C7/067 , G11C7/062 , G11C11/4091
摘要： A single bitline direct sensing architecture employs a 4 transistor sense amplifier circuit located in each memory array, wherein the transistors function to selectively transfer data bits from either a true bitline or a complement bitline of the bitline pair to a data line. The data line is preferably arranged over a plurality of memory arrays. The data line may or may not be shared for the read and write operations. One current source is additionally used to precharge the datalines in a read mode, performing the function of a digital sensing scheme by detecting a resistance ratio between the current source and the transistor driven by the bitline for the corresponding array. A simple inverter may be used for detecting a level of the data line determined by the resistance ratio. The bitline pair is sensed in a single ended fashion, eliminating the need for a cross-coupled pair of CMOS devices, and thus reducing the required layout area. By accessing the bitline pair individually, two sets of control signals for the pre-charge, EQ0, EQ1, are developed to allow for bitline shielding in the array.
摘要翻译：单个位线直接感测架构采用位于每个存储器阵列中的4晶体管读出放大器电路，其中晶体管用于选择性地将数据位从位线对的真位置或补码位线传送到数据线。数据线优选地布置在多个存储器阵列上。读取和写入操作可能共享或不共享数据行。一个电流源另外用于在读取模式下对数据进行预充电，通过检测电流源和由相应阵列的位线驱动的晶体管之间的电阻比来执行数字感测方案的功能。可以使用简单的逆变器来检测由电阻比确定的数据线的电平。以单端方式检测位线对，消除了对交叉耦合的CMOS器件的需要，从而减少了所需的布局面积。通过单独访问位线对，开发了用于预充电EQ0，EQ1的两组控制信号，以允许阵列中的位线屏蔽。

58. 发明授权

US06496037B1 Automatic off-chip driver adjustment based on load characteristics 有权
标题翻译：基于负载特性的自动片外驱动器调整
公开(公告)号：US06496037B1
公开(公告)日：2002-12-17
申请号：US09588202
申请日：2000-06-06
申请人： Claude L. Bertin , John A. Fifield , Thomas M. Maffitt , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , John A. Fifield , Thomas M. Maffitt , Wilbur D. Pricer , William R. Tonti
IPC分类号： H03K190175
CPC分类号： H03K19/0005
摘要： An automatic driver adjuster and methods using the same are provided that modify off-chip drivers based on load characteristics. The preferred embodiments are preferably automatic and require little or no human intervention. Preferred embodiments of the current invention analyze and determine the impedance of a node and adjust a number of output drivers in response to the impedance of the node, or analyze a resultant waveform of the node, caused by an input waveform, and adjust a number of output drivers in response to the resultant waveform of the node.
摘要翻译：提供了一种自动驱动器调节器及其使用方法，其基于负载特性修改片外驱动器。优选的实施方案优选是自动的，并且需要很少的或不需要人为干预。本发明的优选实施例分析和确定节点的阻抗并且响应于节点的阻抗调整输出驱动器的数量，或者分析由输入波形引起的节点的合成波形，并且调整多个输出驱动器响应于该结点的合成波形。

59. 发明授权

US06452439B1 Inductive voltage spike generator with diode shunt 失效
标题翻译：具有二极管分流的感应电压尖峰发生器
公开(公告)号：US06452439B1
公开(公告)日：2002-09-17
申请号：US09850353
申请日：2001-05-07
申请人： John A. Fifield , Nicholas M. Van heel
发明人： John A. Fifield , Nicholas M. Van heel
IPC分类号： G05F110
CPC分类号： H01L23/62 , H01L23/5256 , H01L23/58 , H01L2224/48091 , H01L2224/49171 , H01L2924/30107 , H02M3/155 , H01L2924/00014 , H01L2924/00
摘要： A voltage generator for an integrated circuit chip comprises an integrated circuit chip with a power supply having a voltage available to the chip; an inductor on or in contact with the integrated circuit chip electrically connected to the power supply through which current is driven; and a clock adapted to interrupting current flowing from the power supply through the inductor at desired time intervals to create voltage spikes above the power supply voltage. The inductor may comprise a portion of the lead frame connecting the integrated circuit chip to an integrated chip package. The voltage spikes generate a voltage about two or more times the voltage of the power supply available to the chip. Where the integrated circuit chip includes an electrical fuse and/or a battery, the fuse on the chip may be adapted to be programmed or the battery charged by the voltage spikes.
摘要翻译：一种用于集成电路芯片的电压发生器包括具有电源可用于芯片的电源的集成电路芯片; 与集成电路芯片接触或接触的电感器，其电连接到通过其驱动电流的电源; 以及适于以期望的时间间隔中断从电源流过电感器的电流以在电源电压之上产生电压尖峰的时钟。电感器可以包括将集成电路芯片连接到集成芯片封装的引线框架的一部分。电压尖峰产生大约是芯片可用电源电压的两倍或更多倍的电压。在集成电路芯片包括电熔丝和/或电池的情况下，芯片上的保险丝可能被编程或由电压尖峰充电的电池。

60. 发明授权

US06384666B1 Antifuse latch device with controlled current programming and variable trip point 有权
标题翻译：具有受控电流编程和可变跳变点的防漏锁存器件
公开(公告)号：US06384666B1
公开(公告)日：2002-05-07
申请号：US09816030
申请日：2001-03-23
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Nicholas M. van Heel
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Nicholas M. van Heel
IPC分类号： H01H3776
CPC分类号： G11C17/18
摘要： A latch device is provided having a variable resistive trip point and controlled current programming. The latch device has a trip point current control element that controls an amount of current passing from a voltage source into the latch circuit, thereby varying the resistive trip point of the latch device. The latch device also has a programming current control element that controls an amount of programming current passing through the fuse element during programming. The trip point current reference and a programming current reference are provided by reference circuits having a plurality of selectable inputs that operate to change the current references binarily. An integrated circuit is also provided in which a plurality of the fuse latch devices are connected together in parallel such that the same trip point current reference and programming current reference are supplied to each latch device.
摘要翻译：提供具有可变电阻跳变点和受控电流编程的锁存器件。闩锁装置具有跳闸电流控制元件，其控制从电压源流入锁存电路的电流量，从而改变闩锁装置的电阻性跳变点。闩锁装置还具有编程电流控制元件，其控制在编程期间通过熔丝元件的编程电流量。跳变点电流基准和编程电流基准由具有多个可选择输入的参考电路提供，所述多个可选输入用于二次改变当前基准。还提供一种集成电路，其中多个熔丝锁存器件并联连接在一起，使得相同的跳变点电流参考和编程电流基准被提供给每个锁存器件。

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