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51. 发明授权

US5867418A Semiconductor memory device and semiconductor device 失效
标题翻译：半导体存储器件和半导体器件
公开(公告)号：US5867418A
公开(公告)日：1999-02-02
申请号：US957375
申请日：1997-10-24
申请人： Yasuhiko Okasaka , Mikio Asakura , Hideto Hidaka , Masaaki Ura , Fukashi Morishita
发明人： Yasuhiko Okasaka , Mikio Asakura , Hideto Hidaka , Masaaki Ura , Fukashi Morishita
IPC分类号： H01L21/8242 , G11C5/14 , G11C11/4074 , G11C11/4076 , H01L27/02 , H01L27/108 , G11C7/02
CPC分类号： H01L27/0288 , G11C11/4074 , G11C11/4076 , G11C5/14
摘要： For each of pads for control clock signals and address signals included in a DRAM, an n type well region is provided, and each n type well region is connected to an upper power supply source only by means of a first lower power supply line. Therefore, compared with the conventional device in which n type wells are connected to each other by a second lower power supply line, current flowing from the resistance element in a p type well to the upper power supply line is reduced. Therefore, damage to the resistance element 8 can be prevented, and surge immunity of the DRAM is increased.
摘要翻译：对于包括在DRAM中的控制时钟信号和地址信号的每个焊盘，提供n型阱区，并且每个n型阱区仅通过第一较低电源线连接到上电源。因此，与通过第二低电源线连接n个型阱的常规装置相比，减小了从p型阱中的电阻元件流向上部电源线的电流。因此，可以防止对电阻元件8的损坏，并且DRAM的浪涌抗扰度增加。

52. 发明授权

US5757175A Constant current generating circuit 失效
标题翻译：恒流发电电路
公开(公告)号：US5757175A
公开(公告)日：1998-05-26
申请号：US782036
申请日：1997-01-13
申请人： Fukashi Morishita , Masaki Tsukude , Tsukasa Ooishi , Kyoji Yamasaki
发明人： Fukashi Morishita , Masaki Tsukude , Tsukasa Ooishi , Kyoji Yamasaki
IPC分类号： G05F3/26 , G05F3/24 , G11C11/407 , H03F3/343 , G05F3/16
CPC分类号： G05F3/242
摘要： A current source is provided between a first p channel MOS transistor and a ground node, and a current/voltage converting element is provided isolatedly from the current source between the ground node and a second p channel MOS transistor having a conductance coefficient sufficiently larger than that of the first MOS transistor. The second MOS transistor is connected through a resistive element to an external power supply node. A voltage produced by the current/voltage converting element is converted into current by a voltage/current converting portion. Thus, constant current free from both vibration and a deadlock phenomenon and with small external power supply voltage dependency is supplied.
摘要翻译：在第一p沟道MOS晶体管和接地节点之间提供电流源，并且电流/电压转换元件与接地节点和具有足够大的电导系数的第二p沟道MOS晶体管之间的电流源隔离地提供。的第一MOS晶体管。第二MOS晶体管通过电阻元件连接到外部电源节点。由电流/电压转换元件产生的电压由电压/电流转换部分转换成电流。因此，提供不受振动和死锁现象以及小外部电源电压依赖性的恒定电流。

53. 发明授权

US07764540B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07764540B2
公开(公告)日：2010-07-27
申请号：US12281271
申请日：2006-03-01
申请人： Fukashi Morishita , Kazutami Arimoto
发明人： Fukashi Morishita , Kazutami Arimoto
IPC分类号： G11C11/34
CPC分类号： G11C11/405 , G11C7/18 , G11C11/4097 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： By activating a word line and a bit line in parallel with a storage transistor set to OFF, the potential conditions of the charge line, and the word line, and the bit line are controlled so that the potential of a body region is increased by a leak current flowing from a connecting node to the body region in a period until the storage transistor is turned ON.
摘要翻译：通过与设置为OFF的存储晶体管并行地激活字线和位线，控制充电线，字线和位线的电位条件，使得身体区域的电位增加一在存储晶体管导通的期间内，从连接节点流向身体区域的漏电流。

54. 发明授权

US07738312B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07738312B2
公开(公告)日：2010-06-15
申请号：US12000343
申请日：2007-12-12
申请人： Hiroki Shimano , Fukashi Morishita , Kazutami Arimoto
发明人： Hiroki Shimano , Fukashi Morishita , Kazutami Arimoto
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G11C5/063 , G11C7/12 , G11C7/18 , G11C11/405 , G11C11/4094 , G11C11/4097 , G11C2211/4016 , H01L21/84 , H01L27/0207 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： One memory cell is formed of a first port access transistor, a second port access transistor and a storage transistor coupled commonly to these access transistors. The first port access transistor is coupled to a first electrode of the storage transistor, and the second port access transistor is coupled to a third electrode of the storage transistor. These first and second port access transistors enter a selected state when first and second port word lines are selected, respectively, to couple corresponding second and third electrodes of the corresponding storage transistor to first and second port bit lines, respectively. A dual-port memory cell of which scalability can follow miniaturization in a process can be provided.
摘要翻译：一个存储单元由第一端口存取晶体管，第二端口存取晶体管和与这些存取晶体管共同耦合的存储晶体管形成。第一端口存取晶体管耦合到存储晶体管的第一电极，第二端口存取晶体管耦合到存储晶体管的第三电极。当分别选择第一和第二端口字线时，这些第一和第二端口存取晶体管进入选择状态，以将相应的存储晶体管的相应的第二和第三电极分别耦合到第一和第二端口位线。可以提供一种双端口存储单元，其可扩展性可以在一个过程中跟随小型化。

55. 发明授权

US07397315B2 Oscillator and charge pump circuit using the same 失效
标题翻译：振荡器和电荷泵电路使用相同
公开(公告)号：US07397315B2
公开(公告)日：2008-07-08
申请号：US11311301
申请日：2005-12-20
申请人： Masanobu Kishida , Fukashi Morishita
发明人： Masanobu Kishida , Fukashi Morishita
IPC分类号： H03B27/00
CPC分类号： H03K3/0315 , H03K17/063
摘要： The present invention provides a current-limited oscillator capable of performing stable operation even when it is driven with a low power-supply voltage, and a charge pump circuit using the oscillator. A current-limited oscillator has a delay section that includes a plurality of series-connected inverters to delay an output pulse on the basis of a current limiting level indication signal, and the oscillator further includes at least one first transistor that limits a first current between the inverters and a high potential power supply and at least one second transistor that limits a second current between the inverters and a low potential power supply, wherein at least one of the plurality of inverters is configured as a first inverter that is connected with the first transistor and is not connected with the second transistor, and at least another of the plurality of inverters is configured as a second inverter that is not connected with the first transistor and is connected with the second transistor.
摘要翻译：本发明提供一种即使在以低电源电压驱动的情况下也能够稳定工作的电流限制型振荡器和使用该振荡器的电荷泵电路。限流振荡器具有延迟部分，该延迟部分包括多个串联的反相器，用于基于限流电平指示信号来延迟输出脉冲，并且该振荡器还包括至少一个第一晶体管，其限制第一电流所述逆变器和高电位电源以及限制所述逆变器之间的第二电流和低电位电源的至少一个第二晶体管，其中所述多个逆变器中的至少一个被配置为与所述第一逆变器连接的第一逆变器并且不与第二晶体管连接，并且多个反相器中的至少另一个被配置为不与第一晶体管连接并与第二晶体管连接的第二反相器。

56. 发明申请

US20080023764A1 Semiconductor memory device and manufacturing method of the same 失效
公开(公告)号：US20080023764A1
公开(公告)日：2008-01-31
申请号：US11902996
申请日：2007-09-27
申请人： Masakazu Hirose , Fukashi Morishita
发明人： Masakazu Hirose , Fukashi Morishita
IPC分类号： H01L29/786
CPC分类号： H01L27/10873 , G11C11/404 , G11C11/4085 , G11C2211/4016 , H01L21/84 , H01L27/0218 , H01L27/10808 , H01L27/10817 , H01L27/10832 , H01L27/10835 , H01L27/10882 , H01L27/10894 , H01L27/1203 , H01L29/78612
摘要： In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

57. 发明授权

US07157773B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07157773B2
公开(公告)日：2007-01-02
申请号：US10330093
申请日：2002-12-30
申请人： Hiroshi Kato , Shigehiro Kuge , Hideyuki Noda , Fukashi Morishita , Shuichi Ueno
发明人： Hiroshi Kato , Shigehiro Kuge , Hideyuki Noda , Fukashi Morishita , Shuichi Ueno
IPC分类号： H01L27/01
CPC分类号： H01L29/78648 , H01L21/28282 , H01L29/792
摘要： A memory cell of a nonvolatile semiconductor memory device is formed on a silicon layer formed on a silicon substrate through an ONO film. The memory cell has a source region and a drain region formed in the silicon layer, an ONO film and a gate electrode. The ONO film and the ONO film include nitride films having charge trap parts trapping charges.
摘要翻译：非易失性半导体存储器件的存储单元通过ONO膜形成在硅衬底上形成的硅层上。存储单元具有在硅层中形成的源区和漏区，ONO膜和栅电极。 ONO膜和ONO膜包括具有捕获电荷的电荷陷阱部分的氮化物膜。

58. 发明授权

US07068093B2 Semiconductor integrated circuit with voltage adjusting circuit 失效
标题翻译：具有电压调节电路的半导体集成电路
公开(公告)号：US07068093B2
公开(公告)日：2006-06-27
申请号：US10336793
申请日：2003-01-06
申请人： Fukashi Morishita , Takayuki Gyohten
发明人： Fukashi Morishita , Takayuki Gyohten
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/262
摘要： A voltage adjusting circuit includes a transistor connected in a current mirror, and a resistor element connected to the transistor. The resistor element has a resistance that changes with temperature, so the voltage level is adjusted according to variations in temperature. Accordingly, stable control of an internal circuit in which desirable operating characteristics change with temperature can be attained, even when temperature varies.
摘要翻译：电压调节电路包括连接在电流镜中的晶体管和连接到晶体管的电阻元件。电阻元件具有随温度变化的电阻，因此根据温度变化来调整电压电平。因此，即使在温度变化的情况下，也能够实现期望的工作特性随温度变化的内部电路的稳定控制。

59. 发明授权

US07064993B2 Semiconductor memory device with common I/O type circuit configuration achieving write before sense operation 失效
标题翻译：具有通用I / O型电路配置的半导体存储器件在感测操作之前实现写入
公开(公告)号：US07064993B2
公开(公告)日：2006-06-20
申请号：US10671795
申请日：2003-09-29
申请人： Takayuki Gyohten , Masaru Haraguchi , Fukashi Morishita
发明人： Takayuki Gyohten , Masaru Haraguchi , Fukashi Morishita
IPC分类号： G11C7/00
CPC分类号： G11C11/4096 , G11C7/06 , G11C11/4091 , G11C2207/002 , G11C2207/065
摘要： A connection gate circuit includes first and second N channel MOS transistors connected in series between a first bit line of a pair of bit lines and a first global IO line of a pair of IO lines, and third and fourth N channel MOS transistors connected in series between a second bit line of the pair of bit lines and a second global IO line of the pair of IO lines. The first and second N channel MOS transistors have their gates receiving a sense amplifier activation signal activating a sense amplifier. The third and fourth N channel MOS transistors have their gates receiving a column selection signal.
摘要翻译：连接门电路包括串联连接在一对位线的第一位线和一对IO线的第一全局IO线之间的第一和第二N沟道MOS晶体管，以及串联连接的第三和第四N沟道MOS晶体管在所述一对位线的第二位线与所述一对IO线的第二全局IO线之间。第一和第二N沟道MOS晶体管的栅极接收激活读出放大器的读出放大器激活信号。第三和第四N沟道MOS晶体管的栅极接收列选择信号。

60. 发明申请

US20060103434A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060103434A1
公开(公告)日：2006-05-18
申请号：US11272798
申请日：2005-11-15
申请人： Mako Okamoto , Fukashi Morishita
发明人： Mako Okamoto , Fukashi Morishita
IPC分类号： H03K5/22
CPC分类号： G11C5/145 , G11C11/4074 , G11C11/4085 , H03K5/2481
摘要： A detector circuit and a negative voltage generating circuit capable of performing high-speed operation are provided. A negative voltage generating circuit includes a charge pump circuit, a first voltage divider circuit that makes a voltage division between an output of the charge pump circuit and a power supply to output a detect potential, a reference voltage generating circuit that generates a reference potential, and a comparator circuit that compares the detect potential and the reference potential. The charge pump circuit is driven by an output signal of the comparator circuit and generates the negative voltage. In the first voltage divider circuit, NMOS transistors and make the voltage division between the negative voltage and the power supply to obtain the detect potential.
摘要翻译：提供能够执行高速操作的检测器电路和负电压产生电路。负电压产生电路包括电荷泵电路，在电荷泵电路的输出和电源之间进行分压以输出检测电位的第一分压电路，产生参考电位的基准电压产生电路，以及比较电路，其比较检测电位和参考电位。电荷泵电路由比较器电路的输出信号驱动，并产生负电压。在第一分压电路中，NMOS晶体管和负电压和电源之间的分压获得检测电位。

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