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51. 发明申请

US20080111245A1 Electric Element, Memory Device, and Semiconductor Integrated Circuit 有权
标题翻译：电子元件，存储器件和半导体集成电路
公开(公告)号：US20080111245A1
公开(公告)日：2008-05-15
申请号：US11883481
申请日：2006-10-26
申请人： Koichi Osano , Shunsaku Muraoka , Satoru Mitani , Kumio Nago
发明人： Koichi Osano , Shunsaku Muraoka , Satoru Mitani , Kumio Nago
IPC分类号： H01L23/52
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , G11C2213/32 , G11C2213/79 , H01L27/101 , H01L45/08 , H01L45/1233 , H01L45/145
摘要： An electric element includes a first electrode (1), a second electrode (3), and a variable-resistance film (2) connected between the first electrode (1) and the second electrode (3). The variable-resistance film (2) contains Fe (iron) and O (oxygen) as constituent elements. The content of oxygen in the variable-resistance film (2) is modulated along the film thickness direction.
摘要翻译：电气元件包括连接在第一电极（1）和第二电极（3）之间的第一电极（1），第二电极（3）和可变电阻膜（2）。可变电阻膜（2）含有Fe（铁）和O（氧）作为构成元素。可变电阻膜（2）中的氧含量沿着膜厚度方向被调制。

52. 发明申请

US20070196696A1 Thin film memory device having a variable resistance 有权
标题翻译：具有可变电阻的薄膜存储器件
公开(公告)号：US20070196696A1
公开(公告)日：2007-08-23
申请号：US11578521
申请日：2004-10-22
申请人： Koichi Osano , Shunsaku Muraoka , Hiroshi Sakakima
发明人： Koichi Osano , Shunsaku Muraoka , Hiroshi Sakakima
IPC分类号： G11B5/33
CPC分类号： G11C13/0007 , G11C13/003 , G11C2213/31 , G11C2213/78 , G11C2213/79 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147 , Y10T428/1136 , Y10T428/115
摘要： A thin film storage device includes a first electrode (3), a first variable resistance thin film (2), and a second electrode (1). The first electrode (3) is formed over a surface of a substrate (4). The first variable resistance thin film (2) is formed over a surface of the first electrode (3). The second electrode (1) is formed over a surface of the first variable resistance thin film (2). The first variable resistance thin film (2) comprises a material whose resistance in a bulk state changes in accordance with at least one of a lattice strain and a change of charge-order.
摘要翻译：薄膜存储装置包括第一电极（3），第一可变电阻薄膜（2）和第二电极（1）。第一电极（3）形成在衬底（4）的表面上。第一可变电阻薄膜（2）形成在第一电极（3）的表面上。第二电极（1）形成在第一可变电阻薄膜（2）的表面上。第一可变电阻薄膜（2）包括其体积电阻根据晶格应变和电荷顺序的变化中的至少一个而变化的材料。

53. 发明申请

US20070159867A1 Memory device, memory circuit and semiconductor integrated circuit having variable resistance 有权
标题翻译：存储器件，存储器电路和具有可变电阻的半导体集成电路
公开(公告)号：US20070159867A1
公开(公告)日：2007-07-12
申请号：US10584617
申请日：2004-10-22
申请人： Shunsaku Muraoka , Koichi Osano , Ken Takahashi , Masafumi Shimotashiro
发明人： Shunsaku Muraoka , Koichi Osano , Ken Takahashi , Masafumi Shimotashiro
IPC分类号： G11C17/00
CPC分类号： H01L27/2436 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/0083 , G11C2213/31 , G11C2213/75 , G11C2213/78 , G11C2213/79 , H01L27/2463 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A first variable resistor (5) is connected between a first terminal (7) and a third terminal (9) and increases/reduces its resistance value in accordance with the polarity of a pulse voltage applied between the first terminal (7) and the third terminal (9). A second variable resistor (6) is connected between the third terminal (9) and a second terminal (8) and increases/reduces its resistance value in accordance with the polarity of a pulse voltage applied between the third terminal (9) and the second terminal (8). Given pulse voltages are applied between the first terminal (7) and the third terminal (9) and between the third terminal (9) and the second terminal (8) to reversibly change the resistance values of the first and second variable resistors (5, 6), thereby recording one bit or multiple bits of information.
摘要翻译：第一可变电阻器（5）连接在第一端子（7）和第三端子（9）之间，并且根据施加在第一端子（7）和第三端子（7）之间的脉冲电压的极性来增大/减小其电阻值终端（9）。第二可变电阻器（6）连接在第三端子（9）和第二端子（8）之间，并根据在第三端子（9）和第二端子（8）之间施加的脉冲电压的极性来增大/减小其电阻值端子（8）。给定脉冲电压施加在第一端子（7）和第三端子（9）之间以及第三端子（9）和第二端子（8）之间，以可逆地改变第一和第二可变电阻器（5）的电阻值， 6），从而记录一位或多位信息。

54. 发明授权

US5208971A Process of manufacturing a magnetic head 失效
标题翻译：磁头制造工艺
公开(公告)号：US5208971A
公开(公告)日：1993-05-11
申请号：US700461
申请日：1991-05-15
申请人： Shunsaku Muraoka , Eisuke Sawai , Etsuko Suzuki
发明人： Shunsaku Muraoka , Eisuke Sawai , Etsuko Suzuki
IPC分类号： G11B5/127 , G11B5/105 , G11B5/147
CPC分类号： G11B5/1475 , G11B5/105 , Y10T29/49057
摘要： A method of making a magnetic head wherein a metal material is sandwiched between non-magnetic substrates, including the steps of: forming a magnetic metal material at least on one side of a non-magnetic substrate; forming by sputtering a crystallization glass layer at least on one side of a compound substrate prepared by forming an anti-diffusion film on the magnetic metal material; then heat-treating in an oxygen containing atmosphere the compound substrate on which the crystallization glass has been formed; further laminating together a number of the aforesaid compound substrates under pressure and then processing (such as by cutting, grinding, and heat-treating) the laminate.
摘要翻译：一种制造磁头的方法，其中金属材料夹在非磁性衬底之间，包括以下步骤：在非磁性衬底的至少一侧形成磁性金属材料; 通过在通过在磁性金属材料上形成抗扩散膜制备的复合基板的至少一面上溅射结晶玻璃层而形成; 然后在含氧气氛中对其上形成结晶玻璃的复合基板进行热处理; 在压力下进一步层压在一起的上述复合基板，然后对层压体进行加工（例如通过切割，研磨和热处理）。

55. 发明授权

US09153319B2 Method for driving nonvolatile memory element, and nonvolatile memory device having a variable resistance element 有权
标题翻译：用于驱动非易失性存储元件的方法，以及具有可变电阻元件的非易失性存储器件
公开(公告)号：US09153319B2
公开(公告)日：2015-10-06
申请号：US14004447
申请日：2012-03-13
申请人： Shunsaku Muraoka , Satoru Mitani , Takeshi Takagi
发明人： Shunsaku Muraoka , Satoru Mitani , Takeshi Takagi
IPC分类号： G11C11/00 , G11C13/00 , H01L27/10 , H01L27/24 , H01L45/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C2013/0073 , G11C2013/0092 , G11C2213/32 , G11C2213/79 , H01L27/101 , H01L27/2436 , H01L45/04 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： A method for driving a nonvolatile memory element includes: a writing step of changing a variable resistance layer to a low resistance state, by applying a writing voltage pulse having a first polarity; and an erasing step of changing the variable resistance layer to a high resistance state, by applying an erasing voltage pulse having a second polarity different from the first polarity, wherein in the writing step, a first input and output terminal of a field effect transistor is a source terminal of the transistor, and when a pulse width of the writing voltage pulse is PWLR and a pulse width of the erasing voltage pulse is PWHR, PWLR and PWHR satisfy a relationship of PWLR
摘要翻译：一种用于驱动非易失性存储元件的方法包括：通过施加具有第一极性的写入电压脉冲将可变电阻层改变为低电阻状态的写入步骤; 以及通过施加具有与第一极性不同的第二极性的擦除电压脉冲将可变电阻层改变为高电阻状态的擦除步骤，其中在写入步骤中，场效应晶体管的第一输入和输出端子是晶体管的源极端子，并且当写入电压脉冲的脉冲宽度为PWLR且擦除电压脉冲的脉冲宽度为PWHR时，PWLR和PWHR满足PWLR

56. 发明授权

US08565005B2 Nonvolatile memory element and nonvolatile memory device 有权
标题翻译：非易失性存储器元件和非易失性存储器件
公开(公告)号：US08565005B2
公开(公告)日：2013-10-22
申请号：US13599286
申请日：2012-08-30
申请人： Takeshi Takagi , Zhiqiang Wei , Takeki Ninomiya , Shunsaku Muraoka , Yoshihiko Kanzawa
发明人： Takeshi Takagi , Zhiqiang Wei , Takeki Ninomiya , Shunsaku Muraoka , Yoshihiko Kanzawa
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/31 , G11C2213/32 , G11C2213/56 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/1675
摘要： A nonvolatile memory element includes: a first electrode layer; a second electrode layer; and a variable resistance layer which is placed between the electrode layers, and whose resistance state reversibly changes between a high resistance state and a low resistance state based on a polarity of a voltage applied between the electrode layers. The variable resistance layer is formed by stacking a first oxide layer including an oxide of a first transition metal and a second oxide layer including an oxide of a second transition metal which is different from the first transition metal. At least one of the following conditions is satisfied: (1) a dielectric constant of the second oxide layer is larger than a dielectric constant of the first oxide layer; and (2) a band gap of the second oxide layer is smaller than a band gap of the first oxide layer.
摘要翻译：非易失性存储元件包括：第一电极层; 第二电极层; 以及可变电阻层，其设置在电极层之间，并且其电阻状态基于施加在电极层之间的电压的极性而在高电阻状态和低电阻状态之间可逆地变化。可变电阻层通过堆叠包括第一过渡金属的氧化物的第一氧化物层和包含与第一过渡金属不同的第二过渡金属的氧化物的第二氧化物层而形成。满足以下条件中的至少一个：（1）第二氧化物层的介电常数大于第一氧化物层的介电常数; 和（2）第二氧化物层的带隙小于第一氧化物层的带隙。

57. 发明授权

US08345465B2 Driving method of variable resistance element, initialization method of variable resistance element, and nonvolatile storage device 有权
标题翻译：可变电阻元件的驱动方法，可变电阻元件的初始化方法和非易失性存储器件
公开(公告)号：US08345465B2
公开(公告)日：2013-01-01
申请号：US12745300
申请日：2009-09-30
申请人： Shunsaku Muraoka , Takeshi Takagi , Satoru Mitani , Koji Katayama
发明人： Shunsaku Muraoka , Takeshi Takagi , Satoru Mitani , Koji Katayama
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0033 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2013/009 , G11C2213/31 , G11C2213/32 , G11C2213/34
摘要： A method of driving a variable resistance element includes: a writing step performed by applying a writing voltage pulse having a first polarity to a variable resistance layer to change a resistance state of the layer from high to low; and an erasing step performed by applying an erasing voltage pulse having a second polarity to the layer to change the state from low to high. Here, |Vw1|>|Vw2| where Vw1 represents a voltage value of the writing voltage pulse for first to N-th writing steps (N≧1) and Vw2 represents a voltage value of the writing voltage pulse for (N+1)-th and subsequent writing steps, and |Ve1|>|Ve2| where Ve1 represents a voltage value of the erasing voltage pulse for first to M-th erasing steps (M≧1) and Ve2 represents a voltage value of the erasing voltage pulse for (M+1)-th and subsequent erasing steps. The (N+1)-th writing step follows the M-th erasing step.
摘要翻译：驱动可变电阻元件的方法包括：通过将具有第一极性的写入电压脉冲施加到可变电阻层而将层的电阻状态从高变为低的步骤来执行写入步骤; 以及通过将具有第二极性的擦除电压脉冲施加到该层以将状态从低变为高而执行的擦除步骤。这里，| Vw1 |> | Vw2 | 其中Vw1表示第一至第N写入步骤（N≥1）的写入电压脉冲的电压值，Vw2表示第（N + 1）个和后续写入步骤中的写入电压脉冲的电压值， Ve1 |> | Ve2 | 其中Ve1表示第一至第M擦除步骤（M≥1）的擦除电压脉冲的电压值，Ve2表示（M + 1）次和随后的擦除步骤中的擦除电压脉冲的电压值。第（N + 1）个写入步骤在第M擦除步骤之后。

58. 发明授权

US08279657B2 Nonvolatile memory element and nonvolatile memory device 有权
标题翻译：非易失性存储器元件和非易失性存储器件
公开(公告)号：US08279657B2
公开(公告)日：2012-10-02
申请号：US12990323
申请日：2009-12-04
申请人： Takeshi Takagi , Zhiqiang Wei , Takeki Ninomiya , Shunsaku Muraoka , Yoshihiko Kanzawa
发明人： Takeshi Takagi , Zhiqiang Wei , Takeki Ninomiya , Shunsaku Muraoka , Yoshihiko Kanzawa
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/31 , G11C2213/32 , G11C2213/56 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/1675
摘要： Provided is a nonvolatile memory element which is capable of performing a stable resistance change operation at a low breakdown voltage.A nonvolatile memory element (100) includes: a first electrode layer (103); a second electrode layer (105); and a variable resistance layer (104) which is placed between the electrodes (103 and 105), and whose resistance state reversibly changes between a high resistance state and a low resistance state based on a polarity of a voltage applied between the electrodes (103 and 105). The variable resistance layer (104) is formed by stacking a first oxide layer (104a) including an oxide of a first transition metal and a second oxide layer (104b) including an oxide of a second transition metal which is different from the first transition metal. At least one of the following conditions is satisfied: (1) a dielectric constant of the second oxide layer (104b) is larger than a dielectric constant of the first oxide layer (104a); and (2) a band gap of the second oxide layer (104b) is smaller than a band gap of the first oxide layer (104a).
摘要翻译：提供一种能够在低击穿电压下进行稳定的电阻变化操作的非易失性存储元件。非易失性存储元件（100）包括：第一电极层（103）; 第二电极层（105）; 和位于电极（103和105）之间的可变电阻层（104），并且其电阻状态基于在电极（103和103）之间施加的电压的极性而在高电阻状态和低电阻状态之间可逆地变化 105）。可变电阻层（104）通过堆叠包括第一过渡金属的氧化物的第一氧化物层（104a）和包含与第一过渡金属不同的第二过渡金属的氧化物的第二氧化物层（104b）。满足以下条件中的至少一个：（1）第二氧化物层（104b）的介电常数大于第一氧化物层（104a）的介电常数; 和（2）第二氧化物层（104b）的带隙小于第一氧化物层（104a）的带隙。

59. 发明授权

US07964869B2 Memory element, memory apparatus, and semiconductor integrated circuit 有权
标题翻译：存储元件，存储器件和半导体集成电路
公开(公告)号：US07964869B2
公开(公告)日：2011-06-21
申请号：US12376256
申请日：2007-08-17
申请人： Shunsaku Muraoka , Satoru Fujii , Satoru Mitani , Koichi Osano
发明人： Shunsaku Muraoka , Satoru Fujii , Satoru Mitani , Koichi Osano
IPC分类号： H01L29/10
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , G11C2213/32 , G11C2213/55 , G11C2213/79 , H01L27/101 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1683
摘要： A memory element comprises a first electrode, a second electrode, and a resistance variable film 2 which is disposed between the first and second electrodes to be connected to the first and second electrodes, a resistance value of the resistance variable film 2 varying based on voltage applied between the first and second electrodes, the resistance variable film 2 includes a layer 2a made of Fe3O4 and a layer 2b made of Fe2O3 or a spinel structure oxide which is expressed as MFe2O4 (M: metal element except for Fe); and the layer 2a made of Fe3O4 is thicker than the layer 2b made of Fe2O3 or the spinel structure oxide.
摘要翻译：存储元件包括第一电极，第二电极和电阻可变膜2，电阻可变膜2设置在与第一和第二电极连接的第一和第二电极之间，电阻变化膜2的电阻值基于电压变化电阻可变膜2包括由Fe 3 O 4制成的层2a和由Fe 2 O 3制成的层2b或以MFe 2 O 4表示的尖晶石结构氧化物（M：除了Fe之外的金属元素）; 由Fe 3 O 4制成的层2a比由Fe 2 O 3或尖晶石结构氧化物制成的层2b厚。

60. 发明申请

US20110080770A1 METHOD OF PROGRAMMING VARIABLE RESISTANCE ELEMENT AND NONVOLATILE STORAGE DEVICE 有权
标题翻译：可变电阻元件和非易失性存储器件的编程方法
公开(公告)号：US20110080770A1
公开(公告)日：2011-04-07
申请号：US12994462
申请日：2010-03-25
申请人： Shunsaku Muraoka , Takeshi Takagi , Satoru Mitani , Koji Katayama
发明人： Shunsaku Muraoka , Takeshi Takagi , Satoru Mitani , Koji Katayama
IPC分类号： G11C11/21
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0083 , G11C2213/72 , G11C2213/79 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625
摘要： Applying a writing voltage pulse having a first polarity to a metal oxide layer (3) to change a resistance state of the metal oxide layer (3) from high to low so as to render the resistance state a write state, applying an erasing voltage pulse having a second polarity different from the first polarity to the metal oxide layer (3) to change the resistance state of the metal oxide layer (3) from low to high so as to render the resistance state an erase state, and applying an initial voltage pulse having the second polarity to the metal oxide layer (3) before the applying of a writing voltage pulse is performed for a first time, to change a resistance value of an initial state of the metal oxide layer (3) are included, and R0>RH>RL and |V0|>|Ve|≧|Vw| are satisfied where R0, RL, and RH are the resistance values of the initial, write, and erase states, respectively, of the metal oxide layer (3), and V0, Vw, and Ve are voltage values of the initial, writing, and erasing voltage pulses, respectively.
摘要翻译：将具有第一极性的写入电压脉冲施加到金属氧化物层（3）以将金属氧化物层（3）的电阻状态从高变为低，以使电阻状态成为写入状态，施加擦除电压脉冲具有与第一极性不同于金属氧化物层（3）的第二极性，以将金属氧化物层（3）的电阻状态从低到高改变为使得电阻状态为擦除状态，并且施加初始电压首先执行施加写入电压脉冲之前对金属氧化物层（3）具有第二极性的脉冲，以改变金属氧化物层（3）的初始状态的电阻值，并且R0 > RH> RL，| V0 |> | Ve |≥| Vw | 满足R0，RL和RH分别为金属氧化物层（3）的初始，写入和擦除状态的电阻值，V0，Vw和Ve为初始，写入和写入的电压值，并分别擦除电压脉冲。

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