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51. 发明授权

US5591999A Electrically erasable programmable read only memory device with an improved memory cell pattern layout 失效
标题翻译：具有改进的存储单元图案布局的电可擦除可编程只读存储器件
公开(公告)号：US5591999A
公开(公告)日：1997-01-07
申请号：US257188
申请日：1994-06-08
申请人： Masaki Momodomi , Junichi Miyamoto , Toshiharu Watanabe
发明人： Masaki Momodomi , Junichi Miyamoto , Toshiharu Watanabe
IPC分类号： H01L21/8247 , H01L23/532 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L23/53271 , H01L2924/0002
摘要： A semiconductor memory device according to the present invention comprises a plurality of electrically rewritable memory cells, each of which contains a drain and a source, at least one source line coupled to the sources of the memory cells through a contact hole, and bit lines arranged so as to avoid the contact hole.
摘要翻译：根据本发明的半导体存储器件包括多个电可重写存储单元，每个存储单元包含漏极和源极，至少一个源极线通过接触孔耦合到存储器单元的源极，并且位线布置以避免接触孔。

52. 发明授权

US5452249A Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells 失效
标题翻译：具有用于验证写入存储单元的数据的验证模式的非易失性半导体存储器件
公开(公告)号：US5452249A
公开(公告)日：1995-09-19
申请号：US210434
申请日：1994-03-21
申请人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
发明人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
IPC分类号： G11C17/00 , G11C7/02 , G11C7/10 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454 , G11C7/02 , G11C7/1006 , G11C7/1048
摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element, and a transistor changes the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.
摘要翻译：非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。位线通过开关元件连接到触发器电路，并且晶体管改变位线。连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位，在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。数据设定电路在检测模式中位线处于充电电位时，将触发器电路的第一和第二信号节点中的一个连接到预定电位，从而将触发电路设置为第二状态在验证模式之前的状态。

53. 发明授权

US4970691A 2-cell/1-bit type EPROM 失效
标题翻译： 2单元/ 1位型EPROM
公开(公告)号：US4970691A
公开(公告)日：1990-11-13
申请号：US334842
申请日：1989-04-07
申请人： Shigeru Atsumi , Sumio Tanaka , Junichi Miyamoto
发明人： Shigeru Atsumi , Sumio Tanaka , Junichi Miyamoto
IPC分类号： G11C17/00 , G11C7/00 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/28 , G11C16/34 , G11C29/00 , G11C29/34
CPC分类号： G11C16/3459 , G11C16/0441 , G11C16/10 , G11C16/28 , G11C16/3454
摘要： The first input terminal of a differential amplification type sense amplifier is connected to a first memory cell array and the second input terminal thereof is connected to a second memory cell array. Each of the first and second memory cell arrays is formed of a plurality of memory cells arranged in a matrix form. Each of the memory cells in the first memory cell array and a corresponding one of the memory cells in the second memory cell array are provided in the form of pair for each bit. Complementary data is programmed into the paired memory cells according to programming data. In the data readout operation, the potential of data read out from the paired memory cells is amplified by means of the differential amplification type sense amplifier. First and second loads are connected to the first and second input terminals of the differential amplification type sense amplifier. The mutual conductances of the first and second loads are controlled so as to set the potential difference between the potentials of data read out from the paired memory cells selected in the first and second memory cell arrays smaller in the verify mode than in the normal readout mode.

54. 发明授权

US4951257A Reference setting circuit for determining written-in content in nonvolatile semiconductor memories 失效
标题翻译：用于确定非易失性半导体存储器中的写入内容的参考设置电路
公开(公告)号：US4951257A
公开(公告)日：1990-08-21
申请号：US197437
申请日：1988-05-23
申请人： Keniti Imamiya , Sumio Tanaka , Junichi Miyamoto , Shigeru Atsumi , Yumiko Iyama , Nobuaki Ohtsuka
发明人： Keniti Imamiya , Sumio Tanaka , Junichi Miyamoto , Shigeru Atsumi , Yumiko Iyama , Nobuaki Ohtsuka
IPC分类号： G11C29/00 , G11C16/02 , G11C16/06 , G11C16/34 , G11C17/00 , G11C29/12
CPC分类号： G11C16/3459 , G11C16/3454
摘要： A nonvolatile semiconductor memory according to this invention is so constructed that different data readout references are used in an ordinary readout mode and in a program verification mode. The different read-out references can be set by changing reference input potential VREF supplied to a differential sense amplifier for amplifying a potential derived onto a bit line from a memory cell, or by changing an input threshold level of a circuit for sensing the potential on the bit line. In this case, the readout reference in the program verification mode is set severe, or high, in comparison with that in the ordinary readout mode.
摘要翻译：根据本发明的非易失性半导体存储器被构造成使得在普通读出模式和程序验证模式中使用不同的数据读出参考。可以通过改变提供给差分读出放大器的参考输入电位VREF来设置不同的读出参考，以便放大从存储单元导出到位线上的电位，或者通过改变用于感测电位的电路的输入阈值电平位线。在这种情况下，与普通读出模式相比，程序验证模式中的读出参考被设定为严格或高。

55. 发明授权

US4616143A High voltage bootstrapping buffer circuit 失效
标题翻译：高电压自举缓冲电路
公开(公告)号：US4616143A
公开(公告)日：1986-10-07
申请号：US645627
申请日：1984-08-30
申请人： Junichi Miyamoto
发明人： Junichi Miyamoto
IPC分类号： H03K19/0185 , G11C16/12 , H03K19/017 , H03K19/0948 , H03K17/10 , G11C11/40 , H03K3/027 , H03K17/687
CPC分类号： H03K19/01714 , G11C16/12 , H03K19/01735
摘要： A logic circuit comprises a first MOS transistor of a first conductive type having a gate connected to an input/output line and a source connected to a first power source, a second MOS transistor of a second conductive type having a gate connected to the drain of the first MOS transistor, a source connected to a second power source, and a drain connected to the gate of the first MOS transistor, and a capacitor connected across the gate and source of the second MOS transistor. With the logic circuit of the invention it is possible to change a logic level without forming a direct path. This makes it possible to reduce load of a boosting circuit and a power supply. Also it can be used in a waveform shaping circuit.
摘要翻译：逻辑电路包括第一导电类型的第一MOS晶体管，其具有连接到输入/输出线的栅极和连接到第一电源的源极，第二导电类型的第二MOS晶体管，具有连接到漏极的漏极第一MOS晶体管，连接到第二电源的源极和连接到第一MOS晶体管的栅极的漏极以及连接在第二MOS晶体管的栅极和源极之间的电容器。利用本发明的逻辑电路，可以在不形成直接路径的情况下改变逻辑电平。这使得可以减小升压电路和电源的负载。也可以用在波形整形电路中。

56. 发明授权

US08459119B2 Method of determining propagation time of ultrasonic from movable body and system thereof 有权
标题翻译：确定超声波从移动体传播时间的方法及其系统
公开(公告)号：US08459119B2
公开(公告)日：2013-06-11
申请号：US12524756
申请日：2008-01-28
申请人： Junichi Miyamoto
发明人： Junichi Miyamoto
IPC分类号： G01N21/00
CPC分类号： G06F3/043 , G01S11/16
摘要： For precisely determining a position of an electronic pen using ultrasonic, only a direct wave arriving first at a reception device is detected without being affected by a reflected wave of an ultrasonic signal to count a propagation time of the electronic pen.An infrared signal including a trigger signal indicative of transmission timing and data indicative of an M-sequence initial condition, and an ultrasonic signal made into an M-sequence are simultaneously sent from the electronic pen in each fixed transmission cycle. The reception device disposed at a predetermined position receives the infrared signal from the electronic pen to generate an M-sequence model waveform from M-sequence initial condition data that the infrared signal includes. The reception device further receives the ultrasonic signal from the electronic pen to calculate a value of correlation between the ultrasonic signal and the above-described M-sequence model waveform. Upon detecting a first peak of the calculated correlation value, the reception device calculates a propagation time of ultrasonic from the electronic pen from a time point of reception of the previously received trigger signal and a time point of detection of the detected correlation peak.
摘要翻译：为了精确地确定使用超声波的电子笔的位置，仅检测首先到达接收装置的直接波，而不受超声波信号的反射波的影响，以计算电子笔的传播时间。在每个固定的传输周期中，同时从电子笔发送包括表示发送定时的触发信号和表示M序列初始状态的数据的红外信号以及被制成M序列的超声波信号。设置在预定位置的接收装置接收来自电子笔的红外信号，以从红外信号所包含的M序列初始条件数据生成M序列模型波形。接收装置还从电子笔接收超声波信号，计算超声信号与上述M序列模型波形的相关值。在检测到所计算的相关值的第一峰值时，接收装置从先前接收到的触发信号的接收时间点和检测到的相关峰值的检测时间点计算来自电子笔的超声波的传播时间。

57. 发明授权

US08062123B2 Game system 失效
标题翻译：游戏系统
公开(公告)号：US08062123B2
公开(公告)日：2011-11-22
申请号：US11499641
申请日：2006-08-07
申请人： Noriaki Ueda , Shuhei Fujibe , Jiro Yoshida , Chisaki Kusajima , Junichi Miyamoto , Manabu Igarashi
发明人： Noriaki Ueda , Shuhei Fujibe , Jiro Yoshida , Chisaki Kusajima , Junichi Miyamoto , Manabu Igarashi
IPC分类号： A63F9/24
CPC分类号： G07F17/32
摘要： A game system is disclosed that comprises a server system and a game parlor connected to the server system through a network, the server system forming and retaining a unit price schedule data that set a unit price for a predetermined unit time, the game parlor including a plurality of game terminals connected to a parlor LAN, and a parlor server, the game parlor retaining corresponding unit price schedule data sent from the server system to the parlor server, the plurality of game terminals accessing the parlor server at a time interval shorter than the predetermined unit time to acquire unit price information in accordance with the unit price schedule.
摘要翻译：公开了一种游戏系统，其包括通过网络连接到服务器系统的服务器系统和游戏室，所述服务器系统形成并保持设定单位价格为预定单位时间的单价格表数据，所述游戏室包括连接到客厅LAN的多个游戏终端和客厅服务器，游戏室保持从服务器系统发送到客厅服务器的相应单价格表数据，多个游戏终端以比该服务器系统更短的时间间隔访问客厅服务器预定单位时间按照单位价格表获得单价信息。

58. 发明申请

US20070127292A1 Nonvolatile Semiconductor Memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20070127292A1
公开(公告)日：2007-06-07
申请号：US11671209
申请日：2007-02-05
申请人： Koji Sakui , Junichi Miyamoto
发明人： Koji Sakui , Junichi Miyamoto
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0433
摘要： A memory cell array has a unit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.
摘要翻译：存储单元阵列具有由一个存储单元形成的单元和夹着该存储单元的两个选择晶体管。一个块有一个控制栅极线。连接到一个控制门线的存储单元形成一页。具有锁存功能的读出放大器连接到位线。在数据更改操作中，一页的存储单元的数据被读取到读出放大器。在对读出放大器中的数据进行数据更新之后，执行页擦除，读出放大器中的数据被编程在一页的存储单元中。在读出放大器中的数据的替换允许对字节数据或页数据进行数据改变操作。

59. 发明申请

US20060222498A1 Impeller for centrifugal blower 审中-公开
标题翻译：离心式鼓风机叶轮
公开(公告)号：US20060222498A1
公开(公告)日：2006-10-05
申请号：US11398479
申请日：2006-04-05
申请人： Kazuhiro Yoshida , Junichi Miyamoto
发明人： Kazuhiro Yoshida , Junichi Miyamoto
IPC分类号： B64C11/00
CPC分类号： F04D29/263 , F04D29/281
摘要： An impeller 10 for a centrifugal blower 3 is of a closed type and comprises a first molded part 18 and a second molded part 20. The first part is formed by integrally molding a side plate 14, vanes 16, and a circular base 26 having a smaller area than a central opening 22 formed in the side plate. The second part acts as a main plate 12, having a boss section 24 formed with a recess section 30 into which the circular base is fitted. The impeller can be formed by joining the first and second parts together to form a single body, by fastening both of the circular base and the boss section to the rotating shaft 8 of a drive source 4 in a state where the circular base is fitted into the recess section.
摘要翻译：用于离心式鼓风机3的叶轮10是封闭式的，包括第一模制件18和第二模制件20。第一部分通过一体地模制侧板14，叶片16和具有比形成在侧板中的中心开口22更小的面积的圆形基部26而形成。第二部分用作主板12，其具有形成有圆形基部安装到其中的凹部30的凸台部24。叶轮可以通过将第一和第二部分接合在一起形成单体，通过将圆形基部和凸台部分两者固定在驱动源4的旋转轴8上，其中圆形基座装配到凹部。

60. 发明授权

US07054188B2 Magnetic memory device 失效
公开(公告)号：US07054188B2
公开(公告)日：2006-05-30
申请号：US11012178
申请日：2004-12-16
申请人： Ryousuke Takizawa , Junichi Miyamoto , Yoshihisa Iwata
发明人： Ryousuke Takizawa , Junichi Miyamoto , Yoshihisa Iwata
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C5/063
摘要： A magnetic memory device includes a memory cell array including MTJ elements provided at the coordinates (x, y). First write lines extend in a direction neither perpendicular nor parallel to the magnetization easy axis direction of the MTJ elements. One and the other end of one first write line pass an upper or lower periphery of the memory cell array and a left or right periphery of the memory cell array, respectively. The first write lines and second write lines sandwich the MTJ elements. First write line drivers are connected to both ends of the first write lines, one and the other end of a pair of the first write line drivers connected to ends of one first write lines are located outside the upper or lower periphery and outside the left or right periphery, respectively. Second write line drivers are connected to both ends of the second write lines.

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