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51. 发明授权

US07995417B2 Semiconductor memory circuit 有权
公开(公告)号：US07995417B2
公开(公告)日：2011-08-09
申请号：US12923338
申请日：2010-09-15
申请人： Takesada Akiba , Shigeld Ueda , Toshikazu Tachibana , Masashi Horiguchi
发明人： Takesada Akiba , Shigeld Ueda , Toshikazu Tachibana , Masashi Horiguchi
IPC分类号： G11C5/14 , G11C8/00
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

52. 发明申请

US20110032777A1 Semiconductor memory circuit 有权
标题翻译：半导体存储电路
公开(公告)号：US20110032777A1
公开(公告)日：2011-02-10
申请号：US12923338
申请日：2010-09-15
申请人： Takesada Akiba , Shigeld Ueda , Toshikazu Tachibana , Masashi Horiguchi
发明人： Takesada Akiba , Shigeld Ueda , Toshikazu Tachibana , Masashi Horiguchi
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
摘要翻译：本发明提供了一种半导体存储器电路，其能够在配备有共享使用电源，地址信号和数据总线的多个芯片的系统中减少非操作时的电流消耗。半导体存储器电路具有内部电路，其能够选择性地通过开关装置执行工作电压的供应和停止，并且包括存储器阵列。在其中接收预定控制信号的输入电路通过开关装置控制供电和停止工作电压，以便在不进行存储器操作时减小直流电流和泄漏电流，由此可以实现低功耗。

53. 再颁专利

USRE41379E1 Large-Capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed 有权
标题翻译：大容量半导体存储器，具有改进的子放大器布局以提高操作速度
公开(公告)号：USRE41379E1
公开(公告)日：2010-06-15
申请号：US11759345
申请日：2007-06-07
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C8/00
CPC分类号： H01L27/10805 , G11C7/10 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。

54. 再颁专利

USRE40356E1 Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed 有权
标题翻译：大容量半导体存储器，具有改进的子放大器布局，以提高操作速度
公开(公告)号：USRE40356E1
公开(公告)日：2008-06-03
申请号：US11176881
申请日：2005-07-08
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C8/00
CPC分类号： H01L27/10805 , G11C7/10 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。

55. 发明授权

US07342562B2 Liquid crystal drive device 有权
标题翻译：液晶驱动装置
公开(公告)号：US07342562B2
公开(公告)日：2008-03-11
申请号：US10830072
申请日：2004-04-23
申请人： Yasushi Kawase , Takesada Akiba , Kazuya Endo , Goro Sakamaki
发明人： Yasushi Kawase , Takesada Akiba , Kazuya Endo , Goro Sakamaki
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G3/3696 , G09G2330/021
摘要： By implementing reduction in power of common electrode voltages applied from a power source of a liquid crystal drive device to common electrode interconnects of a liquid crystal display panel, respectively, reduction in power consumption of the liquid crystal display panel as a whole is attained.A VCOM operation waveform in a charging process from a second voltage VCOML to a first voltage VCOMH shows that a charging current Icha represents the sum of a charging current from VCOML to a reference voltage VCI, Icha1=Cp (VCI−VCOML)/Δt, and a charging current from the reference voltage VCI to the first voltage VCOMH, Icha2=Cp (VCOMH−VCI)/Δt. Accordingly, power consumed by Icha1 is the reference voltage VCI×Icha1, and power consumed by Icha2 is VCI×Icha2×2. Meanwhile, a discharging current at a time of discharging from the first voltage VCOMH to the second voltage VCOML is the sum of a discharging current from the first voltage VCOMH to the ground potential GND, Idis1=Cp (VCOMH−GND)/Δt, and a discharging current from the ground potential GND to the second voltage VCOML, Idis2=Cp (GND−VCOML)/Δt. Now, if converted in terms of power consumed at the reference voltage VCI, since Idis1 represents discharge to GND, power consumption thereby becomes zero. Then, consumed power due to the discharging current from the ground potential GND to the second voltage VCOML, Idis2, is VCI×Idis2.
摘要翻译：通过将从液晶驱动装置的电源施加的共电极电压的功率分别实现为液晶显示面板的公共电极互连，能够实现液晶显示面板的整体功耗的降低。从第二电压VCOML到第一电压VCOMH的充电过程中的VCOM操作波形示出充电电流Icha表示从VCOML到参考电压VCI的充电电流之和Icha 1 = Cp（VCI-VCOML）/ Deltat ，以及从参考电压VCI到第一电压VCOMH，Icha 2 = Cp（VCOMH-VCI）/ Deltat的充电电流。因此，Icha1消耗的功率是参考电压VCIxIcha1，Icha2消耗的功率是VCIxIcha 2×2。同时，从第一电压VCOMH向第二电压VCOML放电时的放电电流是从第一电压VCOMH到地电位GND的放电电流Idis 1 = Cp（VCOMH-GND）/ Deltat，和从地电位GND到第二电压VCOML的放电电流Idis 2 = Cp（GND-VCOML）/ Deltat。现在，如果以参考电压VCI消耗的功率转换，由于Idis 1表示放电到GND，因此功耗为零。然后，由于从地电位GND到第二电压VCOML，Idis2的放电电流的消耗功率为VCIxIdis 2。

56. 发明申请

US20070296665A1 Liquid crystal drive device 审中-公开
标题翻译：液晶驱动装置
公开(公告)号：US20070296665A1
公开(公告)日：2007-12-27
申请号：US11892619
申请日：2007-08-24
申请人： Yasushi Kawase , Takesada Akiba , Kazuya Endo , Goro Sakamaki
发明人： Yasushi Kawase , Takesada Akiba , Kazuya Endo , Goro Sakamaki
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G3/3696 , G09G2330/021
摘要： By implementing reduction in power of common electrode voltages applied from a power source of a liquid crystal drive device to common electrode interconnects of a liquid crystal display panel, respectively, reduction in power consumption of the liquid crystal display panel as a whole is attained. A VCOM operation waveform in a charging process from a second voltage VCOML to a first voltage VCOMH shows that a charging current Icha represents the sum of a charging current from VCOML to a reference voltage VCI, Icha1=Cp (VCI−VCOML)/Δt, and a charging current from the reference voltage VCI to the first voltage VCOMH, Icha2=Cp (VCOMH−VCI)/Δt. Accordingly, power consumed by Icha1 is the reference voltage VCI×Icha1, and power consumed by Icha2 is VCI×Icha2×2. Meanwhile, a discharging current at a time of discharging from the first voltage VCOMH to the second voltage VCOML is the sum of a discharging current from the first voltage VCOMH to the ground potential GND, Idis1=Cp (VCOMH−GND)/Δt, and a discharging current from the ground potential GND to the second voltage VCOML, Idis2=Cp (GND−VCOML)/Δt. Now, if converted in terms of power consumed at the reference voltage VCI, since Idis1 represents discharge to GND, power consumption thereby becomes zero. Then, consumed power due to the discharging current from the ground potential GND to the second voltage VCOML, Idis2, is VCI×Idis2.
摘要翻译：通过将从液晶驱动装置的电源施加的共电极电压的功率分别实现为液晶显示面板的公共电极互连，能够实现液晶显示面板的整体功耗的降低。从第二电压VCOML到第一电压VCOMH的充电过程中的VCOM操作波形示出充电电流Icha表示从VCOML到参考电压VCI的充电电流之和Icha 1 = Cp（VCI-VCOML）/ Deltat ，以及从参考电压VCI到第一电压VCOMH，Icha 2 = Cp（VCOMH-VCI）/ Deltat的充电电流。因此，Icha1消耗的功率是参考电压VCIxIcha1，Icha2消耗的功率是VCIxIcha 2×2。同时，从第一电压VCOMH向第二电压VCOML放电时的放电电流是从第一电压VCOMH到地电位GND的放电电流Idis 1 = Cp（VCOMH-GND）/ Deltat，和从地电位GND到第二电压VCOML的放电电流Idis 2 = Cp（GND-VCOML）/ Deltat。现在，如果以参考电压VCI消耗的功率转换，由于Idis 1表示放电到GND，因此功耗为零。然后，由于从地电位GND到第二电压VCOML，Idis2的放电电流的消耗功率为VCIxIdis 2。

57. 发明申请

US20070171182A1 Light control circuit and a liquid-crystal-display control drive device 失效
标题翻译：光控制电路和液晶显示控制驱动装置
公开(公告)号：US20070171182A1
公开(公告)日：2007-07-26
申请号：US11638534
申请日：2006-12-14
申请人： Toshio Mizuno , Takesada Akiba , Kazuo Okado
发明人： Toshio Mizuno , Takesada Akiba , Kazuo Okado
IPC分类号： G09G3/36
CPC分类号： G09G3/3406 , G09G2320/0633 , G09G2360/144
摘要： A light control circuit that makes it possible to, when the light intensity of the area surrounding a display screen varies in a relatively short time, prevent the brightness of a backlight from being erroneously adjusted as the result of the variation being detected is provided. The light control circuit controls the backlight of a display panel. This light control circuit is provided with functions of performing the following operation: detection signals from multiple optical sensors are taken into a common sampling means in a time division manner to acquire multiple sampling values temporally dispersed; a surrounding light intensity is determined by majority decision based on the multiple sampling values, and the result of determination is externally outputted.
摘要翻译：一种光控制电路，其能够在显示画面周围的区域的光强度在相当短的时间内变化的情况下，防止由于检测到的变化而导致背光源的亮度被错误调整。光控制电路控制显示面板的背光。该光控制电路具有执行以下操作的功能：以时分方式将来自多个光学传感器的检测信号作为公共采样装置，以获取时间上分散的多个采样值; 通过基于多个采样值的多数决定来确定周围光强度，并且从外部输出确定结果。

58. 发明授权

US07088636B2 Semiconductor memory circuit 有权
公开(公告)号：US07088636B2
公开(公告)日：2006-08-08
申请号：US11174604
申请日：2005-07-06
申请人： Takesada Akiba , Shigeki Ueda , Toshikazu Tachibana , Masashi Horiguchi
发明人： Takesada Akiba , Shigeki Ueda , Toshikazu Tachibana , Masashi Horiguchi
IPC分类号： G11C8/00
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

59. 发明申请

US20060132417A1 Semiconductor integrated circuit for liquid crystal display driver 审中-公开
标题翻译：半导体集成电路用于液晶显示驱动
公开(公告)号：US20060132417A1
公开(公告)日：2006-06-22
申请号：US11311161
申请日：2005-12-20
申请人： Takeshi Shigenobu , Mitsuru Hiraki , Masashi Horiguchi , Kazuo Okado , Takesada Akiba
发明人： Takeshi Shigenobu , Mitsuru Hiraki , Masashi Horiguchi , Kazuo Okado , Takesada Akiba
IPC分类号： G09G3/36
CPC分类号： G09G3/3696 , G09G3/3674 , G09G3/3685
摘要： In a liquid crystal drive controller formed as a semiconductor integrated circuit having therein a power source circuit including a boosting circuit and driving a source line and a gate line of a TFT liquid crystal panel, the number of external capacitive elements and the number of external terminals for connecting the external capacitive elements are reduced, thereby reducing the size and cost of the chip and an electronic device on which the chip is mounted. As a boosting circuit for generating a voltage for driving a source line of the TFT liquid crystal panel in the liquid crystal controller having therein the power source including the boosting circuit, a boosting circuit having an external capacitive element is used. On the other hand, as a boosting circuit for generating a voltage for driving a gate line, a charge pump having a built-in (on-chip) capacitive element is used.
摘要翻译：在形成为半导体集成电路的液晶驱动控制器中，其中具有包括升压电路并驱动TFT液晶面板的源极线和栅极线的电源电路，外部电容元件的数量和外部端子的数量用于连接外部电容元件的功能减小，从而减小芯片的尺寸和成本以及安装芯片的电子设备。作为用于在其中具有包括升压电路的电源的液晶控制器中产生用于驱动TFT液晶面板的源极线的电压的升压电路，使用具有外部电容元件的升压电路。另一方面，作为用于产生用于驱动栅极线的电压的升压电路，使用具有内置（片上）电容元件的电荷泵。

60. 发明申请

US20050243631A1 Semiconductor memory circuit 有权
标题翻译：半导体存储电路
公开(公告)号：US20050243631A1
公开(公告)日：2005-11-03
申请号：US11174604
申请日：2005-07-06
申请人： Takesada Akiba , Shigeki Ueda , Toshikazu Tachibana , Masashi Horiguchi
发明人： Takesada Akiba , Shigeki Ueda , Toshikazu Tachibana , Masashi Horiguchi
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/4074 , G11C11/409 , G11C29/08 , G11C7/00
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
摘要翻译：本发明提供了一种半导体存储器电路，其能够在配备有共享使用电源，地址信号和数据总线的多个芯片的系统中减少非操作时的电流消耗。半导体存储器电路具有内部电路，其能够选择性地通过开关装置执行工作电压的供应和停止，并且包括存储器阵列。在其中接收预定控制信号的输入电路通过开关装置控制供电和停止工作电压，以便在不进行存储器操作时减小直流电流和泄漏电流，由此可以实现低功耗。

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