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51. 发明授权

US08395103B2 Avalanche impact ionization amplification devices 有权
标题翻译：雪崩冲击电离放大装置
公开(公告)号：US08395103B2
公开(公告)日：2013-03-12
申请号：US13455507
申请日：2012-04-25
申请人： Solomon Assefa , Yurii A. Vlasov , Fengnian Xia
发明人： Solomon Assefa , Yurii A. Vlasov , Fengnian Xia
IPC分类号： H01L31/00 , H01L31/107
CPC分类号： H01L31/107 , H01L31/022408 , H01L31/02327 , H01L31/03529 , Y02E10/50
摘要： A semiconductor photodetector may provide charge carrier avalanche multiplication at high field regions of a semiconductor material layer. A semiconductor current amplifier may provide current amplification by impact ionization near a high field region. A plurality of metal electrodes are formed on a surface of a semiconductor material layer and electrically biased to produce a non-uniform high electric field in which the high electric field strength accelerates avalanche electron-hole pair generation, which is employed as an effective avalanche multiplication photodetection mechanism or as an avalanche impact ionization current amplification mechanism.
摘要翻译：半导体光电探测器可以在半导体材料层的高场区域提供电荷载体雪崩倍增。半导体电流放大器可以通过在高场区域附近的冲击电离提供电流放大。多个金属电极形成在半导体材料层的表面上并被电偏置以产生不均匀的高电场，其中高电场强度加速雪崩电子 - 空穴对产生，其被用作有效的雪崩倍增光电检测机制或雪崩冲击电离电流放大机制。

52. 发明申请

US20120326012A1 AVALANCHE IMPACT IONIZATION AMPLIFICATION DEVICES 有权
公开(公告)号：US20120326012A1
公开(公告)日：2012-12-27
申请号：US13603567
申请日：2012-09-05
申请人： Solomon Assefa , Yurii A. Vlasov , Fengnian Xia
发明人： Solomon Assefa , Yurii A. Vlasov , Fengnian Xia
IPC分类号： H01L31/107 , H03K17/06
CPC分类号： H01L31/107 , H01L31/022408 , H01L31/02327 , H01L31/03529 , Y02E10/50
摘要： A semiconductor photodetector may provide charge carrier avalanche multiplication at high field regions of a semiconductor material layer. A semiconductor current amplifier may provide current amplification by impact ionization near a high field region. A plurality of metal electrodes are formed on a surface of a semiconductor material layer and electrically biased to produce a non-uniform high electric field in which the high electric field strength accelerates avalanche electron-hole pair generation, which is employed as an effective avalanche multiplication photodetection mechanism or as an avalanche impact ionization current amplification mechanism.

53. 发明授权

US08232516B2 Avalanche impact ionization amplification devices 有权
标题翻译：雪崩冲击电离放大装置
公开(公告)号：US08232516B2
公开(公告)日：2012-07-31
申请号：US12533521
申请日：2009-07-31
申请人： Solomon Assefa , Yurii A. Vlasov , Fengnian Xia
发明人： Solomon Assefa , Yurii A. Vlasov , Fengnian Xia
IPC分类号： H01L31/00 , H01L31/107
CPC分类号： H01L31/107 , H01L31/022408 , H01L31/02327 , H01L31/03529 , Y02E10/50
摘要： A semiconductor photodetector may provide charge carrier avalanche multiplication at high field regions of a semiconductor material layer. A semiconductor current amplifier may provide current amplification by impact ionization near a high field region. A plurality of metal electrodes are formed on a surface of a semiconductor material layer and electrically biased to produce a non-uniform high electric field in which the high electric field strength accelerates avalanche electron-hole pair generation, which is employed as an effective avalanche multiplication photodetection mechanism or as an avalanche impact ionization current amplification mechanism.
摘要翻译：半导体光电探测器可以在半导体材料层的高场区域提供电荷载体雪崩倍增。半导体电流放大器可以通过在高场区域附近的冲击电离提供电流放大。多个金属电极形成在半导体材料层的表面上并被电偏置以产生不均匀的高电场，其中高电场强度加速雪崩电子 - 空穴对产生，其被用作有效的雪崩倍增光电检测机制或雪崩冲击电离电流放大机制。

54. 发明授权

US08098968B2 Silicide thermal heaters for silicon-on-insulator nanophotonic devices 失效
标题翻译：用于绝缘体上硅纳米光电器件的硅化物热加热器
公开(公告)号：US08098968B2
公开(公告)日：2012-01-17
申请号：US11849591
申请日：2007-09-04
申请人： William Michael John Green , Hendrik F. Hamann , Yurii A. Vlasov
发明人： William Michael John Green , Hendrik F. Hamann , Yurii A. Vlasov
IPC分类号： G02B6/12 , G02F1/01
CPC分类号： G02B6/125 , B82Y20/00 , G02B2006/12145 , G02B2006/12147 , G02F1/0147 , G02F1/025
摘要： A thermally switched Silicon-On-Insulator (SOI) photo electronic device includes a silicon layer including an optical waveguide and a silicide heating element horizontally adjacent to the waveguide. The waveguide has a refractive index that changes with heat applied to the waveguide.
摘要翻译：热开关绝缘体上硅（SOI）光电子器件包括包含光波导的硅层和与波导水平相邻的硅化物加热元件。波导具有随着施加到波导的热而变化的折射率。

55. 发明申请

US20110052200A1 MULTI-MODE MULTIPLEXING USING STAGED COUPLING AND QUASI-PHASE-MATCHING 有权
标题翻译：使用分层耦合和准相位匹配的多模式多路复用
公开(公告)号：US20110052200A1
公开(公告)日：2011-03-03
申请号：US12552387
申请日：2009-09-02
申请人： Saeed Bagheri , Wiliam M. Green , Petar Pepeljugoski , Yurii A. Vlasov
发明人： Saeed Bagheri , Wiliam M. Green , Petar Pepeljugoski , Yurii A. Vlasov
IPC分类号： H04J14/02
CPC分类号： G02B6/12007 , G02B6/125 , G02B6/14 , G02B6/3596 , H04J14/0201
摘要： A mode-selective add/drop unit for a mode division de/multiplexing device includes an optical ADU waveguide adapted for coupling to an input optical waveguide. The optical ADU waveguide includes at least one region providing optical signal coupling between the ADU waveguide and a multi-mode waveguide; and, one or more phase matching regions for controlling a relative or absolute phase difference between an electromagnetic wave (EMW) carried in the ADU waveguide and the multi-mode waveguide. The mode-selective add/drop unit may further include a transition region connecting the coupling region and a phase matching region, wherein a shape of a transition region is governed by a polynomial function, exponential function, logarithmic function, trigonometric function or, any combination of these functions.
摘要翻译：用于模式分频去/多路复用装置的模式选择性分插单元包括适于耦合到输入光波导的光学ADU波导。光学ADU波导包括提供ADU波导和多模波导之间的光信号耦合的至少一个区域; 以及用于控制ADU波导中携载的电磁波（EMW）和多模波导之间的相对或绝对相位差的一个或多个相位匹配区域。模式选择性分插单元还可以包括连接耦合区域和相位匹配区域的过渡区域，其中过渡区域的形状由多项式函数，指数函数，对数函数，三角函数或任何组合的这些功能。

56. 发明授权

US07897428B2 Three-dimensional integrated circuits and techniques for fabrication thereof 有权
标题翻译：三维集成电路及其制造技术
公开(公告)号：US07897428B2
公开(公告)日：2011-03-01
申请号：US12131988
申请日：2008-06-03
申请人： Solomon Assefa , Kuan-Neng Chen , Steven J. Koester , Yurii A. Vlasov
发明人： Solomon Assefa , Kuan-Neng Chen , Steven J. Koester , Yurii A. Vlasov
IPC分类号： H01L27/12
CPC分类号： H01L27/0688 , H01L25/167 , H01L27/144 , H01L2224/83894 , H01L2224/9202 , H01L2224/9212 , H01L2224/80896 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.
摘要翻译：提供了具有互补金属氧化物半导体（CMOS）的集成电路和用于其三维集成的光子电路和技术。一方面，三维集成电路包括底部器件层和顶部器件层。底部器件层包括衬底; 与衬底相邻的数字CMOS电路层; 以及与数字CMOS电路层的与衬底相对的一侧相邻的第一结合氧化物层。顶部器件层包括形成在具有大于或等于约0.5微米厚度的掩埋氧化物（BOX）的绝缘体上硅（SOI）层中的模拟CMOS和光子电路层; 以及与模拟CMOS和光子电路层相邻的第二键合氧化物层。底部器件层通过第一接合氧化物层和第二接合氧化物层之间的氧化物 - 氧化物键接合到顶部器件层。

57. 发明申请

US20090297091A1 Techniques for Three-Dimensional Circuit Integration 有权
标题翻译：三维电路集成技术
公开(公告)号：US20090297091A1
公开(公告)日：2009-12-03
申请号：US12132029
申请日：2008-06-03
申请人： Solomon Assefa , Kuan-Neng Chen , Steven J. Koester , Yurii A. Vlasov
发明人： Solomon Assefa , Kuan-Neng Chen , Steven J. Koester , Yurii A. Vlasov
IPC分类号： G02B6/12 , H01L21/84 , H01L27/12
CPC分类号： H01L27/0688
摘要： Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.
摘要翻译：提供了具有互补金属氧化物半导体（CMOS）的集成电路和用于其三维集成的光子电路和技术。一方面，一种三维集成电路包括底部器件层和顶部器件层。底部器件层包括数字CMOS电路层; 以及与数字CMOS电路层相邻的第一结合氧化物层。顶部器件层包括衬底; 形成在与衬底相邻的绝缘体上硅（SOI）层中的模拟CMOS和光子电路层，所述SOI层具有厚度大于或等于约1微米的掩埋氧化物（BOX）; 以及与模拟CMOS和与衬底相对的光子电路层的一侧相邻的第二结合氧化物层。底部器件层通过第一接合氧化物层和第二接合氧化物层之间的氧化物 - 氧化物键接合到顶部器件层。

58. 发明申请

US20090294814A1 Three-Dimensional Integrated Circuits and Techniques for Fabrication Thereof 有权
标题翻译：三维集成电路及其制造技术
公开(公告)号：US20090294814A1
公开(公告)日：2009-12-03
申请号：US12131988
申请日：2008-06-03
申请人： Solomon Assefa , Kuan-Neng Chen , Steven J. Koester , Yurii A. Vlasov
发明人： Solomon Assefa , Kuan-Neng Chen , Steven J. Koester , Yurii A. Vlasov
IPC分类号： H01L31/00 , H01L21/00
CPC分类号： H01L27/0688 , H01L25/167 , H01L27/144 , H01L2224/83894 , H01L2224/9202 , H01L2224/9212 , H01L2224/80896 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.
摘要翻译：提供了具有互补金属氧化物半导体（CMOS）的集成电路和用于其三维集成的光子电路和技术。一方面，三维集成电路包括底部器件层和顶部器件层。底部器件层包括衬底; 与衬底相邻的数字CMOS电路层; 以及与数字CMOS电路层的与衬底相对的一侧相邻的第一结合氧化物层。顶部器件层包括形成在具有大于或等于约0.5微米厚度的掩埋氧化物（BOX）的绝缘体上硅（SOI）层中的模拟CMOS和光子电路层; 以及与模拟CMOS和光子电路层相邻的第二结合氧化物层。底部器件层通过第一接合氧化物层和第二接合氧化物层之间的氧化物 - 氧化物键接合到顶部器件层。

59. 发明授权

US07536069B2 Method and apparatus for resonant coupling in photonic crystal circuits 失效
标题翻译：光子晶体谐振耦合的方法和装置
公开(公告)号：US07536069B2
公开(公告)日：2009-05-19
申请号：US11743454
申请日：2007-05-02
申请人： Sharee J. McNab , Yurii A. Vlasov
发明人： Sharee J. McNab , Yurii A. Vlasov
IPC分类号： G02B6/12 , G02B6/26 , G02B6/10
CPC分类号： B82Y20/00 , G02B6/1225
摘要： The present invention is a method and an apparatus for resonant coupling in photonic crystal circuits. In one embodiment, a photonic crystal device comprises a substrate having a plurality of apertures formed therethrough, a photonic crystal circuit (e.g., formed by “removing” a series of apertures), and a strip waveguide extending through the apertures and coupled to the photonic crystal circuit via a surface localized photonic state formed at a surface of the photonic crystal (e.g., in the apertures). The surface localized photonic state facilitates the efficient resonant tunneling of photons from the wavelength-independent strip waveguide to the wavelength-selective photonic crystal circuit, thereby improving the filtering capabilities of the photonic crystal device.
摘要翻译：本发明是一种用于光子晶体谐振耦合的方法和装置。在一个实施例中，光子晶体器件包括具有穿过其形成的多个孔的衬底，光子晶体电路（例如，通过“去除”一系列孔）形成的）以及延伸穿过孔并且耦合到光子通过形成在光子晶体的表面（例如，在孔中）的表面局部光子态的晶体电路。表面局部光子态有助于从波长无关条形波导到波长选择性光子晶体电路的光子的有效谐振隧穿，从而提高光子晶体器件的滤波能力。

60. 发明申请

US20090108384A1 Optoelectronic Device with Germanium Photodetector 有权
标题翻译：具有锗光电检测器的光电器件
公开(公告)号：US20090108384A1
公开(公告)日：2009-04-30
申请号：US11925170
申请日：2007-10-26
申请人： Solomon Assefa , Stephen Walter Bedell , Yurii A. Vlasov , Fengnian Xia
发明人： Solomon Assefa , Stephen Walter Bedell , Yurii A. Vlasov , Fengnian Xia
IPC分类号： H01L31/028 , H01L31/18
CPC分类号： H01L31/1808 , G02B6/12004 , H01L31/02327 , H01L31/105 , H01L31/1812 , Y02E10/50
摘要： An optoelectronic device comprises a photodetector feature, an interfacial layer disposed above at least a portion of the photodetector feature, and a vertical contact disposed on at least a portion of the interfacial layer. The photodetector feature comprises germanium and is operative to convert a light signal into an electrical signal. The interfacial layer comprises nickel. Finally, the vertical contact is operative to transmit the electrical signal from the photodetector feature.
摘要翻译：光电子器件包括光电检测器特征，设置在光电检测器特征的至少一部分上方的界面层，以及设置在界面层的至少一部分上的垂直接触。光电检测器特征包括锗并且可操作以将光信号转换成电信号。界面层包括镍。最后，垂直接触可操作地从光电检测器特征传输电信号。

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