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51. 发明申请

US20110087860A1 PARALLEL DATA PROCESSING SYSTEMS AND METHODS USING COOPERATIVE THREAD ARRAYS 有权
标题翻译：并行数据处理系统和使用合作螺纹阵列的方法
公开(公告)号：US20110087860A1
公开(公告)日：2011-04-14
申请号：US12972361
申请日：2010-12-17
申请人： John R. Nickolls , Stephen D. Lew
发明人： John R. Nickolls , Stephen D. Lew
IPC分类号： G06F15/16
CPC分类号： G06F9/544 , G06F9/3851 , G06F9/3887 , G06F9/522
摘要： Parallel data processing systems and methods use cooperative thread arrays (CTAs), i.e., groups of multiple threads that concurrently execute the same program on an input data set to produce an output data set. Each thread in a CTA has a unique identifier (thread ID) that can be assigned at thread launch time. The thread ID controls various aspects of the thread's processing behavior such as the portion of the input data set to be processed by each thread, the portion of an output data set to be produced by each thread, and/or sharing of intermediate results among threads. Mechanisms for loading and launching CTAs in a representative processing core and for synchronizing threads within a CTA are also described.
摘要翻译：并行数据处理系统和方法使用协同线程数组（CIA），即在输入数据集上同时执行相同程序的多线程组，以产生输出数据集。 CTA中的每个线程都有一个唯一的标识符（线程ID），可以在线程启动时分配。线程ID控制线程的处理行为的各个方面，例如由每个线程处理的输入数据集的部分，由每个线程产生的输出数据集的部分和/或线程之间的中间结果的共享。还描述了在代表性处理核心中加载和启动CTA并在CTA内同步线程的机制。

52. 发明授权

US07865894B1 Distributing processing tasks within a processor 有权
标题翻译：在处理器中分配处理任务
公开(公告)号：US07865894B1
公开(公告)日：2011-01-04
申请号：US11311997
申请日：2005-12-19
申请人： Bryon S. Nordquist , John R. Nickolls
发明人： Bryon S. Nordquist , John R. Nickolls
IPC分类号： G06F9/46
CPC分类号： G06F9/5044
摘要： Embodiments of the present invention facilitate distributing processing tasks within a processor. In one embodiment, processing clusters keep track of resource requirements. If sufficient resources are available within a particular processing cluster, the available processing cluster asserts a ready signal to a dispatch unit. The dispatch unit is configured to pass a processing task (such as a cooperative thread array or CTA) to an available processing cluster that asserted a ready signal. In another embodiment, a processing task is passed around a ring of processing clusters until a processing cluster with sufficient resources available accepts the processing task.
摘要翻译：本发明的实施例便于在处理器内分发处理任务。在一个实施例中，处理集群跟踪资源需求。如果在特定处理集群内有足够的资源可用，则可用的处理集群将向就绪信号发出准备好的信号。调度单元被配置为将处理任务（诸如协作线程数组或CTA）传递到断言就绪信号的可用处理簇。在另一个实施例中，处理任务围绕处理集群环传递，直到具有足够资源的处理集群接受处理任务为止。

53. 发明申请

US20080184211A1 VIRTUAL ARCHITECTURE AND INSTRUCTION SET FOR PARALLEL THREAD COMPUTING 有权
标题翻译：虚拟架构和平行线程计算的指令集
公开(公告)号：US20080184211A1
公开(公告)日：2008-07-31
申请号：US11627892
申请日：2007-01-26
申请人： John R. Nickolls , Henry P. Moreton , Lars S. Nyland , Ian A. Buck , Richard C. Johnson , Robert S. Glanville , Jayant B. Kolhe
发明人： John R. Nickolls , Henry P. Moreton , Lars S. Nyland , Ian A. Buck , Richard C. Johnson , Robert S. Glanville , Jayant B. Kolhe
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A virtual architecture and instruction set support explicit parallel-thread computing. The virtual architecture defines a virtual processor that supports concurrent execution of multiple virtual threads with multiple levels of data sharing and coordination (e.g., synchronization) between different virtual threads, as well as a virtual execution driver that controls the virtual processor. A virtual instruction set architecture for the virtual processor is used to define behavior of a virtual thread and includes instructions related to parallel thread behavior, e.g., data sharing and synchronization. Using the virtual platform, programmers can develop application programs in which virtual threads execute concurrently to process data; virtual translators and drivers adapt the application code to particular hardware on which it is to execute, transparently to the programmer.
摘要翻译：虚拟架构和指令集支持显式并行线程计算。虚拟架构定义了支持多个虚拟线程的并行执行的虚拟处理器，该多个虚拟线程具有不同虚拟线程之间的多级数据共享和协调（例如，同步），以及控制虚拟处理器的虚拟执行驱动器。用于虚拟处理器的虚拟指令集架构用于定义虚拟线程的行为，并且包括与并行线程行为相关的指令，例如数据共享和同步。使用虚拟平台，程序员可以开发虚拟线程同时执行以处理数据的应用程序; 虚拟翻译器和驱动程序将应用程序代码调整到要执行的特定硬件，对程序员是透明的。

54. 发明授权

US07339592B2 Simulating multiported memories using lower port count memories 有权
标题翻译：使用较低端口数存储器模拟多端口存储器
公开(公告)号：US07339592B2
公开(公告)日：2008-03-04
申请号：US10889730
申请日：2004-07-13
申请人： John Erik Lindholm , Ming Y. Siu , Simon S. Moy , Samuel Liu , John R. Nickolls
发明人： John Erik Lindholm , Ming Y. Siu , Simon S. Moy , Samuel Liu , John R. Nickolls
IPC分类号： G06F12/02 , G06F13/00 , G09G5/36
CPC分类号： G06F9/3012 , G06F9/30123 , G06F9/30167 , G06F9/3824 , G06F9/3851 , G06F9/3885
摘要： An apparatus and method for simulating a multiported memory using lower port count memories as banks. A portion of memory is allocated for storing data associated with a thread. The portion of memory allocated to a thread may be stored in a single bank or in multiple banks. A collector unit coupled to each bank gathers source operands needed to process a program instruction as the source operands output from one or more banks. The collector unit outputs the source operands to an execution unit when all of the source operands needed to process the program instruction have been gathered.
摘要翻译：一种使用较低端口计数存储器作为存储体来模拟多端口存储器的装置和方法。分配存储器的一部分用于存储与线程相关联的数据。分配给线程的内存部分可以存储在单个银行或多个银行中。耦合到每个组的收集器单元收集处理程序指令所需的源操作数，作为从一个或多个存储体输出的源操作数。当处理程序指令所需的所有源操作数已经被收集时，收集器单元将源操作数输出到执行单元。

55. 发明授权

US5542074A Parallel processor system with highly flexible local control capability, including selective inversion of instruction signal and control of bit shift amount 失效
标题翻译：并行处理器系统具有高度灵活的本地控制能力，包括指令信号的选择性反转和位移量的控制
公开(公告)号：US5542074A
公开(公告)日：1996-07-30
申请号：US965938
申请日：1992-10-22
申请人： Won S. Kim , John R. Nickolls
发明人： Won S. Kim , John R. Nickolls
IPC分类号： G06F15/80 , G06F15/76
CPC分类号： G06F9/3885 , G06F15/8015 , G06F9/3887
摘要： A parallel processor system which operates in a single-instruction multiple-data mode has a highly flexible local control capability for enabling the system to operate fast. The system contains an array of processing elements or PEs (12.sub.1 -12.sub.N) that process respective sets of data according to instructions supplied from a global control unit (20). Each instruction is furnished simultaneously to all the PEs. One local control feature (52) entails selectively inverting certain instruction signals according to a data-dependent signal. Another local control feature (48) involves controlling the amount of a bit shift in a barrel shifter (98) according to a data-dependent signal.
摘要翻译：以单指令多数据模式运行的并行处理器系统具有高度灵活的本地控制能力，使系统能够快速运行。该系统包含一系列处理元件或PE（121-12N），根据从全局控制单元（20）提供的指令处理相应的数据集。每个指令同时提供给所有的PE。一个本地控制特征（52）需要根据数据相关信号选择性地反转某些指令信号。另一个本地控制特征（48）涉及根据数据相关信号来控制桶形移位器（98）中的位移的量。

56. 发明授权

US08615541B2 Extended-precision integer arithmetic and logical instructions 有权
标题翻译：扩展精度整数算术和逻辑指令
公开(公告)号：US08615541B2
公开(公告)日：2013-12-24
申请号：US12889354
申请日：2010-09-23
申请人： Richard Craig Johnson , John R. Nickolls
发明人： Richard Craig Johnson , John R. Nickolls
IPC分类号： G06F7/38
CPC分类号： G06F7/38 , G06F9/30014 , G06F9/30021 , G06F9/30094 , G06F9/30109 , G06F9/30112 , G06F9/30123 , G06F9/3013 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F9/3891 , G06F2207/382
摘要： The invention set forth herein describes a mechanism for efficiently performing extended precision operations on multi-word source operands. Corresponding data words of the source operands are processed together via each instruction of a cascading sequence of instructions. State information generated when each instruction is processed is stored in condition code flags. The state information is optionally used in the processing of subsequent instructions in the sequence and/or accumulated with previously set state information.
摘要翻译：这里阐述的发明描述了一种用于在多字源操作数上有效执行扩展精度操作的机制。源操作数的相应数据字通过级联指令序列的每条指令一起处理。每个指令被处理时产生的状态信息被存储在条件代码标志中。状态信息可选地用于处理序列中的后续指令和/或用先前设置的状态信息累积。

57. 发明授权

US08321849B2 Virtual architecture and instruction set for parallel thread computing 有权
标题翻译：虚拟架构和并行线程计算的指令集
公开(公告)号：US08321849B2
公开(公告)日：2012-11-27
申请号：US11627892
申请日：2007-01-26
申请人： John R. Nickolls , Henry P. Moreton , Lars S. Nyland , Ian A. Buck , Richard C. Johnson , Robert S. Glanville , Jayant B. Kolhe
发明人： John R. Nickolls , Henry P. Moreton , Lars S. Nyland , Ian A. Buck , Richard C. Johnson , Robert S. Glanville , Jayant B. Kolhe
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A virtual architecture and instruction set support explicit parallel-thread computing. The virtual architecture defines a virtual processor that supports concurrent execution of multiple virtual threads with multiple levels of data sharing and coordination (e.g., synchronization) between different virtual threads, as well as a virtual execution driver that controls the virtual processor. A virtual instruction set architecture for the virtual processor is used to define behavior of a virtual thread and includes instructions related to parallel thread behavior, e.g., data sharing and synchronization. Using the virtual platform, programmers can develop application programs in which virtual threads execute concurrently to process data; virtual translators and drivers adapt the application code to particular hardware on which it is to execute, transparently to the programmer.
摘要翻译：虚拟架构和指令集支持显式并行线程计算。虚拟架构定义了支持多个虚拟线程的并行执行的虚拟处理器，该多个虚拟线程具有不同虚拟线程之间的多级数据共享和协调（例如，同步），以及控制虚拟处理器的虚拟执行驱动器。用于虚拟处理器的虚拟指令集架构用于定义虚拟线程的行为，并且包括与并行线程行为相关的指令，例如数据共享和同步。使用虚拟平台，程序员可以开发虚拟线程同时执行以处理数据的应用程序; 虚拟翻译器和驱动程序将应用程序代码调整到要执行的特定硬件，对程序员是透明的。

58. 发明授权

US08214625B1 Systems and methods for voting among parallel threads 有权
公开(公告)号：US08214625B1
公开(公告)日：2012-07-03
申请号：US12324645
申请日：2008-11-26
申请人： John R. Nickolls , Lars Nyland , Peter C. Mills , Jeremy Sugerman , Timothy Foley , Brian Fahs , Michael Garland , David P. Luebke
发明人： John R. Nickolls , Lars Nyland , Peter C. Mills , Jeremy Sugerman , Timothy Foley , Brian Fahs , Michael Garland , David P. Luebke
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/30087 , G06F9/3009 , G06F9/3887
摘要： One embodiment of the present invention sets forth a technique for efficiently performing voting operations within a multi-threaded parallel-processing system. A group of related parallel program threads executes within a processor core together in parallel. A new instruction, called a “vote” instruction, is introduced that enables a parallel program thread to post an individual vote within the context of the group of related threads and to receive the result of the vote. In this fashion, the vote instruction advantageously reduces overhead associated with inter-thread communication, thereby improving overall system performance.

59. 发明申请

US20110078225A1 Extended-Precision Integer Arithmetic and Logical Instructions 有权
标题翻译：扩展精度整数算术和逻辑指令
公开(公告)号：US20110078225A1
公开(公告)日：2011-03-31
申请号：US12889354
申请日：2010-09-23
申请人： Richard Craig JOHNSON , John R. Nickolls
发明人： Richard Craig JOHNSON , John R. Nickolls
IPC分类号： G06F7/483
CPC分类号： G06F7/38 , G06F9/30014 , G06F9/30021 , G06F9/30094 , G06F9/30109 , G06F9/30112 , G06F9/30123 , G06F9/3013 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F9/3891 , G06F2207/382
摘要： The invention set forth herein describes a mechanism for efficiently performing extended precision operations on multi-word source operands. Corresponding data words of the source operands are processed together via each instruction of a cascading sequence of instructions. State information generated when each instruction is processed is stored in condition code flags. The state information is optionally used in the processing of subsequent instructions in the sequence and/or accumulated with previously set state information.
摘要翻译：这里阐述的发明描述了一种用于对多字源操作数有效执行扩展精度操作的机制。源操作数的相应数据字通过级联指令序列的每条指令一起处理。每个指令被处理时产生的状态信息被存储在条件代码标志中。状态信息可选地用于处理序列中的后续指令和/或用先前设置的状态信息累积。

60. 发明申请

US20110074802A1 Architecture and Instructions for Accessing Multi-Dimensional Formatted Surface Memory 有权
标题翻译：用于访问多维格式化表面存储器的体系结构和说明
公开(公告)号：US20110074802A1
公开(公告)日：2011-03-31
申请号：US12890171
申请日：2010-09-24
申请人： John R. Nickolls , Brian Fahs , Lars Nyland , John Erik Lindholm , Richard Craig Johnson
发明人： John R. Nickolls , Brian Fahs , Lars Nyland , John Erik Lindholm , Richard Craig Johnson
IPC分类号： G06F12/00
CPC分类号： G06T1/60
摘要： One embodiment of the present invention sets forth a technique for a program to access multi-dimensional formatted graphics surface memory. Multi-dimensional memory objects called “surfaces” stored in a user-specified data or pixel format and arranged in a graphics optimized layout are accessed by programs using surface instructions. A set of memory access instructions e.g., load, store, reduce, and atomic, referred to as surface instructions, may be used to access the surfaces. Coordinate bounds checking is performed with configurable clamping. Caching behavior may also be specified by the surface instructions. Data format conversion and packing to a specified storage format is supported for store, reduction, and atomic surface instructions. Data format conversion and unpacking from a specified storage format is supported for loads and atomic surface instructions.
摘要翻译：本发明的一个实施例提出了一种用于访问多维格式化图形表面存储器的程序的技术。称为“表面”的多维存储器对象以用户指定的数据或像素格式存储并以图形优化的布局布置，由使用表面指令的程序访问。可以使用一组存储器访问指令，例如加载，存储，减少和原子，称为表面指令，以访问表面。通过可配置的夹紧进行坐标界限检查。缓存行为也可以由表面指令指定。支持存储，缩小和原子表面指令的数据格式转换和打包到指定的存储格式。负载和原子表面指令支持从指定的存储格式进行数据格式转换和解包。

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