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1. 发明授权

US08615541B2 Extended-precision integer arithmetic and logical instructions 有权
标题翻译：扩展精度整数算术和逻辑指令
公开(公告)号：US08615541B2
公开(公告)日：2013-12-24
申请号：US12889354
申请日：2010-09-23
申请人： Richard Craig Johnson , John R. Nickolls
发明人： Richard Craig Johnson , John R. Nickolls
IPC分类号： G06F7/38
CPC分类号： G06F7/38 , G06F9/30014 , G06F9/30021 , G06F9/30094 , G06F9/30109 , G06F9/30112 , G06F9/30123 , G06F9/3013 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F9/3891 , G06F2207/382
摘要： The invention set forth herein describes a mechanism for efficiently performing extended precision operations on multi-word source operands. Corresponding data words of the source operands are processed together via each instruction of a cascading sequence of instructions. State information generated when each instruction is processed is stored in condition code flags. The state information is optionally used in the processing of subsequent instructions in the sequence and/or accumulated with previously set state information.
摘要翻译：这里阐述的发明描述了一种用于在多字源操作数上有效执行扩展精度操作的机制。源操作数的相应数据字通过级联指令序列的每条指令一起处理。每个指令被处理时产生的状态信息被存储在条件代码标志中。状态信息可选地用于处理序列中的后续指令和/或用先前设置的状态信息累积。

2. 发明申请

US20110078225A1 Extended-Precision Integer Arithmetic and Logical Instructions 有权
标题翻译：扩展精度整数算术和逻辑指令
公开(公告)号：US20110078225A1
公开(公告)日：2011-03-31
申请号：US12889354
申请日：2010-09-23
申请人： Richard Craig JOHNSON , John R. Nickolls
发明人： Richard Craig JOHNSON , John R. Nickolls
IPC分类号： G06F7/483
CPC分类号： G06F7/38 , G06F9/30014 , G06F9/30021 , G06F9/30094 , G06F9/30109 , G06F9/30112 , G06F9/30123 , G06F9/3013 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F9/3891 , G06F2207/382
摘要： The invention set forth herein describes a mechanism for efficiently performing extended precision operations on multi-word source operands. Corresponding data words of the source operands are processed together via each instruction of a cascading sequence of instructions. State information generated when each instruction is processed is stored in condition code flags. The state information is optionally used in the processing of subsequent instructions in the sequence and/or accumulated with previously set state information.
摘要翻译：这里阐述的发明描述了一种用于对多字源操作数有效执行扩展精度操作的机制。源操作数的相应数据字通过级联指令序列的每条指令一起处理。每个指令被处理时产生的状态信息被存储在条件代码标志中。状态信息可选地用于处理序列中的后续指令和/或用先前设置的状态信息累积。

3. 发明申请

US20110074802A1 Architecture and Instructions for Accessing Multi-Dimensional Formatted Surface Memory 有权
标题翻译：用于访问多维格式化表面存储器的体系结构和说明
公开(公告)号：US20110074802A1
公开(公告)日：2011-03-31
申请号：US12890171
申请日：2010-09-24
申请人： John R. Nickolls , Brian Fahs , Lars Nyland , John Erik Lindholm , Richard Craig Johnson
发明人： John R. Nickolls , Brian Fahs , Lars Nyland , John Erik Lindholm , Richard Craig Johnson
IPC分类号： G06F12/00
CPC分类号： G06T1/60
摘要： One embodiment of the present invention sets forth a technique for a program to access multi-dimensional formatted graphics surface memory. Multi-dimensional memory objects called “surfaces” stored in a user-specified data or pixel format and arranged in a graphics optimized layout are accessed by programs using surface instructions. A set of memory access instructions e.g., load, store, reduce, and atomic, referred to as surface instructions, may be used to access the surfaces. Coordinate bounds checking is performed with configurable clamping. Caching behavior may also be specified by the surface instructions. Data format conversion and packing to a specified storage format is supported for store, reduction, and atomic surface instructions. Data format conversion and unpacking from a specified storage format is supported for loads and atomic surface instructions.
摘要翻译：本发明的一个实施例提出了一种用于访问多维格式化图形表面存储器的程序的技术。称为“表面”的多维存储器对象以用户指定的数据或像素格式存储并以图形优化的布局布置，由使用表面指令的程序访问。可以使用一组存储器访问指令，例如加载，存储，减少和原子，称为表面指令，以访问表面。通过可配置的夹紧进行坐标界限检查。缓存行为也可以由表面指令指定。支持存储，缩小和原子表面指令的数据格式转换和打包到指定的存储格式。负载和原子表面指令支持从指定的存储格式进行数据格式转换和解包。

4. 发明授权

US09519947B2 Architecture and instructions for accessing multi-dimensional formatted surface memory 有权
标题翻译：用于访问多维格式化表面存储器的体系结构和指令
公开(公告)号：US09519947B2
公开(公告)日：2016-12-13
申请号：US12890171
申请日：2010-09-24
申请人： John R. Nickolls , Brian Fahs , Lars Nyland , John Erik Lindholm , Richard Craig Johnson
发明人： John R. Nickolls , Brian Fahs , Lars Nyland , John Erik Lindholm , Richard Craig Johnson
IPC分类号： G06F12/00 , G06T1/60
CPC分类号： G06T1/60
摘要： One embodiment of the present invention sets forth a technique for a program to access multi-dimensional formatted graphics surface memory. Multi-dimensional memory objects called “surfaces” stored in a user-specified data or pixel format and arranged in a graphics optimized layout are accessed by programs using surface instructions. A set of memory access instructions e.g., load, store, reduce, and atomic, referred to as surface instructions, may be used to access the surfaces. Coordinate bounds checking is performed with configurable clamping. Caching behavior may also be specified by the surface instructions. Data format conversion and packing to a specified storage format is supported for store, reduction, and atomic surface instructions. Data format conversion and unpacking from a specified storage format is supported for loads and atomic surface instructions.
摘要翻译：本发明的一个实施例提出了一种用于访问多维格式化图形表面存储器的程序的技术。称为“表面”的多维存储器对象以用户指定的数据或像素格式存储并以图形优化的布局布置，由使用表面指令的程序访问。可以使用一组存储器访问指令，例如加载，存储，减少和原子，称为表面指令，以访问表面。通过可配置的夹紧进行坐标界限检查。缓存行为也可以由表面指令指定。支持存储，缩小和原子表面指令的数据格式转换和打包到指定的存储格式。负载和原子表面指令支持从指定的存储格式进行数据格式转换和解包。

5. 发明申请

US20110078415A1 Efficient Predicated Execution For Parallel Processors 审中-公开
标题翻译：并行处理器的高效预测执行
公开(公告)号：US20110078415A1
公开(公告)日：2011-03-31
申请号：US12891629
申请日：2010-09-27
申请人： Richard Craig Johnson , John R. Nickolls , Robert Steven Glanville
发明人： Richard Craig Johnson , John R. Nickolls , Robert Steven Glanville
IPC分类号： G06F9/30 , G06F9/46
CPC分类号： G06F9/3851 , G06F9/30021 , G06F9/30029 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/30094 , G06F9/3012 , G06F9/3013 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： The invention set forth herein describes a mechanism for predicated execution of instructions within a parallel processor executing multiple threads or data lanes. Each thread or data lane executing within the parallel processor is associated with a predicate register that stores a set of 1-bit predicates. Each of these predicates can be set using different types of predicate-setting instructions, where each predicate setting instruction specifies one or more source operands, at least one operation to be performed on the source operands, and one or more destination predicates for storing the result of the operation. An instruction can be guarded by a predicate that may influence whether the instruction is executed for a particular thread or data lane or how the instruction is executed for a particular thread or data lane.
摘要翻译：本文阐述的发明描述了用于在执行多个线程或数据通道的并行处理器内预测执行指令的机制。在并行处理器内执行的每个线程或数据通道与存储一组1位谓词的谓词寄存器相关联。可以使用不同类型的谓词设置指令来设置这些谓词中的每一个，其中每个谓词设置指令指定一个或多个源操作数，要对源操作数执行的至少一个操作以及用于存储结果的一个或多个目标谓词的操作。指令可以由可能影响特定线程或数据通道执行指令的指令或如何针对特定线程或数据通道执行指令的谓词来保护。

6. 发明授权

US10360039B2 Predicted instruction execution in parallel processors with reduced per-thread state information including choosing a minimum or maximum of two operands based on a predicate value 有权
公开(公告)号：US10360039B2
公开(公告)日：2019-07-23
申请号：US12891629
申请日：2010-09-27
申请人： Richard Craig Johnson , John R. Nickolls , Robert Steven Glanville
发明人： Richard Craig Johnson , John R. Nickolls , Robert Steven Glanville
IPC分类号： G06F9/30 , G06F9/38
摘要： A mechanism for predicated execution of instructions within a parallel processor executing multiple threads or data lanes is disclosed. Each thread or data lane executing within the parallel processor is associated with a predicate register that stores a set of 1-bit predicates. Each of these predicates can be set using different types of predicate-setting instructions, where each predicate setting instruction specifies one or more source operands, at least one operation to be performed on the source operands, and one or more destination predicates for storing the result of the operation. An instruction can be guarded by a predicate that may influence whether the instruction is executed for a particular thread or data lane or how the instruction is executed for a particular thread or data lane.

7. 发明授权

US08677106B2 Unanimous branch instructions in a parallel thread processor 有权
标题翻译：并行线程处理器中一致的分支指令
公开(公告)号：US08677106B2
公开(公告)日：2014-03-18
申请号：US12815226
申请日：2010-06-14
申请人： John R. Nickolls , Richard Craig Johnson , Robert Steven Glanville , Guillermo Juan Rozas
发明人： John R. Nickolls , Richard Craig Johnson , Robert Steven Glanville , Guillermo Juan Rozas
IPC分类号： G06F9/32
CPC分类号： G06F9/30072 , G06F9/3851 , G06F9/3887
摘要： One embodiment of the present invention sets forth a mechanism for managing thread divergence in a thread group executing a multithreaded processor. A unanimous branch instruction, when executed, causes all the active threads in the thread group to branch only when each thread in the thread group agrees to take the branch. In such a manner, thread divergence is eliminated. A branch-any instruction, when executed, causes all the active threads in the thread group to branch when at least one thread in the thread group agrees to take the branch.
摘要翻译：本发明的一个实施例提出了一种用于管理执行多线程处理器的线程组中的线程发散的机制。一致的分支指令执行时，只有当线程组中的每个线程同意采用分支时，才能使线程组中的所有活动线程分支。以这种方式消除螺纹发散。分支 - 任何指令执行时，会导致线程组中的所有活动线程在线程组中的至少一个线程同意分支时分支。

8. 发明授权

US08615646B2 Unanimous branch instructions in a parallel thread processor 有权
标题翻译：并行线程处理器中一致的分支指令
公开(公告)号：US08615646B2
公开(公告)日：2013-12-24
申请号：US12815201
申请日：2010-06-14
申请人： John R. Nickolls , Richard Craig Johnson , Robert Steven Glanville , Guillermo Juan Rozas
发明人： John R. Nickolls , Richard Craig Johnson , Robert Steven Glanville , Guillermo Juan Rozas
IPC分类号： G06F9/32
CPC分类号： G06F9/30072 , G06F9/3851 , G06F9/3887
摘要： One embodiment of the present invention sets forth a mechanism for managing thread divergence in a thread group executing a multithreaded processor. A unanimous branch instruction, when executed, causes all the active threads in the thread group to branch only when each thread in the thread group agrees to take the branch. In such a manner, thread divergence is eliminated. A branch-any instruction, when executed, causes all the active threads in the thread group to branch when at least one thread in the thread group agrees to take the branch.
摘要翻译：本发明的一个实施例提出了一种用于管理执行多线程处理器的线程组中的线程发散的机制。一致的分支指令执行时，只有当线程组中的每个线程同意采用分支时，才能使线程组中的所有活动线程分支。以这种方式消除螺纹发散。分支 - 任何指令执行时，会导致线程组中的所有活动线程在线程组中的至少一个线程同意分支时分支。

9. 发明申请

US20110072249A1 UNANIMOUS BRANCH INSTRUCTIONS IN A PARALLEL THREAD PROCESSOR 有权
公开(公告)号：US20110072249A1
公开(公告)日：2011-03-24
申请号：US12815226
申请日：2010-06-14
申请人： John R. Nickolls , Richard Craig Johnson , Robert Steven Glanville , Guillermo Juan Rozas
发明人： John R. Nickolls , Richard Craig Johnson , Robert Steven Glanville , Guillermo Juan Rozas
IPC分类号： G06F9/38
CPC分类号： G06F9/30072 , G06F9/3851 , G06F9/3887
摘要： One embodiment of the present invention sets forth a mechanism for managing thread divergence in a thread group executing a multithreaded processor. A unanimous branch instruction, when executed, causes all the active threads in the thread group to branch only when each thread in the thread group agrees to take the branch. In such a manner, thread divergence is eliminated. A branch-any instruction, when executed, causes all the active threads in the thread group to branch when at least one thread in the thread group agrees to take the branch.

10. 发明授权

US09223578B2 Coalescing memory barrier operations across multiple parallel threads 有权
标题翻译：在多个并行线程之间合并记忆障碍操作
公开(公告)号：US09223578B2
公开(公告)日：2015-12-29
申请号：US12887081
申请日：2010-09-21
申请人： John R. Nickolls , Steven James Heinrich , Brett W. Coon , Michael C. Shebanow
发明人： John R. Nickolls , Steven James Heinrich , Brett W. Coon , Michael C. Shebanow
IPC分类号： G06F9/46 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30087 , G06F9/3851
摘要： One embodiment of the present invention sets forth a technique for coalescing memory barrier operations across multiple parallel threads. Memory barrier requests from a given parallel thread processing unit are coalesced to reduce the impact to the rest of the system. Additionally, memory barrier requests may specify a level of a set of threads with respect to which the memory transactions are committed. For example, a first type of memory barrier instruction may commit the memory transactions to a level of a set of cooperating threads that share an L1 (level one) cache. A second type of memory barrier instruction may commit the memory transactions to a level of a set of threads sharing a global memory. Finally, a third type of memory barrier instruction may commit the memory transactions to a system level of all threads sharing all system memories. The latency required to execute the memory barrier instruction varies based on the type of memory barrier instruction.
摘要翻译：本发明的一个实施例提出了一种用于在多个并行线程之间聚合存储器屏障操作的技术。来自给定并行线程处理单元的存储器屏障请求被合并以减少对系统其余部分的影响。此外，存储器屏障请求可以指定针对其提交内存事务的一组线程的级别。例如，第一类型的存储器障碍指令可以将存储器事务提交到共享L1（一级）高速缓存的一组协作线程的级别。第二种类型的存储器障碍指令可以将存储器事务提交到共享全局存储器的一组线程的级别。最后，第三种类型的存储器障碍指令可以将存储器事务提交到共享所有系统存储器的所有线程的系统级。执行存储器屏障指令所需的延迟基于存储器屏障指令的类型而变化。

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