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51. 发明申请

US20090189579A1 SWITCH STATE CONTROLLER WITH A SENSE CURRENT GENERATED OPERATING VOLTAGE 有权
标题翻译：开关状态控制器，具有感应电流产生的工作电压
公开(公告)号：US20090189579A1
公开(公告)日：2009-07-30
申请号：US12165556
申请日：2008-06-30
申请人： John L. Melanson , Karl Thompson , Kartik Nanda , Mauro Gaetano
发明人： John L. Melanson , Karl Thompson , Kartik Nanda , Mauro Gaetano
IPC分类号： H02M3/156
CPC分类号： H02J7/0054 , H02J2007/0059 , H02M3/33592 , Y02B40/90 , Y02B70/1475
摘要： A power supply system and method includes a switch state controller that is operational to control a switching power converter during certain power loss conditions that cause conventional switch state controllers to have diminished or no functionality. In at least one embodiment, during certain power loss conditions, such as when an auxiliary power supply is in standby mode or when the switching power converter is not operating, a power supply for the switch state controller does not provide sufficient operating power to the switch state controller during certain power loss conditions. In at least one embodiment, during such power loss conditions power is generated for the switch state controller using sense input and/or sense output currents of the switching power converter to allow an integrated circuit (IC) switch state controller to generate a control signal to control a switch of the switching power converter.
摘要翻译：电源系统和方法包括开关状态控制器，该开关状态控制器在导致常规开关状态控制器已经减小或没有功能的某些功率损耗条件下可操作以控制开关功率转换器。在至少一个实施例中，在某些功率损耗状态下，例如当辅助电源处于待机模式时或者当开关电源转换器不工作时，开关状态控制器的电源不能向开关提供足够的工作电力在某些功率损耗条件下状态控制器。在至少一个实施例中，在这种功率损耗状态期间，使用开关功率转换器的感测输入和/或感测输出电流为开关状态控制器产生功率，以允许集成电路（IC）开关状态控制器产生控制信号控制开关电源转换器的开关。

52. 发明申请

US20090147545A1 HISTORY-INDEPENDENT NOISE-IMMUNE MODULATED TRANSFORMER-COUPLED GATE CONTROL SIGNALING METHOD AND APPARATUS 有权
标题翻译：历史独立噪声调制变压器耦合门控信号方法与装置
公开(公告)号：US20090147545A1
公开(公告)日：2009-06-11
申请号：US12164217
申请日：2008-06-30
申请人： John L. Melanson
发明人： John L. Melanson
IPC分类号： H02M3/335
CPC分类号： H03K17/691 , H03K17/08128
摘要： A history-independent and noise-immune modulated transformer-coupled gate control signaling method and apparatus provides robust design characteristics in switching power circuits having a transformer-coupled gate drive. A modulated control signal at a rate substantially higher than the switching circuit gate control rate is provided from the controller circuit to a demodulator via transformer coupling. Codes specified by relative timing of transitions in multiple periods of the modulated control are assigned to gate-on and gate-off timing events that control the switching transistor gate(s) and unassigned patterns are decoded as gate-off events, reducing the possibility that a switching transistor will be erroneously activated due to noise. The modulated signal is constructed so that signal history is not required for decoding, eliminating any requirement of a reference clock. Blanking may be employed to conserve power between codes and to avoid mis-triggering due to noise events during power switching.
摘要翻译：具有历史无关和无噪声调制的变压器耦合门控信号方法和装置在具有变压器耦合栅极驱动的开关电源电路中提供鲁棒的设计特性。通过变压器耦合，从控制器电路向解调器提供基本上高于开关电路栅极控制速率的调制控制信号。通过调制控制的多个周期中的转换的相对定时指定的代码被分配给控制开关晶体管栅极和未分配模式的栅极导通和栅极截止定时事件被解码为栅极断开事件，从而降低了开关晶体管将由于噪声而被错误地激活。调制信号被构造成使得信号历史不需要用于解码，消除了参考时钟的任何要求。可以采用消隐来节省代码之间的功率，并且避免在功率切换期间由于噪声事件引起的误触发。

53. 发明申请

US20080272756A1 POWER FACTOR CORRECTION CONTROLLER WITH DIGITAL FIR FILTER OUTPUT VOLTAGE SAMPLING 审中-公开
标题翻译：功率因数校正控制器，带数字FIR滤波器输出电压采样
公开(公告)号：US20080272756A1
公开(公告)日：2008-11-06
申请号：US11967276
申请日：2007-12-31
申请人： John L. Melanson
发明人： John L. Melanson
IPC分类号： G05F1/10
CPC分类号： H02M1/4225 , H03M3/476 , Y02B70/126 , Y02P80/112
摘要： A power control system includes a digital FIR filter in an output voltage feedback loop of a switching power converter. A feedback loop includes an output voltage signal of the switching power converter. The output voltage signal includes direct current (DC) and alternating current (AC) components. The FIR filter provides discrete samples of an output voltage feedback signal to a switch state controller that allows the switch state controller to generate a control signal that reflects a relatively quick response to changes in the output voltage signal while reducing an influence of the AC component. In at least one embodiment, the FIR filter is configured to generate the discrete samples at a sampling frequency fs, the sampling frequency fs is approximately an integer multiple of a line frequency fL, and the line frequency fL is a frequency of a line input voltage supplied to the switching power converter.
摘要翻译：功率控制系统包括开关功率转换器的输出电压反馈回路中的数字FIR滤波器。反馈回路包括开关功率转换器的输出电压信号。输出电压信号包括直流（DC）和交流（AC）分量。 FIR滤波器提供输出电压反馈信号的离散采样到开关状态控制器，其允许开关状态控制器产生反映对输出电压信号的变化的相对快速响应的控制信号，同时减少AC分量的影响。在至少一个实施例中，FIR滤波器被配置为以采样频率f N s N生成离散样本，采样频率f S s大约是线的整数倍频率f L L，线路频率f L L是提供给开关功率转换器的线路输入电压的频率。

54. 发明申请

US20080272747A1 PROGRAMMABLE POWER CONTROL SYSTEM 有权
标题翻译：可编程功率控制系统
公开(公告)号：US20080272747A1
公开(公告)日：2008-11-06
申请号：US11967275
申请日：2007-12-31
申请人： John L. Melanson
发明人： John L. Melanson
IPC分类号： G05F1/70
CPC分类号： H02M1/4225 , H03M3/476 , Y02B70/126 , Y02P80/112
摘要： A power control system includes a switching power converter and a programmable power factor correction (PFC) and output voltage controller. The programmable PFC and output voltage controller generates a control signal to control power factor correction and voltage regulation of the switching power converter. In at least one embodiment, the control signal is a pulse width modulated signal. The programmability of the PFC and output voltage controller provides the programmable PFC and output voltage controller flexibility to operate in accordance with programmable parameters, to adapt to various operating environments, and to respond to various operating exigencies. In at least one embodiment, the programmable PFC and output voltage controller includes a state machine to process one or more programmable, operational parameters to determine the period and pulse width states of the control signal.
摘要翻译：功率控制系统包括开关功率转换器和可编程功率因数校正（PFC）和输出电压控制器。可编程PFC和输出电压控制器产生控制信号，以控制开关电源转换器的功率因数校正和电压调节。在至少一个实施例中，控制信号是脉宽调制信号。 PFC和输出电压控制器的可编程性使可编程PFC和输出电压控制器的灵活性能够根据可编程参数进行操作，以适应各种操作环境，并响应各种操作的紧急情况。在至少一个实施例中，可编程PFC和输出电压控制器包括处理一个或多个可编程的操作参数以确定控制信号的周期和脉冲宽度状态的状态机。

55. 发明授权

US07365669B1 Low-delay signal processing based on highly oversampled digital processing 有权
标题翻译：基于高度过采样数字处理的低延迟信号处理
公开(公告)号：US07365669B1
公开(公告)日：2008-04-29
申请号：US11692906
申请日：2007-03-28
申请人： John L. Melanson
发明人： John L. Melanson
IPC分类号： H03M3/00
CPC分类号： G10K11/178 , G10K2210/1081 , G10L21/0208 , H03M3/424 , H03M3/452 , H03M7/3024 , H03M7/3033 , H03M7/304 , H04R25/453
摘要： A low-delay signal processing system and method are provided which includes a delta-sigma analog-to-digital converter, an oversampling processor, and a delta-sigma digital-to-analog converter. The delta-sigma analog-to-digital converter receives an input or audio signal and generates a digital sample signal at a high oversampling rate. The oversampling processor is connected to the analog-to-digital converter for processing the digital sample signal at the high oversampling rate with low-delay. The delta-sigma digital-to-analog converter is connected to the oversampling processor for receiving the digital sample signal at the high oversampling rate with low-delay for generating an analog signal. The oversampling processor includes a low-delay filter and a programmable delay element. In this manner, the analog signal is produced with a low delay and high accuracy.
摘要翻译：提供了一种低延迟信号处理系统和方法，其包括Δ-Σ模数转换器，过采样处理器和Δ-Σ数模转换器。 Δ-Σ模数转换器接收输入或音频信号并以高过采样率产生数字采样信号。过采样处理器连接到模数转换器，以低延迟的高过采样速率处理数字采样信号。 Δ-Σ数模转换器连接到过采样处理器，用于以高过采样速率接收数字采样信号，具有低延迟以产生模拟信号。过采样处理器包括低延迟滤波器和可编程延迟元件。以这种方式，以低延迟和高精度产生模拟信号。

56. 发明授权

US07365667B1 Delta-sigma analog-to-digital converter (ADC) having an intermittent power-down state between conversion cycles 有权
标题翻译：在转换周期之间具有间歇掉电状态的Delta-sigma模数转换器（ADC）
公开(公告)号：US07365667B1
公开(公告)日：2008-04-29
申请号：US11534191
申请日：2006-09-21
申请人： Kartik Nanda , John L. Melanson
发明人： Kartik Nanda , John L. Melanson
IPC分类号： H03M3/00
CPC分类号： H03M3/32 , H03M3/43 , H03M3/452 , H03M3/474
摘要： A delta-sigma analog to digital converter (ADC) having an intermittent power down state between conversion cycles provides for power consumption savings when the converter is in a lower sample rate operating mode. Clocks provided to the digital portions of the converter are disabled, except for a periodic interval in which a conversion is performed at the higher selectable sample rate of the converter. The analog portions of the converter can also be disabled, but are re-enabled for a predetermined time period and reset before the digital clocks are enabled, so that the loop filter and feedback value supplied from the quantizer to the loop filter are stable prior to each conversion.
摘要翻译：在转换周期间具有间歇掉电状态的Δ-Σ模数转换器（ADC）提供了当转换器处于较低采样率操作模式时的功耗节省。提供给转换器的数字部分的时钟被禁用，除了在转换器的较高可选采样率下进行转换的周期性间隔之外。转换器的模拟部分也可以被禁用，但在预定的时间周期内重新使能并在数字时钟被使能之前复位，使得从量化器提供给环路滤波器的环路滤波器和反馈值在每次转换。

57. 发明授权

US07327295B1 Constant edge-rate ternary output consecutive-edge modulator (CEM) method and apparatus 有权
标题翻译：恒边缘三进制输出连续边缘调制器（CEM）方法和装置
公开(公告)号：US07327295B1
公开(公告)日：2008-02-05
申请号：US11343027
申请日：2006-01-30
申请人： Brian David Trotter , John L. Melanson
发明人： Brian David Trotter , John L. Melanson
IPC分类号： H03M3/00
CPC分类号： H03M1/822 , G06F1/025 , H03K7/08 , H03M3/506
摘要： A constant edge-rate ternary output consecutive-edge modulator (CEM) method and apparatus provides improved dynamic range in a noise-shaped CEM ternary pulse generator. A noise shaper shapes an input signal that is supplied to a pair of CEMs through a mismatch shaper or other code splitter that assigns unequal pulse width portions (the extra count in odd counts) between the pair of CEMs. The range of pulse width out of the CEMs can then be allowed to extend to the full sample period for one or possibly both of the CEMs in a given cycle. A control circuit overrides the mismatch shaper's assignment of the unequal pulse width portions when a previous pulse period yielded no transition from a given CEM, so that the given CEM is guaranteed to have a transition in the current pulse period.
摘要翻译：恒定边缘速率三进制输出连续边缘调制器（CEM）方法和装置在噪声形状的CEM三元脉冲发生器中提供改进的动态范围。噪声整形器通过错配整形器或其他代码分离器来形成输入信号，该输入信号通过在一对CEM之间分配不相等的脉冲宽度部分（奇数的额外计数）而被提供给一对CEM。然后可以允许CEM中的脉冲宽度范围延伸到给定周期中的一个或可能两个CEM的完整采样周期。当先前的脉冲周期不产生从给定的CEM的转变时，控制电路覆盖不匹配整形器对不等的脉冲宽度部分的分配，使得给定的CEM被保证在当前脉冲周期内具有转变。

58. 发明授权

US07224216B2 Segmented chopping amplifier 有权
标题翻译：分段斩波放大器
公开(公告)号：US07224216B2
公开(公告)日：2007-05-29
申请号：US11455592
申请日：2006-06-19
申请人： Karl Thompson , John L. Melanson , Chung-Kai Chow , Ammisetti V. Prasad
发明人： Karl Thompson , John L. Melanson , Chung-Kai Chow , Ammisetti V. Prasad
IPC分类号： H03F1/02
CPC分类号： H03F3/211 , H03F1/02 , H03F1/26 , H03F3/217 , H03F3/38 , H03F2200/331
摘要： A chopping amplifier and method for chopping an input signal are disclosed. The chopping amplifier and method utilize at least two chopping amplifier stages. A chopping operation of an input signal is segmented across two or more chopping amplifier stages, and the two or more chopping amplifier stages are responsive to a master controller. Chop clock signals of the chopping amplifier stages are staggered so that they have non-overlapping periods and at least one of the chopping amplifier stages is not operating in an open loop at any given time. The non-overlapping periods are periodic so that a master chop clock of the master controller can be operated at a lower chop clock frequency. For every doubling of N number of chopping amplifier stages, magnitudes of chopping artifacts and aliased components are each respectively reduced by 3 dB.
摘要翻译：公开了一种用于斩波输入信号的斩波放大器和方法。斩波放大器和方法利用至少两个斩波放大器级。输入信号的斩波操作跨越两个或更多个斩波放大器级分段，并且两个或更多个斩波放大器级对主控制器做出响应。斩波放大器级的斩波时钟信号交错，使得它们具有非重叠周期，并且至少一个斩波放大器级在任何给定时间都不在开环中工作。非重叠周期是周期性的，使得主控制器的主斩波时钟可以以较低的斩波时钟频率工作。对于N个斩波放大器级的每一倍，斩波伪影和混叠分量的大小分别降低3dB。

59. 发明授权

US07212137B2 Delta sigma modulator with integral decimation 有权
标题翻译：具有整数抽取的ΔΣ调制器
公开(公告)号：US07212137B2
公开(公告)日：2007-05-01
申请号：US10682552
申请日：2003-10-09
申请人： John L. Melanson
发明人： John L. Melanson
IPC分类号： H03M7/32
CPC分类号： H03M7/3015
摘要： A digital signal processing system utilizes an internal filter of a delta-sigma modulator in a novel manner to implement both the integration functions of the delta-sigma modulator and a decimation function. Using the internal filter to combine integration and decimation functions can eliminate the need for a separate decimation filter. The combination of integration and decimation functions can also improve signal-to-noise ratio by improving low-pass filtering performance.
摘要翻译：数字信号处理系统以新颖的方式利用Δ-Σ调制器的内部滤波器来实现Δ-Σ调制器的集成功能和抽取功能。使用内部滤波器组合集成和抽取功能可以消除对单独抽取滤波器的需要。集成和抽取功能的组合也可以通过改进低通滤波性能来提高信噪比。

60. 发明授权

US07167118B1 Centered-pulse consecutive edge modulation (CEM) method and apparatus 有权
标题翻译：中心脉冲连续边缘调制（CEM）方法和装置
公开(公告)号：US07167118B1
公开(公告)日：2007-01-23
申请号：US11297016
申请日：2005-12-08
申请人： John L. Melanson , Melvin L. Hagge , Brian David Trotter
发明人： John L. Melanson , Melvin L. Hagge , Brian David Trotter
IPC分类号： H03M3/00
CPC分类号： H03M3/506 , H03M7/3026 , H03M7/3037
摘要： A centered-pulse consecutive edge modulation (CEM) method and apparatus provides a pulse output that advantageously exploits the full edge update rate of the CEM while providing substantially centered pulses. The method and apparatus also operate without substantial delay in the input control path. The apparatus includes a delta-sigma noise shaping modulator followed by a CEM that receives an output of the delta-sigma modulator quantizer. A non-linear correction signal is applied with polarity alternating at each edge and is applied to the quantizer input or is designed into the quantizer transfer function. The non-linear correction signal compensates for the noise-shaping modulator output such that the expected rising edge and falling edge widths of the CEM output pulses are substantially equal with respect to a DC input to the delta-sigma modulator.
摘要翻译：中心脉冲连续边缘调制（CEM）方法和装置提供脉冲输出，其有利地利用CEM的全边缘更新速率，同时提供基本上居中的脉冲。该方法和装置也在输入控制路径中没有实质延迟的情况下工作。该装置包括后跟有CEM的Δ-Σ噪声整形调制器，其接收Δ-Σ调制器量化器的输出。在每个边缘处以极性交替施加非线性校正信号，并施加到量化器输入或被设计成量化器传递函数。非线性校正信号补偿噪声整形调制器输出，使得CEM输出脉冲的预期上升沿和下降沿宽度相对于Δ-Σ调制器的DC输入基本相等。

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