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51. 发明申请

US20110279819A1 ILLUMINATION SUBSYSTEMS OF A METROLOGY SYSTEM, METROLOGY SYSTEMS, AND METHODS FOR ILLUMINATING A SPECIMEN FOR METROLOGY MEASUREMENTS 有权
标题翻译：计量系统的照明子系统，计量系统和用于量化测量样本的方法
公开(公告)号：US20110279819A1
公开(公告)日：2011-11-17
申请号：US13061936
申请日：2009-09-29
申请人： Yung-Ho (Alex) Chuang , Vladimir Levinski , Xuefeng Liu
发明人： Yung-Ho (Alex) Chuang , Vladimir Levinski , Xuefeng Liu
IPC分类号： G02F1/03 , G01B11/00
CPC分类号： G01N21/9501 , G01N2021/479
摘要： Illumination subsystems of a metrology system, metrology systems, and methods for illuminating a specimen for metrology measurements are provided.
摘要翻译：提供了计量系统的照明子系统，计量系统和用于度量测量的照明样本的方法。

52. 发明授权

US07915158B2 Method for forming an on-chip high frequency electro-static discharge device 有权
标题翻译：用于形成片上高频静电放电装置的方法
公开(公告)号：US07915158B2
公开(公告)日：2011-03-29
申请号：US12144071
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/3148 , H01L21/318 , H01L21/3185 , H01L27/0248
摘要： A method for forming an on-chip high frequency electro-static discharge device is described. In one embodiment, a wafer with a multi-metal level wiring is provided. The wafer includes a first dielectric layer with more than one electrode formed therein, a second dielectric layer disposed over the first dielectric layer with more than one electrode formed therein and more than one via connecting the more than one electrode in the first dielectric layer to a respective more than one electrode in the second dielectric layer. The more than one via is misaligned a predetermined amount with the more than one electrodes in the first dielectric layer and the second dielectric layer. The at least one of the misaligned vias forms a narrow gap with another misaligned via. A cavity trench is formed through the second dielectric layer between the narrow gap that separates the misaligned vias.
摘要翻译：描述形成片上高频静电放电装置的方法。在一个实施例中，提供具有多金属层布线的晶片。该晶片包括：第一电介质层，其中形成有多于一个电极;第二电介质层，设置在第一电介质层上，其中形成有多于一个电极，多个通孔将第一介电层中的多于一个的电极连接到在第二介电层中分别有一个以上的电极。多于一个通孔与第一介电层和第二介电层中的多于一个的电极不对准预定量。至少一个不对齐的通孔与另一个不对齐的通孔形成了狭窄的间隙。在分隔未对准的通孔的窄间隙之间通过第二介电层形成腔沟槽。

53. 发明申请

US20090316313A1 DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 失效
标题翻译：片上高频电子放电装置的设计结构
公开(公告)号：US20090316313A1
公开(公告)日：2009-12-24
申请号：US12144084
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H02H9/00 , G06F17/50
CPC分类号： G06F17/5068 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge device comprises a substrate and multiple metal level layers disposed on the substrate. Each metal level comprises more than one electrode formed therein and more than one via connecting with some of the electrodes in adjacent metal levels. The device further includes a gap formed about one of the metal level layers, wherein the gap is hermetically sealed to provide electro-static discharge protection for the integrated circuit.
摘要翻译：描述了片上高频静电放电装置的设计结构。在一个实施例中，静电放电装置包括衬底和设置在衬底上的多个金属层。每个金属层包括多于一个电极，其中形成有多个电极，并且多个通孔与相邻金属层中的一些电极连接。所述装置还包括围绕所述金属层之一形成的间隙，其中所述间隙被气密密封以为所述集成电路提供静电放电保护。

54. 发明申请

US20080277769A1 Package Integrated Soft Magnetic Film for Improvement In On-Chip Inductor Performance 有权
标题翻译：封装集成软磁膜，用于片内电感性能的提高
公开(公告)号：US20080277769A1
公开(公告)日：2008-11-13
申请号：US11690682
申请日：2007-05-08
申请人： John Michael Cotte , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Nils D. Hoivik , Xuefeng Liu
发明人： John Michael Cotte , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Nils D. Hoivik , Xuefeng Liu
IPC分类号： H01L23/02 , H01L21/58
CPC分类号： H01L23/04 , H01L23/5227 , H01L23/552 , H01L23/645 , H01L24/16 , H01L24/29 , H01L24/32 , H01L2224/29101 , H01L2224/2919 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01068 , H01L2924/01075 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/19042 , H01L2924/19104 , H01L2924/19105 , H01L2924/30107 , H01L2924/00 , H01L2924/01026 , H01L2924/01028 , H01L2924/01042
摘要： An integrated circuit package includes an integrated circuit with one or more on-chip inductors. A package cover covers the integrated circuit. A magnetic material is provided between the integrated circuit and the package cover. The magnetic material may be a soft magnetic thin film. The magnetic material may be affixed to the package cover by an adhesive. The magnetic material may be formed directly on the package cover by one of deposition, sputtering or spraying. The magnetic material may be affixed to the integrated circuit.
摘要翻译：集成电路封装包括具有一个或多个片上电感器的集成电路。封装盖覆盖集成电路。在集成电路和封装盖之间提供磁性材料。磁性材料可以是软磁性薄膜。磁性材料可以通过粘合剂固定到包装盖上。磁性材料可以通过沉积，溅射或喷涂之一直接形成在封装盖上。磁性材料可以固定在集成电路上。

55. 发明授权

US07323948B2 Vertical LC tank device 失效
标题翻译：垂直液相色谱槽装置
公开(公告)号：US07323948B2
公开(公告)日：2008-01-29
申请号：US11161929
申请日：2005-08-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H03B5/18 , H01L29/00
CPC分类号： H03L7/099 , H01L23/5223 , H01L23/5225 , H01L23/5227 , H01L27/0617 , H01L27/0641 , H01L27/08 , H01L27/0811 , H01L28/10 , H01L2924/0002 , H03J3/20 , H01L2924/00
摘要： An LC tank structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.
摘要翻译： LC液箱结构。该结构包括在半导体衬底顶部的一组布线级别，从最靠近衬底的最低配线水平到离衬底最远的最高配线电平彼此堆叠的布线电平; 电感处于最高布线水平，电感器限制在最高布线水平的区域的周边内; 以及形成在基板中的变容二极管，变容二极管完全对准在最高布线水平的区域的周边。该结构可以另外包括在最低布线电平和最高布线电平之间的布线级别的布线级中的电屏蔽。或者，电感器包括磁芯和交替的非磁性导电金属线圈和围绕磁芯的磁性线圈。

56. 发明授权

US07271693B2 On-chip inductor with magnetic core 有权
标题翻译：带磁芯的片上电感
公开(公告)号：US07271693B2
公开(公告)日：2007-09-18
申请号：US11400669
申请日：2006-04-07
申请人： Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01F5/00
CPC分类号： H01F41/046 , H01F17/0006 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An inductor formed on an integrated circuit chip including one or more inner layers between two or more outer layers, inductor metal winding turns included in one or more inner layers, and a magnetic material forming the two or more outer layers and the one or more inner layers. In one embodiment, the magnetic material is a photoresist paste having magnetic particles. In another embodiment, the magnetic material is a series of magnetic metallic strips disposed on each of first and second portions of the two or more outer layers and on each of the one or more inner layers. The series of magnetic metallic strips on the first and second portions form a grid pattern. Other embodiments include an adjustable controlled compound deposit and control windings with adjustable electrical currents.
摘要翻译：形成在集成电路芯片上的电感器，其包括在两个或多个外层之间的一个或多个内层，包括在一个或多个内层中的电感器金属绕组匝以及形成两个或更多个外层的磁性材料和一个或多个内层层。在一个实施例中，磁性材料是具有磁性颗粒的光致抗蚀剂浆料。在另一个实施例中，磁性材料是设置在两个或多个外层的第一和第二部分中的每一个上以及一个或多个内层中的每一个上的一系列磁性金属条。第一和第二部分上的一系列磁性金属条形成网格图案。其他实施例包括具有可调电流的可调控制的化合物沉积和控制绕组。

57. 发明申请

US20070096257A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20070096257A1
公开(公告)日：2007-05-03
申请号：US11163882
申请日：2005-11-02
申请人： Douglas Coolbaugh , Alvin Joseph , Seong-dong Kim , Louis Lanzerotti , Xuefeng Liu , Robert Rassel
发明人： Douglas Coolbaugh , Alvin Joseph , Seong-dong Kim , Louis Lanzerotti , Xuefeng Liu , Robert Rassel
IPC分类号： H01L27/102
CPC分类号： H01L27/0814 , H01L27/0664 , H01L27/0823 , H01L29/0821 , H01L29/7371 , H01L29/868
摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.
摘要翻译：一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。第二掺杂区形成在与第一掺杂区不同的深度。该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

58. 发明申请

US20070052062A1 VERTICAL LC TANK DEVICE 失效
标题翻译：垂直液相色谱箱装置
公开(公告)号：US20070052062A1
公开(公告)日：2007-03-08
申请号：US11161929
申请日：2005-08-23
申请人： Hanyi Ding , Kai Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L29/00
CPC分类号： H03L7/099 , H01L23/5223 , H01L23/5225 , H01L23/5227 , H01L27/0617 , H01L27/0641 , H01L27/08 , H01L27/0811 , H01L28/10 , H01L2924/0002 , H03J3/20 , H01L2924/00
摘要： An LC tank structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.
摘要翻译： LC液箱结构。该结构包括在半导体衬底顶部的一组布线级别，从最靠近衬底的最低配线水平到离衬底最远的最高配线电平彼此堆叠的布线电平; 电感处于最高布线水平，电感器限制在最高布线水平的区域的周边内; 以及形成在基板中的变容二极管，变容二极管完全对准在最高布线水平的区域的周边。该结构可以另外包括在最低布线电平和最高布线电平之间的布线级别的布线级中的电屏蔽。或者，电感器包括磁芯和交替的非磁性导电金属线圈和围绕磁芯的磁性线圈。

59. 发明申请

US20060163688A1 MULTIPLE LAYER STRUCTURE FOR SUBSTRATE NOISE ISOLATION 有权
标题翻译：用于基层噪声隔离的多层结构
公开(公告)号：US20060163688A1
公开(公告)日：2006-07-27
申请号：US10905934
申请日：2005-01-27
申请人： Hanyi Ding , Kai Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L21/76 , H01L29/00 , H01L23/58 , H01L23/552
CPC分类号： H01L21/76264 , H01L23/552 , H01L23/585 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method of forming a semiconductor structure, comprising: providing a substrate having a buried insulative layer and a heavily doped layer; forming a first trench within the substrate around a protected area; filling the first trench with an insulative material, wherein the first trench filled with the insulative material and the buried insulative layer combine to form a high impedance noise isolation that surrounds the protected area on all sides except one side of the protected area to isolate noise from the protected area; forming a second trench within the substrate around the first trench; and filling the second trench with a conductive material, wherein the second trench filled with the conductive material and the heavily doped layer combine to form a low impedance ground path that surrounds the high impedance noise isolation on all sides except one side of the high impedance noise isolation to isolate noise from the protected area.
摘要翻译：一种形成半导体结构的方法，包括：提供具有掩埋绝缘层和重掺杂层的衬底; 在保护区域周围形成衬底内的第一沟槽; 用绝缘材料填充第一沟槽，其中填充有绝缘材料的第一沟槽和埋入绝缘层组合形成高阻抗噪声隔离，围绕保护区域的保护区域，除了保护区域的一侧以隔离噪声保护区; 在所述衬底内围绕所述第一沟槽形成第二沟槽; 以及用导电材料填充所述第二沟槽，其中填充有所述导电材料和所述重掺杂层的所述第二沟槽组合以形成低阻抗接地路径，所述低阻抗接地路径围绕除所述高阻抗噪声的一侧之外的所有侧面上的高阻抗噪声隔离隔离隔离来自保护区的噪音。

60. 发明申请

US20050070101A1 SILICON DIOXIDE REMOVING METHOD 失效
标题翻译：二氧化硅去除方法
公开(公告)号：US20050070101A1
公开(公告)日：2005-03-31
申请号：US10605435
申请日：2003-09-30
申请人： Peter Geiss , Alvin Joseph , Xuefeng Liu , James Nakos , James Quinlivan
发明人： Peter Geiss , Alvin Joseph , Xuefeng Liu , James Nakos , James Quinlivan
IPC分类号： H01L21/302 , H01L21/311 , H01L21/331 , H01L21/461
CPC分类号： H01L29/66242 , H01L21/31116
摘要： A method for removing silicon dioxide residuals is disclosed. The method includes reacting a portion of a silicon dioxide layer (i.e., oxide) to form a reaction product layer, removing the reaction product layer and annealing in an environment to remove oxide residuals. The method finds application in a variety of semiconductor fabrication processes including, for example, fabrication of a vertical HBT or silicon-to-silicon interface without an oxide interface.
摘要翻译：公开了一种去除二氧化硅残留物的方法。该方法包括使一部分二氧化硅层（即氧化物）反应以形成反应产物层，除去反应产物层并在环境中退火以除去氧化物残余物。该方法应用于各种半导体制造工艺中，包括例如制造垂直HBT或无硅氧化物界面的硅 - 硅界面。

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